WO2008032549A1

WO2008032549A1 - Semiconductor storage device

Info

Publication number: WO2008032549A1
Application number: PCT/JP2007/066509
Authority: WO
Inventors: Koichi Takeda
Original assignee: Nec Corporation
Priority date: 2006-09-13
Filing date: 2007-08-21
Publication date: 2008-03-20
Also published as: JPWO2008032549A1

Abstract

Provided is a data writing method for reading stored data at first and then performing a writing action. By a write data selecting circuit for switching the data to be written in an SRAM cell, the write data from the outside is written in the SRAM cell selected with a column address, and the stored data of the SRAM cell itself is written back in the SRAM cell unselected with the column address. This constitution makes it possible to arrange the memory cells of the different column addresses adjacent to each other.

Description

Semiconductor memory device

Technical field:

The present invention relates to a semiconductor memory device, and more particularly to a method for writing data in a static random access memory (SRAM) cell having a write write line. Background art: calligraphy

In recent years, semiconductor devices have become larger and faster, and many functions have been incorporated into a system. These semiconductor devices are miniaturized to improve the operating speed by increasing the scale and speed. In addition to the various functional blocks including the CPU, various storage devices are mixed for systemization. Even in the storage devices embedded in these systems LSI, for example, SRAMs embedded in applications such as cache memory, miniaturization of the transistors that make up the SRAM enables large-scale and high-speed operation. ing.

A conventional SRAM will be described with reference to the drawings. Figure 1 shows a conventional SRAM memory cell consisting of six transistors (hereinafter referred to as an SRAM cell). When the word line WL is at a low potential, two CMOS (Complementary Metal Oxide Semiconductor) inverter circuits form a loop, so that data can be stored stably. The first inverter circuit is composed of a load transistor P1 and a drive transistor N1, and the second inverter circuit is composed of a load transistor P2 and a drive transistor N2. That is, one CMOS inverter circuit receives the storage node V 1 as an input and outputs inverted data of the data stored in the storage node V 1 to the storage node V 2. The other CMOS inverter circuit receives the storage node V 2 as an input and outputs inverted data stored in the storage node V 2 to the storage node V 1. When access is made and the node line WL is at a high potential, the access transistors N 3 and 4 are turned on, whereby the data stored in the memory nodes V 1 and V 2 are charged to the high potential BL 1 And output to BL2 for memory read operation. In addition, according to the write data, one bit line is discharged to a low potential, and data is input from the bit line pair BL 1 and BL 2 to the storage nodes V 1 and V 2, thereby performing a memory write operation.

Figure 2 shows an SRAM cell array arranged in two dimensions. In SRAM, it is possible to access any cell by using word line WL and bit line pair (B L 1, B L 2). In the case of a read operation, by activating the word line WL corresponding to the row address, the stored data is output to the bit line pair (B L 1 and BL 2) in all SRAM cells having the same row address. Next, the bit line pair corresponding to the column address is selected by the selector and input to the sense amplifier SA. The sense amplifier is activated and the input signal is amplified, completing the read operation of the data stored in any cell. A condition for achieving stable column selection in a read operation is that a sufficient read margin is ensured in all SRAM cells.

On the other hand, in the case of a write operation, the write driver outputs data to the bit line pair corresponding to the column address from all the bit line pairs charged to a high potential. For example, when the write data is “1” level, the bit line BL 1 is discharged to a low potential, and when the write data is “0” level, the bit line BL 2 is discharged to a low potential. Next, by activating the word line corresponding to the row address, write data is input to any selected SRAM cell, and the write operation is completed.

At this time, in the SRAM cell activated by the row address and not selected by the column address, the bit line pairs to be connected are both at a high potential, and a pseudo read operation is performed. The conditions for achieving stable column selection in a write operation are that a sufficient write margin is ensured in the SRAM cell in which the write operation is performed, and a sufficient read margin in the SRAM cell in which the pseudo read operation is performed. Is to be secured. However, in S RAM after 9 Onm generation, As transistors are scaled down for large-scale and high-speed operation, the variation width of transistor drive capability increases, the read margin is greatly degraded, and the problem that the stored data is destroyed due to read operation becomes obvious. ing. If the transistor threshold voltage is increased to improve the read margin, the write margin deteriorates, making it difficult to complete the write operation.

Reference 1 (Shang et al, "Stable SRAM Cell Design for the 32nra Node and Beyond," VLSI Tech. Papers, pp.128-129, Jun.

2005) and reference 2 (K. Takeda et al, "A Read-Static-Noise-Margin-Free SRAM Cell for Low-VDD and High-Speed Applications," ISSCC Dig. Tech. Papers, pp.478-479, Feb (2005) has taken measures to greatly increase the read margin. For example, in the SRAM cell of Reference 1 shown in Fig. 3, two read transistors (N6, N7) are added to the conventional SRAM cell, and the word line is separated into read-only read line RWL and write-only read line WWL. is doing. By activating only the read-only word line RWL during the read operation, the stored data is prevented from being destroyed during the read operation. During a write operation, only the write-only word line WWL is activated. At this time, since the write operation is performed in all the SRAM cells connected to the word line WWL, it is not possible to perform the power ram selection in the SRAM cell array which has been conventionally performed in the SRAM.

In the SRAM cell of Reference 2 shown in Fig. 4 and Fig. 5, the holding control transistor N5 is added to improve the read margin. As shown in Fig. 6, one SRAM cell array is composed of multiple SRAM cells with the same column address, and only the SRAM cell array corresponding to the column address is activated using the sub-wire driver. When configuring an SRAM cell array, SRAM cells are arranged in the horizontal direction by the data bit width, and the vertical direction corresponds to the row address as in the conventional SRAM. The problem with configuring an SRAM cell array with memory cells with the same column address is that the number of snores in the lateral direction of the SRAM cell array cannot be made larger than the data bit width. Therefore, the degree of freedom when changing the memory capacity is low, and the resistance to multi-bit errors caused by cosmic rays and alpha rays is low. There is a problem.

Reference 3 (K. Osada et al, "Cosmic-Ray Multi-Error Immunity for SRAM, Based on Analysis of the Parasitic Bipolar Effect," VLSI Circuit.

In Papers, pp. 255-258, Jun. 2003), a cell array with a different column address is placed adjacent to each other to form a RAM cell array. Limited to one, ECC (Error

It describes that error bits can be easily corrected by “Checking and Correcting”. On the other hand, when a SRAM cell array is configured with SRAM cells having the same column address as in Non-Patent Document 2, it is difficult to correct a multi-bit error even if ECC is used. Disclosure of the invention:

Problems to be solved by the invention

As described above, the conventional SRAM cell composed of six transistors has a problem that a read margin for realizing a stable read operation is deteriorated by miniaturization and voltage reduction. In References 1 and 2, a word line for writing was added to improve only the reading margin without degrading the writing margin. However, since the write operation is always performed when the write word line is operated, the floor plan must be changed so that the SRAM cell array is composed of the SRAM cells having the same column address, and A new problem arises that the resistance to multi-bit errors deteriorates.

The present invention has been made to remedy the above-described problems, and even if a write word line is operated during a write operation, stored data is stably stored in a SRAM cell that is not selected by a column address. An object of the present invention is to provide a semiconductor memory device provided with a data writing method capable of being held.

Means for solving the problem

In order to solve the above-described problems, the present application basically employs the techniques described below. In addition, applied technologies that can be variously modified without departing from the technical spirit However, it goes without saying that they are included in the present application.

A semiconductor storage device according to the present invention includes a first storage node having a first storage node and a second storage node, the second storage node being an input and the first storage node being an output. A circuit, a second inverter circuit having the first storage node as an input and the second storage node as an output, and a first and a second accessing the first and second storage nodes, respectively. A plurality of SRAM cells having two access means and two-dimensionally arranged,

Select one of the write word line activated during writing, the read word line activated during read, the read data from the SRAM cell during write, and the write data input from the outside And a write data selection circuit.

In the semiconductor memory device of the present invention, at the beginning of the write operation, the read data read from the SRAM cell selected by the row address is activated by activating the write word line selected by the port address. It is characterized by being written back to the SR AM cell.

The write data selection circuit of the semiconductor memory device of the present invention outputs either the read data or the write data to a write bit line of a SRAM cell based on a selection signal.

In the semiconductor memory device of the present invention, the selection signal is activated or deactivated by a column address.

The semiconductor memory device according to the present invention is characterized in that the write data is written to the SRAM cell selected by the column address, and the read data is written back to the SRAM cell not selected by the column address. To do. The SRAM cell of the semiconductor memory device of the present invention is characterized by further comprising two read-only transistors.

In the semiconductor memory device of the present invention, the two read-only transistors are connected in series between a read bit line and a ground potential, and the gate of the transistor connected to the read bit line is connected to the read word line. Connected to the ground potential. The continued transistor goot is connected to the second storage node.

In the semiconductor memory device of the present invention, the read bit line is input to a sense amplifier, the read data is output from the sense amplifier, and the read data and the write data are input to the write data selection circuit, Either one of the data is output to the write bit line.

The semiconductor memory device of the present invention is characterized in that the SRAM cell further includes a transistor connected in series to a drive transistor of the second inverter circuit, and a gate connected to an inverting wire.

In the semiconductor memory device of the present invention, the bit line connected to the first access transistor is input to a sense amplifier, the read data is output from the sense amplifier, and the write data selection circuit is connected to the data and The write data is input, and one of the data is output to a write bit line.

The writing method of the semiconductor memory device according to the present invention includes a first storage node and a second storage node, wherein the second storage node is an input and the first storage node is an output. An inverter circuit, a second inverter circuit having the first storage node as an input and the second storage node as an output, and a first accessing the first and second storage nodes, respectively. And a second access means, and a semiconductor memory device in which a plurality of SRAM cells having a two-dimensional arrangement are arranged, the SRAM cell in which the read word line selected by the row address is activated at the beginning of the write operation. Memory data is read as read data, and then the write word line selected by the row address is activated, and the read data or the write data input from the outside is activated. One of the data is written into the SRAM cell.

In the writing method of the semiconductor memory device of the present invention, the write data is written to the SRAM cell selected by the column address, and the read data is written back to the SRAM cell not selected by the column address. Features The

The invention's effect

The semiconductor memory device of the present application includes an SRAM cell having a write write line, and in a write operation, a read operation is performed in advance and then a write is performed. As a writing method, the storage data of the SRAM cell is first read, and the read storage data is written back to the SRAM cell not selected by the column address. On the other hand, the input external data is written to the SRAM cell selected by the column address.

When an SRAM cell array is configured by the writing method of the present invention, memory cells having different column addresses can be arranged adjacent to each other as in the conventional SRAM. This increases the degree of freedom when configuring the SRAM cell array, and improves the resistance to multi-bit errors caused by cosmic rays and alpha rays. Brief description of the drawings:

Figure 1 is a circuit diagram of a conventional 6-transistor SRAM cell.

Figure 2 shows the SR when SRAM cells with different column addresses are placed adjacent to each other.

It is a figure which shows AM cenoalay.

Figure 3 is a circuit diagram of a conventional 8-transistor SRAM cell.

Figure 4 is a circuit diagram of a conventional 7-transistor SRAM cell.

FIG. 5 is a circuit diagram of another form of a conventional 7-transistor SRAM cell. Figure 6 shows an SRA with adjacent SRAM cells with the same column address.

It is a figure which shows M cell array.

FIG. 7 is a first memory circuit block configuration diagram when writing to the 8-transistor SRAM cell according to the present invention.

FIG. 8 is an operation waveform diagram for explaining the write operation when the column address in FIG. 7 is selected.

9 is selected by column address in the memory circuit block diagram of FIG. It is an operation | movement waveform diagram explaining the write-in operation | movement when there is nothing.

FIG. 10 is a second memory circuit block configuration diagram in the case of writing to the 8-transistor SRAM cell according to the present invention.

FIG. 11 is a block diagram of a third memory circuit when writing to an 8-transistor SRAM cell according to the present invention.

FIG. 12 is a block diagram of the fourth memory circuit when writing to an 8-transistor SRAM cell according to the present invention.

FIG. 13 is a block diagram of a fifth memory circuit block for writing to an 8-transistor SRAM cell according to the present invention.

FIG. 14 is a circuit diagram of a sense amplifier used in the memory circuit block configuration diagram of FIG.

FIG. 15 is an operation waveform diagram for explaining the write operation when the column address is selected in the memory circuit block configuration diagram of FIG.

FIG. 16 is an operation waveform diagram for explaining a write operation when the column address is not selected in the memory circuit block configuration diagram of FIG.

FIG. 17 is another circuit diagram of the sense amplifier used in the memory circuit block diagram of FIG.

FIG. 18 is a sixth memory circuit block configuration diagram when writing to a 7-transistor SRAM cell according to the present invention.

FIG. 19 is an operation waveform diagram for explaining a write operation when a column address is selected in the memory circuit block configuration diagram of FIG.

FIG. 20 is an operation waveform diagram for explaining the write operation when the column address is not selected in the memory circuit block configuration diagram of FIG.

FIG. 21 is a block diagram of a seventh memory circuit in the case where data is written to a 7-transistor SRAM cell according to the present invention.

FIG. 22 is an eighth memory circuit block configuration diagram when writing to the 7-transistor SRAM cell according to the present invention.

Figure 23 shows the case of writing to a 7-transistor SRAM cell according to the present invention. FIG. 10 is a ninth memory circuit block configuration diagram;

FIG. 24 is a block diagram of a tenth memory circuit block when data is written to a 7-transistor SRAM cell according to the present invention. Best Mode for Carrying Out the Invention:

A writing method of the present invention and a memory circuit block configuration for realizing the writing method will be described in detail with reference to the drawings.

(Example 1)

A first embodiment of the present invention will be described with reference to FIGS. FIG. 7 is a block diagram of a first memory circuit having eight transistor SRAM cells. 8 and 9 show operation waveforms for explaining the operation of the writing method of the present invention. Figure 8 shows the operation waveform when external write data is written to the SRAM cell selected by the force selection signal. Figure 9 shows the memory of the cell itself in the unselected SRAM cell by the column selection signal. It is an operation waveform when data is written back again.

The memory circuit block diagram shown in FIG. 7 includes a plurality of SRAM circuit blocks 41 and a data input / output circuit 63. The SRAM circuit block 41 is a SRAM circuit block that is configured by a plurality of SRAM cells 11 and sense amplifiers 21 each composed of eight transistors, and is arranged two-dimensionally. The SRAM cell 1 1 includes a first inverter circuit composed of a load transistor P 1 and a drive transistor N1, a second inverter circuit composed of a load transistor P 2 and a drive transistor N2, and an access transistor N 3. N4 and read transistors N6 and N7. The first inverter circuit receives the storage node V 2 and outputs the inverted data to the storage node V 1. The second inverter circuit receives the storage node V 1 as an input and outputs the inverted data to the storage node V 2. This SRAM cell 11 is an 8-transistor SRAM cell composed of 8 transistor forces as shown in FIG.

SRA ^ H? 1 1 includes read-only word line RWL, write-only word line W WL, write bit line pair (WBL 1, WB L 2), and read bit line RBL. Have. The read-only word line RWL is connected to the gate of the read transistor N 7, and the write-only word line WWL is connected to the gates of the access transistors N 3 and N 4. The write bit line pair (WBL 1, WBL 2) is connected to access transistors N3, N4. Read transistors N6 and N7 are connected in series between the read bit line RB L and the ground potential. The drain, source, and gate of transistor N 6 are connected to the source of transistor N 7, ground potential, and storage node V 2, respectively. The drain, source, and gate of transistor N 7 are connected to read bit line RBL, the drain of transistor N6, and read-only word line RWL, respectively.

At the time of reading, the read-only word line RWL is activated, the information in the storage node V2 is inverted, and is read to the read bit line RBL. At the time of writing, the write-only word line WWL is activated, and writing to the SRAM cell is performed by the write data from the write bit line pair (WBL 1, WBL 2). The sense amplifier 21 amplifies the signal from the read bit line RBL of the SRAM cell and outputs it to the read data line DL. The global data signal lines wired in common between the plurality of SRAM circuit blocks 41 are the read data line DL and the write bit lines WB L 1 and WB L 2.

The data input / output circuit 63 is a data input / output circuit that transmits / receives data to / from the SRAM circuit block 41 arranged two-dimensionally. The data input / output circuit 63 includes a read data selection circuit 61, a write data selection circuit 31, and a CMOS inverter IV1. The read data selection circuit 61 selects one of the plurality of read data lines DL by the column selection signal YA according to the column address and outputs it as read data DO. The write data selection circuit 31 selects either the data line DL read from the SRAM cell or the externally input write data DI by the column selection signal YA and outputs it to the write bit line WBL 1. The CMOS inverter IV 1 inverts the output signal from the write data selection circuit 31 and outputs it to the other write bit line WBL 2. Figures 8 and 9 show the operation waveforms for explaining the operation of this circuit during writing. The arbitrary read mode line RWL of the SRAM circuit block 41 selected by the row address is activated, and the data stored in the SRAM cell 11 is output to the read bit line RBL. The sense amplifier 21 amplifies the signal output to the read bit line RBL, and the amplified read data is output to the read data line DL. In the data input / output circuit 63, in the write data selection circuit 31 selected by the column address, the column selection signal YA is at "1" level, and the write data DI is selected and the write bit line WBL 1 as shown in FIG. , Output to WBL 2. In the write data selection circuit 31 not selected by the column address, the column selection signal YA is at the “0” level, and the read data line DL is selected and output to the write bit lines WBL 1 and WBL 2 as shown in FIG.

Next, the write mode line WWL of the SRAM cell 11 in which the read word line RWL is activated is activated. As shown in FIG. 8, the write data DI is written to the SRAM cell 11 selected by the column address. As shown in FIG. 9, the signal output to the read data line DL, that is, the stored data of the SRAM cell 11 itself is written back to the SRAM cell 11 not selected by the power address. Therefore, stable data can be written only to the 31 8] ^ cell 11 selected by the column address without destroying the stored data of the SRAM cell 11 1 not selected by the column address. Rewriting the stored data again in this way is called write back. In the write method of the present embodiment, a write data signal is written to the SRAM cell selected by the column address among the SRAM cells accessed to the write state by the row address. Read data is written back to SRAM cells that are not selected by the column address. When an SRAM cell array is configured by this writing method, memory cells having different column addresses can be arranged adjacent to each other. Therefore, it is possible to obtain a semiconductor memory device having flexibility in the configuration of the SRAM cell array and having resistance against multi-bit errors. In FIG. 7, the write data selection circuit 31 drives the write bit line WBL 1 and inverts the write bit line WBL 1 using the CMOS inverter I VI. Output to BL2. However, the present invention is not limited to this, and depending on the configuration of the write data selection circuit 31, the relationship between the write bit lines WBL 1 and WBL 2 can be reversed.

(Example 2)

A second embodiment of the present invention will be described with reference to FIG. FIG. 10 is a block diagram of a second memory circuit block having eight transistor SRAM cells. In this embodiment, the inverted data of the write data is generated in the SRAM circuit block.

The SRAM circuit block 42 is composed of a plurality of SRAM cells 11 composed of eight transistors, a sense amplifier 21, and a CMO S NOR gate NR 1 that drives one of the write data lines. The inverted data signal of the write data is generated by the CMOS NOR gate NR1. The SRAM sensing 1 1 and the sense amplifier 21 have the same configuration as that of the first embodiment, and a description thereof is omitted. The output data from the write data selection circuit 31 and the write selection signal WEB are input to the CMOS NOR gate NR1, and the output signal is output to the write bit line WBL2. The write selection signal WEB is "0" level when writing.

The data input / output circuit 64 is a data input / output circuit that transmits / receives data to / from the SRAM circuit block 42 arranged two-dimensionally. The data input / output circuit 64 selects one of the read data lines DL according to the column address and selects one of the read data lines DL and the write data DI and writes one of them. It consists of a write data selection circuit 31 that outputs to the bit line WB L 1. The global data signal lines wired in common between the plurality of SRAM circuit blocks 42 are the read data line DL and the write bit line W B L 1.

The operation at the time of writing in this embodiment will be described. The arbitrary read mode line RWL of the SRAM circuit block 42 selected by the row address is activated, and the storage data of the SRAM cell 11 is output to the read bit line RBL. The sense amplifier 21 amplifies the data signal output to the read bit line RBL and amplifies it. The read data is output to the read data line DL. In the data input / output circuit 64, in the write data selection circuit 31 selected by the column address, the column selection signal YA is at the “1” level, and the write data DI is selected and output to the write bit line WBL 1. In the write data selection circuit 31 which is not selected by the column address, the column selection signal YA is at "0" level, the read data line DL is selected and output to the write bit line WB L 1.

In the SRAM circuit block 42 selected by the address, the write selection signal WEB is activated to "0" level, and the CMOS NOR gate NR1 is the inverted signal of the signal output to the write bit line WB L1. Is output to the write bit line WBL2. In the SRAM circuit block 42 not selected by the row address, the write selection signal WEB is at the “1” level, and the write bit line W BL2 remains at the “0” level.

Next, the write mode line WWL of the SRAM cell 11 in which the read mode line RWL is activated is activated. The write data DI is written to the SRAM cell 11 selected by the column address. In the SRAM cell 11 which is not selected by the column address, the signal output to the read data line DL, that is, the storage data of the SRAM cell 11 itself is written back. Therefore, it is possible to perform stable data writing only to the SRAM cell 11 selected by the column address without destroying the stored data of the SRAM cell 11 not selected by the column address.

In the write method of the present embodiment, a write data signal is written to the SRAM cell selected by the column address among the SRAM cells accessed in the write state by the mouth address. Read data is written back to SRAM cells that are not selected by the column address. When an SRAM cell array is configured by this writing method, memory cells having different column addresses can be arranged adjacent to each other. Therefore, it is possible to obtain a semiconductor memory device having flexibility in the configuration of the SRAM cell array and having resistance against multi-bit errors. In FIG. 10, the write data selection circuit 31 writes the global data signal line. Only the bit line WB L 1 is driven, and this is inverted using the CMOS NOR gate NR 1 and output to the write bit line WBL 2. However, the present invention is not limited to this, and depending on the configuration of the write data selection circuit 31, the relationship between the write bit lines WB L 1 and W BL 2 can be reversed.

(Example 3)

A third embodiment of the present invention will be described with reference to FIG. FIG. 11 is a block diagram of a third memory circuit block having eight transistor SRAM cells. In this embodiment, the write data selection circuit 31 and the CMOS inverter IVI in the data input / output circuit 63 of the first embodiment are distributed in the 8-transistor SRAM circuit block 43.

The SRAM circuit block 43 includes a plurality of SRAM cells 11 including eight transistors, a sense amplifier 21, a write data selection circuit 32, and a CMOS inverter IV2. The SRAM cell 11 and the sense amplifier 21 have the same configuration as in the first embodiment, and a description thereof is omitted. The write data selection circuit 3 2 selects one of the read data line DL and the write data line D I 2 and outputs it to one write bit line WB L 1. The CMOS inverter I V2 inverts the output signal from the write data selection circuit 32 and outputs it to the other write bit line WB L 2.

The data input / output circuit 65 is a data input / output circuit that transmits / receives data to / from the SRAM circuit block 43 arranged two-dimensionally. The data input / output circuit 65 includes a read data selection circuit 61 that selects one of a plurality of read data lines DL according to the column address, a write data drive circuit 62 that outputs the write data DI to the write data line DI 2, and Consists of. The global data signal lines commonly wired between the plurality of SRAM circuit blocks 43 are the read data line DL and the write data line D I 2.

The operation at the time of writing of this circuit will be described. The arbitrary read mode line RWL of the SRAM circuit block 43 selected by the address is activated, and the storage data of the SRAM cell 11 is output to the read bit line RBL. Sensea The amplifier 21 amplifies the data signal output to the read bit line RBL, and the amplified read data is output to the read data line DL. In the write data selection circuit 32 selected by the column address, the selection signal YS is “1” level, the write data line DI 2 is selected and output to the write bit lines WB L 1 and WBL 2. In the write data selection circuit 32 that is not selected by the column address, the selection signal Y is at “0” level, the read data line DL is selected and output to the write bit lines WBL 1 and WBL 2. The write selection circuit 32 of the SRAM circuit block 43 not selected by the row address does not select either the read data line DL or the write data line DI2.

Next, the write mode line WWL of the SRAM cell 11 in which the read word line RWL is activated is activated. The write data DI is written to the SRAM cell 11 selected by the column address. In the SRAM cell 11 which is not selected by the column address, the signal output to the read data line DL, that is, the storage data of the SRAM cell 11 itself is written back. Therefore, it is possible to perform stable data writing only to the SRAM cell 11 selected by the column address without destroying the stored data of the SRAM cell 11 not selected by the column address.

In the write method of the present embodiment, a write data signal is written to the SRAM cell selected by the column address among the SRAM cells accessed to the write state by the row address. Read data is written back to SRAM cells that are not selected by the column address. When an SRAM cell array is configured by this writing method, memory cells having different column addresses can be arranged adjacent to each other. Therefore, it is possible to obtain a semiconductor memory device having flexibility in the configuration of the SRAM cell array and having resistance against multi-bit errors. In FIG. 11, the write data selection circuit 32 drives the write bit line WBL 1, inverts it using the CMOS inverter IV 2, and outputs it to the write bit line WBL 2. However, the present invention is not limited to this. Depending on the configuration of the write data selection circuit 32, the relationship between the write bit lines WB L 1 and WB L 2 may be reversed. It is possible.

(Example 4)

A fourth embodiment of the present invention will be described with reference to FIG. FIG. 12 is a block diagram of a fourth memory circuit block having eight transistor SRAM cells. In this embodiment, the sense amplifier is operated only at the time of reading.

The SRAM circuit block 44 includes a plurality of SRAM cells 11 composed of eight transistors, a sense amplifier 22, a write data selection circuit 33, and a CMOS inverter IV2. The SRAM cell 11 has the same configuration as that of the first embodiment, and a description thereof is omitted. The sense amplifier 22 receives the sense amplifier activation signal RE and operates only during a read operation. The write data selection circuit 33 selects one of the read bit line RB L and the write data line DI 2 and outputs it to one write bit line WB L 1. The CMOS inverter I V 2 inverts the output signal from the write data selection circuit 33 and outputs it to the other write bit line WB L 2.

The data input / output circuit 65 is a data input / output circuit that transmits / receives data to / from the SRAM circuit block 44 arranged two-dimensionally. The data input / output circuit 65 includes a read data selection circuit 61 that selects one of a plurality of read data lines DL according to the column address, a write data drive circuit 62 that outputs the write data DI to the write data line DI 2, and Consists of. The global data signal lines commonly wired between the plurality of SRAM circuits Plock 44 are the read data line DL and the write data line D I 2.

The operation at the time of writing of this circuit will be described. The arbitrary read mode line RWL of the SRAM circuit block 44 selected by the address is activated, and the stored data of the SRAM cell 11 is output to the read bit line RBL. The sense amplifier activation signal RE is set to "0" level, and the sense amplifier 22 is operated only during a read operation. In the write data selection circuit 33 selected by the column address, the selection signal YS is at “1” level, the write data line DI 2 is selected and output to the write bit lines WBL 1 and WBL 2. By column address In the unselected write data selection circuit 33, the selection signal YS is at "0" level, the read bit line RBL is selected and output to the write bit lines WBL 1 and WBL2. In the SRAM circuit block 44 not selected by the row address, the selection signal YS is at the “0” level, and the write selection circuit 33 selects the read bit line RBL charged to the “1” level.

Next, the write mode line WWL of the SRAM cell 11 in which the read word line RWL is activated is activated. The write data DI is written to the SRAM cell 11 selected by the column address. In the SRAM cell 11 which is not selected by the column address, the signal output to the read bit line RBL, that is, the stored data of the SRAM cell 11 itself is written back. Therefore, in the SRAM cell 11 that is not selected by the power address, it is possible to perform stable data writing only to the SRAM cell 11 selected by the column address without destroying the stored data.

In the write method of the present embodiment, a write data signal is written to the SRAM cell selected by the column address among the SRAM cells accessed in the write state by the mouth address. Read data is written back to SRAM cells that are not selected by the column address. When an SRAM cell array is configured by this writing method, memory cells having different column addresses can be arranged adjacent to each other. Therefore, it is possible to obtain a semiconductor memory device having flexibility in the configuration of the SRAM cell array and having resistance against multi-bit errors. In FIG. 12, the write data selection circuit 33 drives the write bit line WBL 1 and inverts it using the CMOS inverter I V2 and outputs it to the write bit line WBL 2. However, the present invention is not limited to this, and depending on the configuration of the write data selection circuit 33, the relationship between the write bit lines WBL 1 and WBL 2 may be reversed.

(Example 5)

A fifth embodiment of the present invention will be described with reference to FIGS. FIG. 13 is a block diagram of a fifth memory circuit having an 8-transistor SRAM cell. Book The configuration is an example of a circuit configuration in which the data line DL is used for both input and output. FIG. 14 is a block diagram of the sense amplifier. FIG. 15 and FIG. 16 show operation waveforms for explaining the operation of the writing method of the present invention. Figure 15 shows the operation waveform when the externally selected write data is written by the column selection signal. Figure 16 shows the operation when the stored data is written back to the SRAM cell again by the column selection signal. It is a waveform. Figure 17 shows the configuration of a sense amplifier that can be used for two SRAM cell arrays.

The SRAM circuit block 45 is composed of a plurality of SRAM memory 11, a sense amplifier 23, a CMOS NOR gate NR 1, and a CMOS inverter I V2 including eight transistors. 31 8] ^ Cell 1 1 has the same configuration as in the first embodiment. The sense amplifier 23 is activated by the sense amplifier activation signal REB, receives the read bit line RBL, and outputs the output to the data line DL. The CM OS NOR gate NR 1 receives the data line DL and the write selection signal WEB, inverts the signal on the data line DL, and outputs it to the write bit line WBL2. The CMOS inverter I V 2 inverts the output signal of the CMOS NOR gate NR 1 and outputs it to the other write bit line WB L 1.

The data input / output circuit 66 is a data input / output circuit that transmits / receives data to / from the SRAM circuit block 45 arranged two-dimensionally. When the column selection signal Y A is input and selected, external write data DI is output to the data line DL. If not selected, the sense amplifier 23 is activated by the sense amplifier activation signal REB, and the output signal of the sense amplifier 23 is output to the data line DL.

The operation at the time of writing in this embodiment will be described. The arbitrary read node line RWL of the SRAM circuit block 45 selected by the row address is activated, and the storage data of the SRAM memory 11 is output to the read bit line RBL.

In the SRAM circuit block 45 selected by the column address, the sense amplifier activation signal REB is “1” level (or floating state), and the write selection signal WEB is “0” level. The sense amplifier activation signal REB is "1" level. Since it is a bell, the sense amplifier 23 stops its operation. Write data DI is output from the data input / output circuit 66 to the data line DL. The write data DI output to the data line DL is output to the write bit lines WB L 1 and WB L 2 by the CMOS NOR gate gate NR 1 and the CMOS inverter IV 2. By stopping the operation of the sense amplifier 23, data collision on the data line DL can be avoided.

In the SRAM circuit block 45 that is not selected by the column address, the write selection signal WEB is at "0" level and the sense amplifier activation signal REB is at "0" level. The sense amplifier activation signal REB is at “0” level, and the sense amplifier 23 is operated to output the storage data of the SRAM cell to the data line DL. At this time, write data DI is not input. The write selection signal WEB is activated and is at "0" level, and the read data output from the sense amplifier 23 to the read data line DL is written to the CMO S NOR gate NR 1 and I V2 by the write bit line WBL 1, Output to WBL 2.

In the SRAM circuit block 45 that is not selected by the address, the word line remains inactive and the write selection signal WEB is at "1" level. The output of the CMO S NOR gate NR 1 is fixed at "0" level, and the write bit lines W B L 1 and W L L 2 are also fixed at "1" level and "0" level, respectively. Next, the write mode line WWL of the SRAM cell 11 in which the read word line RWL is activated is activated. The write data DI is written to the SRAM cell 11 selected by the column address. The SRAM cell 11 not selected by the column address is written back with the signal output to the data line DL, that is, the stored data of the SRAM cell 11 itself. Therefore, it is possible to perform stable data writing only to the SRAM cell 11 selected by the column address without destroying the storage data of the SRAM cell 11 not selected by the column address.

In Figure 13 CMOS NOR gate NR 1 drives write bit line WB L 2 and inverts it using CMOS inverter I V2 to write bit line W Outputs to BL 1. However, the present invention is not limited to this, and depending on the configuration of the sense amplifier 23, the relationship between the write bit lines WB L 1 and WB L 2 may be reversed.

FIG. 14 shows a specific example of the sense amplifier 23. Precharge PMOS transistor P 10 that charges read bit line RBL to "1" level, CMOS inverter I V3 that amplifies read data output to read bit line RBL, and amplified data is output to data line DL It consists of NMOS transistor N10. The operation of the sense amplifier 23 can be stopped by connecting the source terminal of the NMOS transistor N10 to the write selection signal REB and making it floating.

Figures 15 and 16 show the operation waveforms for explaining the write operation when this circuit is used. As shown in FIG. 15, write data DI from the outside is output to the data line DL from the data input / output circuit 66 to the SRAM circuit block 45 selected by the column address. At this time, the sense amplifier activation signal REB is controlled to be in a floating state. This avoids data collisions that occur on the read data line DL when the read data is at the "0" level and the write data is at the "1" level. Instead, the NMOS transistor N 10 that is turned on causes charge to flow from the read data line D to the sense amplifier activation signal REB, and the potential of the sense amplifier activation signal REB slightly increases. Write word line WWL is activated, and external write data DI is written to the SRAM cell.

As shown in FIG. 16, “0” level is output from the data input / output circuit 66 to the sense amplifier activation signal REB in the SRAM circuit block 45 not selected by the column address, and the sense amplifier operates. The SRAM circuit block 45 not selected by the column address performs a read operation. The read data output to the data line DL is output to the write bit lines WBL 1 and WBL 2, and the write operation is completed without destroying the stored data.

Another form of the sense amplifier 23 is shown in FIG. Sense amplifier shown in Figure 14 Unlike 23, it is used in a configuration where one sense amplifier is placed between two SRAM cell arrays. Precharge PMO S transistors P 1 1 and P 12 for charging the read bit lines RB L 1 and RBL 2 of each of the two SRAM cell arrays to one of the read bit lines RB L 1 and RB L 2 It comprises an amplified CMOS NAND gate ND 1 and an NMOS transistor N 10 that reads the amplified data and outputs it to the data line DL. By using this configuration, the number of sense amplifiers can be reduced and the area can be reduced.

Also in the writing method of the present embodiment, the write data signal is written to the SRAM cell selected by the column address among the SRAM cells accessed in the write state by the mouth address. Read data is written back to SRAM cells that are not selected by the column address. When an SRAM cell array is configured by this writing method, memory cells having different column addresses can be arranged adjacent to each other. Therefore, it is possible to obtain a semiconductor memory device having flexibility in the configuration of the SRAM cell array and having resistance against multi-bit errors.

(Example 6)

An embodiment of the present invention will be described with reference to FIGS. FIG. 18 is a block diagram of a sixth memory circuit having a seven-transistor SRAM cell. 19 and 20 show operation waveforms for explaining the operation of the writing method of the present invention. Figure 19 shows the operation waveform when writing externally written data, selected by the column selection signal. Figure 20 shows the operation waveforms when the memory data is written back to the SRAM cell after being deselected by the column selection signal.

The SRAM circuit block 51 is composed of a plurality of SRAM cells 12, a sense amplifier 21, and a write NMOS transistor N 11 composed of seven transistors. The SRAM sensor 12 includes a first inverter circuit composed of a load transistor P1 and a drive transistor N1, a second inverter circuit composed of a load transistor P2 and a drive transistor N2, and an access transistor. N3 and N4, and the holding control transistor N5 of the second inverter circuit. The holding control transistor N 5 is connected to the load transistor P 2 as shown in FIG. And drive transistor N 2, or between drive transistor N 2 and ground potential as shown in FIG. This is a 7-transistor SRAM cell composed of 7 transistors.

The 7-transistor SRAM Sennore has a word line WL and an inverted word line WLB that is an inversion of the word signal, a write-only word line WWL, a bit line BL, and a write bit line WBL. The node line WL is connected to the gate of the access transistor N 3, the write node line WWL is connected to the gate of the access transistor N 4, and the inverted word line WLB is connected to the gate of the holding control transistor N 5. Bit line BL and write bit line WBL are connected to access transistors N3 and N4. The sense amplifier 21 receives the bit line BL and outputs it to the data line DL. The write NMOS transistor Nl 1 uses the write selection signal WE as a gate input to transfer data between the bit line BL and the data line WBLB.

At the time of reading, the node line WL is activated, the data of the storage node V 1 is read and read to the bit line BL. When writing, the word lines WL and WWL are activated, and writing is performed from the bit line BL and the write bit line WBL. At the time of reading and writing, the inverted word line WLB is deactivated and the second inverter circuit is turned off. By turning off the second inverter circuit, the read and write operation margin can be expanded. Since these SRAM cells are described in detail in W0-2005 / 041203 filed by the inventor of the present application, detailed description thereof is omitted. The data input / output circuit 63 is a data input / output circuit that transmits / receives data to / from the SRAM circuit block 51 arranged two-dimensionally. The data input / output circuit 63 includes a read data selection circuit 61, a write data selection circuit 31, and a CMOS inverter IV1. The read data selection circuit 61 selects one of the plurality of read data lines DL according to the column address. The write data selection circuit 31 selects one of the read data line DL and the write data DI and outputs it to the write data line WB LB. The CMOS inverter IV 1 inverts the output signal from the write data selection circuit 31 and outputs it to the write bit line WBL. A global wiring that is commonly wired between multiple SRAM circuit blocks 51 The data signal lines are a read data line DL, a write data line WB LB, and a write bit line WB L.

Figures 19 and 20 show the operation waveforms for explaining the operation of this circuit during writing. The arbitrary word line WL of the SRAM circuit block 51 selected by the address is activated, and the storage data of the SRAM cell 12 is output to the read bit line BL. At this time, in order to prevent the stored data from being destroyed at the time of reading, the inversion word line WLB is also simultaneously deactivated to “0” level. The sense amplifier 21 amplifies the signal output to the bit line BL, and the amplified read data is output to the read data line DL.

In the data input / output circuit 63, in the write data selection circuit 31 selected by the column address, the column selection signal YA is “1” level, and the write data DI is selected and the write data lines WB LB and Output to write bit line WBL. In the write data selection circuit 31 that is not selected by the column address, the column selection signal YA is at "0" level, and the read data line DL is selected and the write data line WB LB and write bit line WB L are selected as shown in FIG. Is output.

Next, in the SRAM circuit block 51 selected by the row address, the write selection signal WE is activated, the write NMOS transistor Nl 1 is turned on, and write data is output from the write data line WB LB to the bit line BL. At the same time, the write word line WWL of the SRAM cell 12 in which the word line WL is activated is activated. The data of the write data DI is written into the SRAM cell 12 selected by the column address as shown in FIG. As shown in FIG. 20, the signal output to the read data line DL, that is, the stored data of the SRAM cell 12 itself is written back to the SRAM cell 12 not selected by the column address. Therefore, in the SRAM cell 12 not selected by the column address, it is possible to perform stable data writing only to the SRAM cell 12 selected by the column address without destroying the stored data. The semiconductor memory device of this embodiment employs a 7-transistor SRAM cell. Also in the writing method of the present embodiment, the same effect as the above-described embodiment can be obtained. That is, the write data signal is written to the SRAM cell selected by the column address among the SRAM cells accessed to the write state by the mouth address. Read data is written back to SRAM cells that are not selected by the column address. When an SRAM cell array is configured by this write method, memory cells with different column addresses can be arranged adjacent to each other. Therefore, it is possible to obtain a semiconductor memory device having the flexibility in configuring the SRAM cell array and having resistance against multi-bit errors.

In FIG. 18, the write data selection circuit 31 drives the write data line WBLB, inverts it using the CMOS inverter I V 1 and outputs it to the write bit line WBL. However, the present invention is not limited to this, and depending on the configuration of the write data selection circuit 31, the relationship between the write data line WBLB and the write bit line WBL may be reversed.

(Example 7)

A seventh embodiment of the present invention will be described with reference to FIG. FIG. 21 is a seventh memory circuit block configuration diagram including seven transistor SRAM cells. In this embodiment, the inverted data of the write data in the sixth embodiment is generated in the SRAM circuit block.

The SRAM circuit block 52 includes a plurality of SRAM cells 12 including 7 transistors, a sense amplifier 21, a write NMOS transistor N 1 1, and a CMO S NOR gate NR 1 that drives a write bit line WB L. Consists of Compared to the sixth embodiment, a CMOS NOR gate NR 1 for generating inverted data of write data is added. The CMOS NOR gate NR 1 receives the write data line WBLB and the write selection signal WEB and outputs it to the write bit line WB L. The SRAM cell 12, the sense amplifier 21, and the write NMOS transistor Nl 1 have the same configuration as in the sixth embodiment.

The data input / output circuit 64 is a data input / output circuit that transmits / receives data to / from the SRAM circuit block 52 arranged two-dimensionally. Data input / output circuit 64 Is a read data selection circuit that selects one of the multiple read data lines DL according to the column address, and selects one of the read data line DL or write data DI and outputs it to the write data line WBLB. And data selection circuit 31. The global data signal lines commonly wired between the plurality of SRAM circuit blocks 52 are the read data line DL and the write data line WBLB.

The operation at the time of writing of this circuit will be described. The arbitrary data line WL of the SRAM circuit block 52 selected by the address is activated and the stored data of the SRAM cell 12 is output to the bit line BL. At this time, in order to prevent the stored data from being destroyed during reading, the inverted word line WLB is also set to "0" at the same time. The sense amplifier 21 amplifies the data signal output to the bit line BL, and the amplified read data is output to the read data line DL.

In the data input / output circuit 64, in the write data selection circuit 31 selected by the column address, the column selection signal YA is at "1" level, and the write data DI is selected and output to the write data line WB LB. In the write data selection circuit 31 that is not selected by the column address, the column selection signal Y A is at “0” level, and the read data line DL is selected and output to the write data line WB L B.

In the SRAM circuit block 52 selected by the address, the write selection signal WEB is activated and is at "0" level, and the gate NR 1 writes the inverted signal of the signal output to the write data line WB LB Output to bit line WBL. However, in the SRAM circuit block 52 not selected by the address, the node line is deactivated, the write selection signal WEB is at "1" level, and the write bit line WBL is at "0" level.

Next, in the SRAM circuit block 52 selected by the address, the write selection signal WE is activated, the write NMOS transistor Nl 1 is turned on, and the write data is output from the write data line WB LB to the bit line BL. . At the same time, the write word of the SRAM cell 12 in which the word line WL is activated Line WWL is activated. The data of the write data DI is written into the SRAM cell 12 selected by the column address. In the SRAM cell 12 not selected by the column address, the signal output to the read data line DL, that is, the storage data of the SRAM cell 12 itself is written back. Therefore, in the SRAM cell 12 not selected by the column address, it is possible to perform stable data writing only to the SRAM cell 12 selected by the column address without destroying the stored data.

Also in the write method of this embodiment, the write data signal is written to the SRAM cell selected by the column address among the SRAM cells accessed to the write state by the row address. Read data is written back to SRAM cells that are not selected by the column address. When an SRAM cell array is configured by this writing method, memory cells having different column addresses can be arranged adjacent to each other. Therefore, it is possible to obtain a semiconductor memory device having flexibility in the configuration of the SRAM cell array and having resistance against multi-bit errors. In FIG. 21, the write data selection circuit 31 drives the write data line WB LB of the global data signal line, inverts it using the CMOS NOR gate NR 1 and outputs it to the write bit line WBL. However, the present invention is not limited to this, and depending on the configuration of the write data selection circuit 31, the relationship between the write data line WB LB and the write bit line WB L may be reversed. At this time, a CMOS inverter gate can be used instead of the CMOS NOR gate NR1. (Example 8)

An eighth embodiment of the present invention will be described with reference to FIG. FIG. 22 is an eighth memory circuit block diagram including seven transistor SRAM cells. This configuration is an example in which the write data selection circuit 31 and the CMOS inverter I V 1 in the data input / output circuit 63 of the sixth embodiment are distributed in the SRAM circuit block 53.

The SRAM circuit block 53 includes a plurality of SRAM cells 12 including seven transistors, a sense amplifier 21, a write data selection circuit 32, a CMOS inverter IV2, and a write NMOS transistor Nl 1. Is done. The SRAM cell 12, the sense amplifier 21, and the write NMOS transistor N 1 1 have the same configuration as in the sixth embodiment. The write data selection circuit 32 selects one of the read data line DL and the write data line DI 2 and outputs it to the data line WBLB. The CMOS inverter IV 2 inverts the signal on the data line WB LB and outputs it to the write bit line WBL.

The data input / output circuit 65 is a data input / output circuit that transmits / receives data to / from the SRAM circuit block 53 arranged two-dimensionally. The data input / output circuit 65 includes a read data selection circuit 61 that selects one of a plurality of read data lines DL according to the column address, a write data drive circuit 62 that outputs the write data DI to the write data line DI 2, and Consists of. Global data signal lines commonly wired between the plurality of SRAM circuit blocks 53 are the read data line DL and the write data line D I 2.

The operation at the time of writing of this circuit will be described. The arbitrary word line WL of the SRAM circuit block 53 selected by the address is activated and the stored data of the SRAM cell 12 is output to the bit line BL. At this time, in order to prevent the stored data from being destroyed at the time of reading, the inversion lead line W L B is also deactivated at the same time. The sense amplifier 21 amplifies the data signal output to the bit line BL, and the amplified read data is output to the read data line DL.

In the write data selection circuit 32 selected by the column address, the selection signal YS is at “1” level, the write data line D I 2 is selected and further inverted and output to the write bit line WB L. In the write data selection circuit 32 that is not selected by the column address, the selection signal Y S is at the “0” level, the read data line DL is selected and output to the write data line WBL B and further inverted to the write bit line WBL. In the SRAM circuit block 53 that is not selected by the row address, the write selection circuit 32 selects neither the read data line DL nor the write data line DI2.

Next, the write selection signal WE is activated in the SRAM circuit block 53 selected by the row address, and the write NMOS transistor Nl 1 is activated. Turns on and write data is output to bit line BL. At the same time, the write word line WWL of the SRAM cell 12 activated by the word line WL activation is activated. The data of the write data DI is written into the SRAM cell 12 selected by the column address. In the SRAM cell 12 not selected by the column address, the signal output to the read data line DL, that is, the storage data of the SRAM cell 12 itself is written back. Accordingly, in the SRAM cell 12 not selected by the column address, it is possible to perform stable data writing only to the SRAM cell 12 selected by the column address without destroying the stored data.

Also in the write method of this embodiment, the write data signal is written to the SRAM cell selected by the column address among the SRAM cells accessed to the write state by the row address. Read data is written back to SRAM cells that are not selected by the column address. When an SRAM cell array is configured by this writing method, memory cells having different column addresses can be arranged adjacent to each other. Therefore, it is possible to obtain a semiconductor memory device having flexibility when configuring the SRAM cell array and having resistance against multi-bit errors. In FIG. 22, the write data selection circuit 32 drives the data line WB LB, inverts it using the CMOS inverter I V 2 and outputs it to the write bit line WBL. However, the present invention is not limited to this, and depending on the configuration of the write data selection circuit 32, the relationship between the data line WBLB and the write bit line WBL may be reversed.

(Example 9)

A ninth embodiment of the present invention will be described with reference to FIG. FIG. 23 is a block diagram of a ninth memory circuit block having seven transistor SRAM cells. The sense amplifier 22 of this embodiment operates only at the time of reading by the sense amplifier activation signal RE.

The SRAM circuit block 54 includes a plurality of SRAM memory 1 2 composed of 7 transistors, a sense amplifier 22, a write data selection circuit 33, and a CMO. It consists of S inverter I V2 and write NMOS transistor Nl 1. The SRAM cell 12 is the same as that in the sixth embodiment. The sense amplifier 22 operates only at the time of reading by the sense amplifier activation signal RE, receives the bit line BL, and outputs it to the read data line DL. The write data selection circuit 33 selects one of the bit line BL and the write data line DI 2 and outputs it to the data line WBLB. The C MOS inverter I V2 inverts the signal on the data line WBLB and outputs it to the write bit line WBL. The NMOS transistor Nl 1 uses the write selection signal WE as a gate input, and transfers data between the bit line BL and the data line WBLB. The data input / output circuit 65 is a data input / output circuit that transmits / receives data to / from the SRAM circuit block 54 arranged two-dimensionally. The data input / output circuit 65 includes a read data selection circuit 61 that selects one of a plurality of read data lines DL according to the column address, a write data drive circuit 62 that outputs the write data DI to the write data line DI 2, and Consists of. The global data signal lines commonly wired between the plurality of SRAM circuit blocks 54 are the read data line DL and the write data line DI2.

The operation at the time of writing of this circuit will be described. The arbitrary word line WL of the SRAM circuit block 54 selected by the address is activated and the stored data of the SRAM cell 12 is output to the bit line BL. At this time, in order to prevent the stored data from being destroyed at the time of reading, the inversion node line WLB is also deactivated at the same time. At this time, the sense amplifier activation signal RE is set to “0” level, and the sense amplifier 22 is operated only during the read operation.

In the write data selection circuit 33 selected by the column address, the selection signal YS is at “1” level, and the write data line DI 2 is selected and output to the write bit line WBL. In the write data selection circuit 33 that is not selected by the column address, the selection signal YS is “0” level, and the bit line signal BL is selected and output to the write bit line WBL. In the SRAM circuit block 54 that is not selected by the address, the selection signal YS is at the “0” level, and the write selection circuit 33 selects the bit line BL charged to the “1” level. Next, in the SRAM circuit block 54 selected by the address, the write selection signal WE is activated, the write NMOS transistor Nl 1 is turned on, and write data is output to the bit line BL. At the same time, the write word line WWL of the activated SRAM cell 12 is activated. The data of the write data DI is written into the SRAM cell 12 selected by the column address. In the SRAM cell 12 not selected by the column address, the signal output to the bit line BL, that is, the stored data of the SRAM cell 12 itself is written back. Therefore, in the SRAM cell 12 not selected by the column address, it is possible to perform stable data writing only to the SRAM cell 12 selected by the column address without destroying the stored data. Also in the write method of this embodiment, the write data signal is written to the SRAM cell selected by the column address among the SRAM cells accessed to the write state by the row address. Read data is written back to SRAM cells that are not selected by the column address. When an SRAM cell array is configured by this writing method, memory cells having different column addresses can be arranged adjacent to each other. Therefore, it is possible to obtain a semiconductor memory device having flexibility in the configuration of the SRAM cell array and having resistance against multi-bit errors. In FIG. 23, the write data selection circuit 33 drives the data line WBLB, inverts it using the CMOS inverter IV2, and outputs it to the write bit line WBL. However, the present invention is not limited to this, and depending on the configuration of the write data selection circuit 33, the relationship between the data line WB LB and the write bit line WBL may be reversed.

(Example 10)

A tenth embodiment of the present invention will be described with reference to FIG. FIG. 24 is a block diagram of a tenth memory circuit block having 7 transistor SRAM cells. This configuration is an example of a circuit configuration in which the read data line DL is shared for input and output.

The SRAM circuit block 55 has a plurality of SRAM cells 12 composed of 7 transistors, the sense amplifier 23, and the read data line DL inverted and written. This is composed of a CMOS NOR gate NR 1 that outputs to the bit line WB L and a write NMOS transistor Nil. The SRAM cell 12 has the same configuration as that of the sixth embodiment. The sense amplifier 23 is activated by the sense amplifier activation signal REB, receives the bit line BL, and outputs the output to the data line DL. The CMOS NOR gate NR 1 inverts the data line DL by the write selection signal WEB and outputs it to one write bit line WB L 1. The NMOS transistor Nl 1 uses the write selection signal WE as a gate input, and transfers data between the bit line BL and the data line DL.

The data input / output circuit 66 is a data input / output circuit that transmits / receives data to / from the SRAM circuit block 55 arranged two-dimensionally. When reading, the sense amplifier activation signal REB is activated by the column end address, and the signal on the data line D is output as read data DO. When writing, the data input signal is output to the data line DL by the column address.

The operation at the time of writing of this circuit will be described. An arbitrary word line WL of the SRAM circuit block 55 selected by the address is activated, and the storage data of the SRAM cell 12 is output to the bit line BL. At this time, in order to prevent the stored data from being destroyed at the time of reading, the inversion lead line W L B is also deactivated at the same time.

In the SRAM circuit block 55 selected by the column address, the sense amplifier activation signal REB is “1” level and the write selection signal WEB is “0” level. When the sense amplifier activation signal REB is “1” level, the operation of the sense amplifier 23 is stopped, and the data input / output circuit 66 outputs write data DI from the outside to the read data line DL. Write select signal WE B is activated

The write data DI for writing, which is “0” level and output from the data input / output circuit 66 to the read data line DL, is output to the write bit line WBL by the NOR gate NR 1. By stopping the operation of the sense amplifier 23, data collision on the data line DL can be avoided.

In the SRAM circuit block 55 that is not selected by the column address, the sense The amplifier activation signal RE B is at "0" level, and the write selection signal WEB is at "0" level. Sense amplifier active b When signal REB is "0" level, operate sense amplifier 23 to amplify the data on bit line BL and read it to data line DL. The write selection signal WEB is at "0" level, and the read data output from the sense amplifier 23 to the read data line DL is output to the write bit line WBL by the NOR gate NR1.

In the SRAM circuit block 55 not selected by the address, the word line is inactive, the write selection signal WEB is at "1" level, and the write bit line WBL is fixed at "0" level.

Next, in the SRAM circuit block 55 selected by the address, the write selection signal WE is activated, the write NMOS transistor Nl 1 is turned on, and the write data is output to the bit line BL. At the same time, the write word line WWL of the SRAM cell 12 in which the word line WL is activated is activated. The data of the write data D I is written to the SRAM cell 12 selected by the column address. A signal output to the read data line DL, that is, data stored in the SRAM cell 12 itself is written back to the SRAM cell 12 that is not selected by the column address. Accordingly, in the SRAM cell 12 not selected by the column address, it is possible to perform stable data writing only to the SRAM cell 12 selected by the column address without destroying the stored data.

In the write method of the present embodiment, a write data signal is written to the SRAM cell selected by the column address among the SRAM cells accessed in the write state by the row address. Read data is written back to SRAM cells that are not selected by the column address. When an SRAM cell array is configured by this writing method, memory cells having different column addresses can be arranged adjacent to each other. Therefore, it is possible to obtain a semiconductor memory device having flexibility in the configuration of the SRAM cell array and having resistance against multi-bit errors. As in the fifth embodiment, a specific example of the sense amplifier 23 is shown in FIG. Amplifiers can be used. In this case, the bit line BL is connected to the input RBL of the sense amplifier. When one sense amplifier is arranged between two SRAM cell arrays, the sense amplifier shown in FIG. 17 can be used as a specific example of the sense amplifier 23 as in the fifth embodiment. In this case, the bit lines of the two SRAM cell arrays are connected to the input RB 1 and RBL 2 of the sense amplifier. The semiconductor memory device of the present invention is composed of SRAM cells having write-only word lines in order to improve the read margin. When performing a write operation, perform the read operation before performing the write operation and output the read data to the bit line. The write data selection circuit that switches between read data and external write data writes the write data to the SRAM cells selected by the column address, and writes back the stored data to the SRAM cells that are not selected by the column address. As a result, when an SRAM cell array is configured, memory cells having different column addresses can be arranged adjacent to each other as in the conventional SRAM. A semiconductor memory device capable of increasing the degree of freedom in configuring the SRAM cell array and improving the resistance to multi-bit errors caused by cosmic rays and alpha rays can be obtained.

The present invention has been specifically described above based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention. It goes without saying that the modified example is also included in the present application. Industrial applicability:

The present invention can be applied to a semiconductor memory device such as a static random access memory (SRAM) having a write write wire. This application claims priority based on Japanese Patent Application No. 2006-2 47521 filed on Sep. 13, 2006, the entire disclosure of which is incorporated herein.

Claims

The scope of the claims

1. a first inverter circuit having a first storage node and a second storage node, wherein the second storage node is an input and the first storage node is an output; and the first storage node And a second inverter circuit having the second storage node as an output and first and second access means for accessing the first and second storage nodes, respectively. A semiconductor memory device arranged in two dimensions,

Select one of the write word line activated at the time of writing, the read word line activated at the time of reading, the read data from the SRAM cell at the time of write, and the write data input from the outside A semiconductor memory device comprising: a write data selection circuit.

2. At the beginning of the write operation, the read data read from the SRAM cell selected by the row address is written back to the SRAM cell by activating the write word line selected by the row address. The semiconductor memory device according to claim 1.

3. The semiconductor memory device according to claim 1, wherein the write data selection circuit outputs either the read data or the write data to a write bit line of an SRAM cell based on a selection signal.

4. The semiconductor memory device according to claim 3, wherein the selection signal is activated or deactivated by a column address.

5. The write data is written in an SRAM cell selected by the column address, and the read data is written back in an SRAM cell not selected by the column address. Semiconductor memory apparatus.

6. The semiconductor memory device according to any one of claims 1 to 5, wherein the SRAM cell further includes two read-only transistors.

7. The two read-only transistors are connected in series between a read bit line and a ground potential, and a gate of the transistor connected to the read bit line is connected to the read word line and connected to the ground potential. 7. The semiconductor memory device according to claim 6, wherein a gate of the transistor formed is connected to the second storage node.

8. The read bit line is input to a sense amplifier, the read data is output from the sense amplifier, and the write data selection circuit is input with the read data and the write data. 8. The semiconductor memory device according to claim 7, wherein the data is output to a write bit line.

9. The SRAM cell is further connected to a drive transistor of the second inverter circuit in series, and further includes a transistor whose gate is connected to an inverting node line. 6. The semiconductor memory device according to any one of 5.

1 0. The bit line connected to the first access transistor is input to a sense amplifier, read data is output from the sense amplifier, and the write data selection circuit inputs the data and the write data. 10. The semiconductor memory device according to claim 9, wherein one of the data and the error is output to a write bit line.

1 1. Having a first storage node and a second storage node, the second storage node A first inverter circuit having the first storage node as an input and an output from the first storage node; a second inverter circuit having the first storage node as an input and the second storage node as an output; and In a writing method of a semiconductor memory device in which a plurality of SRAM cells are arranged two-dimensionally, each having first and second access means for accessing the second storage node,

At the beginning of the write operation, the storage data of the SRAM cell in which the read word line selected by the row address is activated is read as read data, and then the write word line selected by the port address is activated and the read data is read. A method for writing into a semiconductor memory device, wherein either the write data inputted from the outside or the write data inputted from the outside is written into the SRAM cell.

1 2. The semiconductor memory according to claim 11, wherein the write data is written in a SRAM cell selected by a column address, and the read data is written back in a SRAM cell not selected by a column address. How to write the device.