WO2012090803A1

WO2012090803A1 - Liquid crystal display device

Info

Publication number: WO2012090803A1
Application number: PCT/JP2011/079587
Authority: WO
Inventors: 鷲尾　一
Original assignee: シャープ株式会社
Priority date: 2010-12-28
Filing date: 2011-12-21
Publication date: 2012-07-05

Abstract

A liquid crystal display device provided with memory units (51) that hold image data and are disposed in each pixel (P). Each pixel (P) has a memory unit (51) that includes a first pixel memory (MR1) and a second pixel memory (MR2) that each hold two image data, and displays based on the image data hold by each pixel memory (MR1, MR2). This enables power consumption when displaying by switching between a plurality of images in the liquid crystal display device comprising a pixel memory circuit to be reduced.

Description

Liquid crystal display

The present invention relates to a liquid crystal display device including a memory circuit capable of holding data in a pixel.

In recent years, a liquid crystal display device has been proposed as a liquid crystal display device including a pixel memory that performs display by holding image data written in the pixel in a memory circuit (referred to as a pixel memory) in the pixel (Patent Document 1). etc). In a normal operation for displaying a multi-gradation moving image, a new image data is rewritten on a pixel-by-frame basis through a data signal line for display. On the other hand, in a memory operation for displaying a still image, a rewrite image is displayed. Display is performed using image data held in the pixel memory without supplying data.

Therefore, in the memory operation, the operation of the drive circuit that drives the scanning signal line and the data signal line can be stopped, so that power consumption can be greatly reduced. Accordingly, the memory operation is often used for image display that is strongly demanded to reduce power consumption, such as a standby screen display of a cellular phone.

In the liquid crystal display device disclosed in Patent Document 1, one pixel memory circuit (DM18 in FIG. 33) is provided for each pixel, and a still image display is performed using image data held in each pixel memory circuit. ing.

Japanese Patent Publication “JP 2002-229532 A (published on August 16, 2002)”

However, in the liquid crystal display device of Patent Document 1, since one pixel memory circuit is provided for each pixel, for example, a displayed image (first image) is changed to another image (second image). When switching, it is necessary to write (rewrite) the image data corresponding to the second image to the pixel memory circuit by setting the data signal line and the scanning signal line to the active state. Therefore, there is a problem that power for driving the data signal line and the scanning signal line is required, and power consumption increases.

Thus, in the conventional liquid crystal display device, when one image is displayed as a still image for a long time, the effect of low power consumption can be sufficiently obtained, but when a plurality of images are switched and displayed, An operation similar to that of normal moving image display is required, and the effect of low power consumption cannot be obtained.

The present invention has been made in view of the above-described conventional problems, and an object thereof is to reduce power consumption when a plurality of images are switched and displayed in a liquid crystal display device including a pixel memory circuit. is there.

In order to solve the above problems, the liquid crystal display device according to the present invention provides
A liquid crystal display device provided with a storage unit for holding image data in each pixel,
In each pixel, the storage unit includes a plurality of memory circuits each holding individual image data,
Display is performed based on image data held in each memory circuit.

According to the above configuration, each pixel is provided with a plurality of memory circuits, and each memory circuit can individually hold image data. As a result, when switching images, it is only necessary to switch and display the image data held in each memory circuit, so there is no need to perform the same operation as normal moving image display as in the prior art, and power consumption is reduced. Can be reduced.

As described above, in the liquid crystal display device according to the present invention, in each pixel, the storage unit includes a plurality of memory circuits each holding individual image data, and based on the image data held in each memory circuit. It is the structure which performs a display. Thereby, in the liquid crystal display device provided with the pixel memory circuit, there is an effect that it is possible to reduce power consumption when switching and displaying a plurality of images.

3 is an equivalent circuit diagram illustrating a configuration of one pixel in the liquid crystal display device according to Embodiment 1. FIG. 1 is a block diagram illustrating an overall configuration of a liquid crystal display device according to Embodiment 1. FIG. FIG. 3 is a schematic diagram illustrating a configuration of a pixel of the liquid crystal display panel in FIG. 2. 3 is a timing chart illustrating a driving method of the liquid crystal display device according to the first embodiment. 6 is a timing chart illustrating another driving method of the liquid crystal display device according to the first embodiment. 6 is a timing chart illustrating another driving method of the liquid crystal display device according to the first embodiment. FIG. 6 is an equivalent circuit diagram illustrating a first modification of the pixel in FIG. 1. 6 is a schematic diagram illustrating a configuration of a pixel of a liquid crystal display panel in a liquid crystal display device according to Embodiment 2. FIG. 6 is an equivalent circuit diagram illustrating a configuration of one pixel in the liquid crystal display device according to Embodiment 2. FIG. FIG. 10 is a circuit diagram of a decoder included in the pixel of FIG. 9. 10 is a table showing a relationship between a combination of a first image data selection signal and a second image data selection signal, an output signal of the decoder of FIG. 10, and a pixel memory selected from a storage unit included in the pixel of FIG. FIG. 10 is an equivalent circuit diagram illustrating a modification of the pixel in FIG. 9. 6 is a schematic diagram illustrating a configuration of a pixel of a liquid crystal display panel in a liquid crystal display device according to Embodiment 3. FIG. 6 is an equivalent circuit diagram showing a configuration of one pixel in a liquid crystal display device according to Embodiment 3. FIG. 6 is a timing chart illustrating a method for driving a liquid crystal display device according to a third embodiment. FIG. 6 is a schematic diagram illustrating a configuration of a pixel of a liquid crystal display panel in a liquid crystal display device according to a fourth embodiment. 6 is an equivalent circuit diagram illustrating a configuration of one pixel in a liquid crystal display device according to Embodiment 4. FIG. FIG. 18 is an equivalent circuit diagram illustrating a modification of the pixel in FIG. 17. FIG. 10 is a block diagram illustrating an overall configuration of a liquid crystal display device according to a fifth embodiment. FIG. 10 is a schematic diagram illustrating a configuration of a pixel of a liquid crystal display panel in a liquid crystal display device according to a fifth embodiment. FIG. 10 is an equivalent circuit diagram illustrating a configuration of one pixel in a liquid crystal display device according to a fifth embodiment. 10 is a timing chart illustrating a driving method of the liquid crystal display device according to the fifth embodiment. FIG. 22 is an equivalent circuit diagram illustrating a modification of the pixel in FIG. 21. FIG. 10 is a schematic diagram illustrating a configuration of a pixel of a liquid crystal display panel in a liquid crystal display device according to a sixth embodiment. FIG. 10 is an equivalent circuit diagram illustrating a configuration of one pixel in a liquid crystal display device according to a sixth embodiment. FIG. 16 is a schematic diagram illustrating a configuration of a pixel of a liquid crystal display panel in a liquid crystal display device according to a seventh embodiment. FIG. 10 is an equivalent circuit diagram illustrating a configuration of one pixel in a liquid crystal display device according to a seventh embodiment. 18 is a timing chart illustrating a driving method of the liquid crystal display device according to the seventh embodiment. FIG. 16 is a schematic diagram showing a pixel configuration of a liquid crystal display panel in a liquid crystal display device according to an eighth embodiment. FIG. 10 is an equivalent circuit diagram illustrating a configuration of one pixel in a liquid crystal display device according to an eighth embodiment. FIG. 31 is an equivalent circuit diagram illustrating a modification of the pixel in FIG. 30. FIG. 10 is an equivalent circuit diagram illustrating a second modification of the pixel in FIG. 1. It is a figure which shows the structure of the pixel in the conventional liquid crystal display device.

[Embodiment 1]
An embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a block diagram showing the overall configuration of the liquid crystal display device according to the present embodiment. The liquid crystal display device 10 includes a liquid crystal display panel 100 and a display control circuit 200. The liquid crystal display panel 100 includes a source driver (data signal line driving circuit) 300, a gate driver (scanning signal line driving circuit) 400, a display unit 500, and a memory operation driver 600. The display control circuit 200 includes a memory drive control unit 20. The display unit 500 includes a first source bus line (first data signal line) SL1, a second source bus line (second data signal line) SL2, a gate bus line (scanning signal line) GL, an image data selection line SEL, A high potential side power supply line VHL and a low potential side power supply line VLL are included. The first source bus line SL1 and the second source bus line SL2 are connected to the source driver 300, the gate bus line GL is connected to the gate driver 400, the image data selection line SEL, the high potential side power supply line VHL, and the low The potential power supply line VLL is connected to the memory driving driver 600.

In addition, the display unit 500 includes a plurality of pixels P. One gate bus line GL and two source bus lines (first source bus line SL1, second source bus line) corresponding to each pixel P. SL2), an image data selection line SEL, a high potential side power supply line VHL, and a low potential side power supply line VLL are provided. Each pixel P has a pixel electrode PIX for applying a voltage according to an image to be displayed to a liquid crystal capacitor Clc, which will be described later, and a common electrode COM that is a common electrode provided to the plurality of pixels P. And a liquid crystal layer provided in common to the plurality of pixels P and sandwiched between the pixel electrode PIX and the common electrode COM. Each pixel P is provided with a storage unit, and the storage unit is provided with two memory circuits (first memory circuit and second memory circuit) each as a storage circuit capable of holding 1-bit data. Yes. Hereinafter, the first memory circuit is referred to as a first pixel memory MR1, and the second memory circuit is referred to as a second pixel memory MR2.

The liquid crystal display device 10 according to the present embodiment performs display by holding the image data written in the pixel P in the first pixel memory MR1 and the second pixel memory MR2 in the pixel P. More specifically, the liquid crystal display device 10 has an image data writing period in which image data is written and an image data holding period in which display is performed while holding the written image data. First image data for two image data corresponding to images (first image and second image) (for convenience, the first image data corresponding to the first image and the second image data corresponding to the second image) Is written in the first pixel memory MR1, the second image data is written in the second pixel memory MR2, and in the image data holding period, the first image held in the first pixel memory MR1 is displayed when displaying the first image. When displaying with the image data and displaying the second image, the display is switched to the second image data held in the second pixel memory MR2.

The display control circuit 200 receives a data signal DAT and an image data selection signal VSEL sent from the outside, and receives a digital video signal DV (image data) and a source start pulse signal SSP for controlling image display on the display unit 500, A source clock signal SCK, a latch strobe signal LS, a gate start pulse signal GSP, a gate clock signal GCK, and an image data selection signal VSEL for selecting an image (first image, second image) to be displayed on the display unit 500 Output. A specific configuration for selecting an image will be described later.

The source driver 300 receives the digital video signal DV, the source start pulse signal SSP, the source clock signal SCK, and the latch strobe signal LS output from the display control circuit 200, and receives each source bus line (first source bus line SL1, first source bus line SL1). A driving video signal (image data) is applied to the 2-source bus line SL2). Specifically, the first image data is applied to the first source bus line SL1, and the second image data is applied to the second source bus line SL2. For example, when it is desired to switch between a white solid image as the first image and a black solid image as the second image, the first image data is white image data and the second image data is black. It can be image data.

The gate driver 400 sequentially selects each gate bus line GL by one horizontal scanning period (1H) when writing image data (first image data, second image data) (image data writing period). Based on the gate start pulse signal GSP and the gate clock signal GCK output from the display control circuit 200, an active scanning signal (gate signal) is sequentially applied to each gate bus line GL. Thereby, in each pixel P in the same row (horizontal line), the first image data is written in the first pixel memory MR1, and at the same time, the second image data is written in the second pixel memory MR2. In the image data holding period, the gate driver 400 stops applying the active scanning signal to each gate bus line GL and deactivates all the gate bus lines GL.

(Pixel circuit configuration)
FIG. 3 is a schematic diagram showing the configuration of the pixels of the liquid crystal display panel 100, and shows two pixels P in each of the (n-1), n, and (n + 1) rows. FIG. 1 is an equivalent circuit diagram showing the configuration of one pixel P. The pixel P includes a switch unit 50, a storage unit 51, a data selection unit 52, and a display element unit 53.

The switch unit 50 includes a first switch unit SW10 and a second switch unit SW20, and the first switch unit SW10 is realized by an N-type TFT (hereinafter referred to as “N-type” as needed), The switch SW12 and the inverter circuit INV11 (hereinafter referred to as “P-type” if necessary) realized by a P-type TFT include an inverter circuit INV11. The second switch unit SW20 includes an N-type switch SW21, a P-type switch SW22, and an inverter. A circuit INV21 is included. For each switch, a switch with a white circle is a P-type switch, and a switch without a white circle is an N-type switch. In the following description, the terms “N type” and “P type” are omitted as necessary.

The switch SW11 has a control terminal connected to the gate bus line GL, one conduction terminal connected to the first source bus line SL1, and the other conduction terminal connected to the output terminal swout1 of the first switch unit SW10. The switch SW12 has a control terminal connected to the output terminal of the inverter circuit INV11, one conduction terminal connected to the first source bus line SL1, and the other conduction terminal connected to the output terminal swout1 of the first switch unit SW10. Yes. The input terminal of the inverter circuit INV11 is connected to the gate bus line GL.

The switch SW21 has a control terminal connected to the gate bus line GL, one conduction terminal connected to the second source bus line SL2, and the other conduction terminal connected to the output terminal swout2 of the second switch unit SW20. The switch SW22 has a control terminal connected to the output terminal of the inverter circuit INV21, one conduction terminal connected to the second source bus line SL2, and the other conduction terminal connected to the output terminal swout2 of the second switch unit SW20. Yes. The input terminal of the inverter circuit INV21 is connected to the gate bus line GL.

The storage unit 51 includes a first pixel memory MR1 and a second pixel memory MR2. The first pixel memory MR1 includes two inverter circuits INV12 and INV13. The second pixel memory MR2 includes two inverter circuits INV22 and INV23. Is included.

The inverter circuit INV12 has an input terminal connected to the output terminal swout1 of the first switch unit SW10, and an output terminal connected to the output terminal mout1 of the first pixel memory MR1. The inverter circuit INV13 has an input terminal connected to the output terminal of the inverter circuit INV12, and an output terminal connected to the input terminal of the inverter circuit INV12.

The inverter circuit INV22 has an input terminal connected to the output terminal swout2 of the second switch unit SW20, and an output terminal connected to the output terminal mout2 of the second pixel memory MR2. The inverter circuit INV23 has an input terminal connected to the output terminal of the inverter circuit INV22, and an output terminal connected to the input terminal of the inverter circuit INV22.

The data selection unit 52 includes N-type switches SW13 and SW23, P-type switches SW14 and SW24, and an inverter circuit INV14. The switch SW13 has a control terminal connected to the image data selection line SEL, one conduction terminal connected to the output terminal mout1 of the first pixel memory MR1, and the other conduction terminal connected to the output terminal selout of the data selection unit 52. ing. The switch SW14 has a control terminal connected to the output terminal of the inverter circuit INV14, one conduction terminal connected to the output terminal mout1 of the first pixel memory MR1, and the other conduction terminal connected to the output terminal selout of the data selection unit 52. Has been. The switch SW23 has a control terminal connected to the output terminal of the inverter circuit INV14, one conduction terminal connected to the output terminal mout2 of the second pixel memory MR2, and the other conduction terminal connected to the output terminal selout of the data selection unit 52. Has been. The switch SW24 has a control terminal connected to the image data selection line SEL, one conduction terminal connected to the output terminal mout2 of the second pixel memory MR2, and the other conduction terminal connected to the output terminal selout of the data selection unit 52. ing. The inverter circuit INV14 has an input terminal connected to the image data selection line SEL, and an output terminal connected to the control terminal of the switch SW14 and the control terminal of the switch SW23.

The display element unit 53 includes N-type switches SW15 and SW25, P-type switches SW16 and SW26, an inverter circuit INV15, a pixel electrode PIX, a counter electrode COM, and a liquid crystal capacitor Clc. The switch SW15 has a control terminal connected to the output terminal selout of the data selection unit 52, one conduction terminal connected to the low potential side power supply line VLL, and the other conduction terminal connected to the pixel electrode PIX. The switch SW16 has a control terminal connected to the output terminal of the inverter circuit INV15, one conduction terminal connected to the low potential power supply line VLL, and the other conduction terminal connected to the pixel electrode PIX. The switch SW25 has a control terminal connected to the output terminal of the inverter circuit INV15, one conduction terminal connected to the high potential side power supply line VHL, and the other conduction terminal connected to the pixel electrode PIX. The switch SW26 has a control terminal connected to the output terminal selout of the data selection unit 52, one conduction terminal connected to the high potential side power supply line VHL, and the other conduction terminal connected to the pixel electrode PIX. A liquid crystal capacitance Clc is formed between the pixel electrode PIX and the counter electrode COM.

(Driving method)
Next, a driving method in the present embodiment will be described with reference to FIGS. FIG. 4 is a timing chart showing a driving method (normally black mode) of the liquid crystal display device 10. VSL1 and VSL2 are signals of the first image data and the second image data supplied to the first source bus line SL1 and the second source bus line SL2, respectively. VGL (n−1), VGLn, VGL ( n + 1) are gate signals (scanning signals) supplied to the gate bus lines GL (n−1), GLn, GL (n + 1) in the (n−1) th row, the nth row, and the (n + 1) th row, respectively. VSEL indicates an image data selection signal supplied to the image data selection line SEL, and VMR1 (n−1), VMR1n, and VMR1 (n + 1) are the (n−1) th row, the nth row, and (n + 1), respectively. ) Indicates the potential of the first pixel memory MR1 in the row, and VMR2 (n−1), VMR2n, VMR2 (n + 1) are the second in the (n−1) th row, the nth row, and the (n + 1) th row, respectively. Pixel memory VP (n−1), VPn, VP (n + 1) are the potentials (pixel potentials) of the pixel electrodes PIX in the (n−1) th row, the nth row, and the (n + 1) th row, respectively. Is shown. In the present embodiment, as described above, the display image is switched between the first image and the second image. This switching is performed based on an image data selection signal VSEL sent to the display control circuit 200 from the outside. Hereinafter, a driving method during the image data writing period and a driving method during the image data holding period will be described in order. FIG. 4 shows a case where the first image displayed by the first image data is a white solid image, and the second image displayed by the second image data is a black solid image.

(Driving method for image data writing period)
In FIG. 4, image data is written from time t1 to time t2. In the image data writing period, active signals are sequentially supplied to the gate bus lines GL (n−1), GLn, and GL (n + 1) for a predetermined period. A high (H) level or low (L) level image data selection signal VSEL is supplied to the image data selection line SEL. Here, it is assumed that an H level image data selection signal VSEL is supplied.

Here, focusing on the pixel Pn in the n-th row, when an active signal (H level) is applied to the gate bus line GLn provided corresponding to the pixel Pn, the switches SW11 and SW21 are turned on. . At the same time, the H level signal is input to the inverter circuits INV11 and INV21, and the inverted level (L level) output signal is applied to the switches SW12 and SW22, so that the switches SW12 and SW22 are also turned on.

Accordingly, the first image data (image data corresponding to white: H level (“1”)) supplied to the first source bus line SL1 is supplied to the first pixel of the storage unit 51 via the switches SW11 and SW12. Second image data (image data corresponding to black: L level (“0”)) input to the memory MR1 and supplied to the second source bus line SL2 is stored in the storage unit 51 via the switches SW21 and SW22. It is input to the second pixel memory MR2.

In the first pixel memory MR1, when an H level signal is input to the inverter circuit INV12, an L level signal is input to the inverter circuit INV13, whereby an H level signal is input to the inverter circuit INV12 again. In this way, an H level signal is held in the first pixel memory MR1 (“VMR1n” in FIG. 4). The L level signal output from the inverter circuit INV12 is provided to the switches SW13 and SW14 of the data selection unit 52 as the output of the first pixel memory MR1.

In the second pixel memory MR2, when an L level signal is input to the inverter circuit INV22, an H level signal is input to the inverter circuit INV23, whereby an L level signal is input to the inverter circuit INV22 again. In this way, an L level signal is held in the second pixel memory MR2 (“VMR2n” in FIG. 4). The H level signal output from the inverter circuit INV22 is provided to the switches SW23 and SW24 of the data selection unit 52 as the output of the second pixel memory MR2.

Since the H-level image data selection signal VSEL is input to the data selection unit 52, the switch SW13 is turned on and the switch SW24 is turned off. Further, since the L level signal is supplied to the switches SW14 and SW23 via the inverter circuit INV14, the switch SW14 is turned on and the switch SW23 is turned off. As a result, an L level signal of the first pixel memory MR <b> 1 is output from the data selection unit 52 and input to the display element unit 53.

In the display element section 53, an L level signal is applied to the switches SW15 and SW26, and an H level signal is applied to the switches SW16 and SW25 via the inverter INV15. Therefore, the switches SW15 and SW16 are turned off, and the switches SW25 and SW26 are turned on. As a result, the voltage (H level) of the high potential side power supply line VHL is applied to the pixel electrode PIX, and white is displayed in the pixel Pn (“VPn” in FIG. 4). The same operation is performed on the pixels adjacent to the pixel Pn, and a white solid image is displayed.

(Driving method for image data retention period)
In the image data holding period, display is performed using the image data held in the storage unit 51. For example, paying attention to the pixel Pn in the n-th row, the display is performed with the first image data (white) stored in the first pixel memory MR1 from the time point t2 to the time point t3, and the second pixel memory after the time point t3. It is assumed that display is performed using the second image data (black) stored in MR2.

First, when the image data holding period starts (time t2), an inactive signal (L level) is supplied to all the gate bus lines GL (n−1), GLn, and GL (n + 1). The image data selection line SEL is continuously supplied with the H level image data selection signal VSEL as in the image data writing period.

When an inactive signal (L level) is applied to all the gate bus lines GL (n−1), GLn, GL (n + 1), the switches SW11 and SW21 are turned off. At the same time, since the L level signal is input to the inverter circuits INV11 and INV21 and the inverted signal (H level) is output to the switches SW12 and SW22, the switches SW12 and SW22 are also turned off. Thereby, the supply of the data signal from the switch unit 50 to the storage unit 51 is stopped. Therefore, since the operation of the source driver 300 can be stopped in the image data holding period, power consumption can be reduced.

In the storage unit 51, an H level data signal is held in the first pixel memory MR1 (“VMR1n” in FIG. 4), and an L level data signal is held in the second pixel memory MR2 (“VMR2n” in FIG. 4). Therefore, an L level data signal is output from the first pixel memory MR1, and an H level data signal is output from the second pixel memory MR2.

Since the H-level image data selection signal VSEL is input to the data selection unit 52, the switch SW13 is kept on and the switch SW24 is kept off. In addition, since an L level signal is supplied to the switches SW14 and SW23 via the inverter circuit INV14, the switch SW14 is kept on and the switch SW23 is kept off. As a result, as in the image data writing period, the output signal (L level) of the first pixel memory MR1 is output from the data selection unit 52 and input to the display element unit 53.

In the display element section 53, since the L level signal is supplied to the switches SW15 and SW26 and the H level signal is supplied to the switches SW16 and SW25 via the inverter INV15, the switches SW15 and SW16 maintain the OFF state. SW25 and SW26 are kept on. Accordingly, the voltage (H level) of the high potential side power supply line VHL is continuously applied to the pixel electrode PIX, and white display is maintained in the pixel Pn (“VPn” in FIG. 4). The same operation is performed on the pixels adjacent to the pixel Pn, and the display of the white solid image is maintained.

Next, at time t3, the L-level image data selection signal VSEL is supplied to the image data selection line SEL. In this case as well, since the inactive signal (L level) is supplied to all the gate bus lines GL (n−1), GLn, and GL (n + 1), the supply of the data signal is stopped.

Thus, since the L-level image data selection signal VSEL is input to the data selection unit 52, the switch SW13 is turned off and the switch SW24 is turned on. Further, since the H level signal is supplied to the switches SW14 and SW23 via the inverter circuit INV14, the switch SW14 is turned off and the switch SW23 is turned on. As a result, the output signal (H level) of the second pixel memory MR <b> 2 is output from the data selection unit 52 and input to the display element unit 53.

In the display element unit 53, the H level signal is supplied to the switches SW15 and SW26, and the L level signal is supplied to the switches SW16 and SW25 via the inverter INV15. Therefore, the switches SW15 and SW16 are turned on, and the switch SW25 is turned on. , SW26 is turned off. As a result, the voltage (L level) of the low potential side power supply line VLL is applied to the pixel electrode PIX, and the pixel Pn is switched to black display (“VPn” in FIG. 4). The same operation is performed on the pixels adjacent to the pixel Pn, and the white solid image is switched to the black solid image.

As described above, in the image data holding period, display is performed using the image data held in the storage unit 51, and the first image data held in the first pixel memory MR1 is displayed on the basis of the image data selection signal VSEL. The corresponding first image and the second image corresponding to the second image data held in the second pixel memory MR2 can be switched and displayed.

Here, black display is performed in the image data writing period from time t1 to time t2 and image data holding period from time t2 to time t3, and white display is performed after time t3 as shown in the timing chart of FIG. In addition, the potential level (H / L) of the image data selection signal VSEL may be reversed.

In addition, when the first image data is a first image having a horizontal stripe pattern (stripe) and the second image data is a second image having a horizontal stripe pattern (black and white of each pixel is reversed from the first image), FIG. As shown in the timing chart, the potential levels of the first image data supplied to the first source bus line SL1 and the second image data supplied to the second source bus line SL2 are reversed from each other, and each image data The potential level may be reversed every horizontal scanning period (1H). Furthermore, when a checkerboard pattern is displayed, the connection between the first source bus line SL1 and the second source bus line SL2 may be configured to be opposite to each other in adjacent pixel columns. For example, in the pixel adjacent to the pixel shown in FIG. 1 in the row direction (the horizontal direction in FIG. 1), the first source bus line SL1 is connected to the second switch unit SW12, and the second source bus line SL2 is connected to the first switch. What is necessary is just to connect to part SW10.

Incidentally, it is generally known that a liquid crystal display device adopts AC driving to prevent deterioration of a liquid crystal material used for a liquid crystal display panel. The AC driving in this description means that the voltage applied to both ends of the liquid crystal capacitor Clc shown in FIG. In the present liquid crystal display device 10, synchronized alternating current waveform signals are input to the high potential side power supply line VHL, the low potential side power supply line VLL, and the common electrode COM. In the present embodiment, since normally black liquid crystal material is used, the common electrode COM and the low potential power line VLL are signals having the same potential and the same timing, and the high potential power line VHL is The signal has a phase opposite to that of the common electrode COM and the low-potential side power supply line VLL. The same applies to other embodiments.

(Modification 1)
FIG. 7 is an equivalent circuit diagram showing a first modification of the pixel P in FIG. The pixel P in FIG. 7 schematically has a configuration in which the inverter circuit INV15 of the display element unit 53 in the pixel P in FIG. 1 is omitted. Below, it demonstrates centering on difference with the pixel P of FIG.

The switch unit 50 and the storage unit 51 have the same configuration as the pixel P in FIG.

The image data selection unit 52 is provided with N-type switches SW17 and SW27 and P-type switches SW18 and SW28 in addition to the switches SW13, SW14, SW23 and SW24 and the inverter circuit INV14 shown in FIG. Each of the switches SW13 and SW14 has one conduction terminal connected to the output terminal mout1 of the first pixel memory MR1, and the other conduction terminal connected to the output terminal selout1 of the data selection unit 52. Each of the switches SW23 and SW24 has one conduction terminal connected to the output terminal mout2 of the second pixel memory MR2, and the other conduction terminal connected to the output terminal selout1 of the data selection unit 52. The switch SW17 has a control terminal connected to the image data selection line SEL, one conduction terminal connected to the input terminal of the inverter circuit INV12 and the output terminal of the inverter circuit INV13 in the first pixel memory MR1, and the other conduction terminal connected to the data. The selector 52 is connected to the output terminal selout2. The switch SW18 has a control terminal connected to the output terminal of the inverter circuit INV14, one conduction terminal connected to the input terminal of the inverter circuit INV12 and the output terminal of the inverter circuit INV13, and the other conduction terminal output of the data selection unit 52. It is connected to the terminal selout2. The switch SW27 has a control terminal connected to the output terminal of the inverter circuit INV14, one conduction terminal connected to the input terminal of the inverter circuit INV22 and the output terminal of the inverter circuit INV23, and the other conduction terminal output of the data selection unit 52. It is connected to the terminal selout2. The switch SW28 has a control terminal connected to the image data selection line SEL, one conduction terminal connected to the input terminal of the inverter circuit INV22 and the output terminal of the inverter circuit INV23, and the other conduction terminal output terminal of the data selection unit 52. It is connected to selout2. The inverter circuit INV14 has an input terminal connected to the image data selection line SEL and an output terminal connected to the control terminals of the switches SW14, SW18, SW23, and SW27.

The display element unit 53 includes switches SW15, SW25, SW16, SW26, a pixel electrode PIX, a counter electrode COM, and a liquid crystal capacitor Clc. The switch SW15 has a control terminal connected to the output terminal selout1 of the data selection unit 52, one conduction terminal connected to the low potential side power supply line VLL, and the other conduction terminal connected to the pixel electrode PIX. The switch SW16 has a control terminal connected to the output terminal selout2 of the data selection unit 52, one conduction terminal connected to the low potential side power supply line VLL, and the other conduction terminal connected to the pixel electrode PIX. The switch SW25 has a control terminal connected to the output terminal selout2 of the data selection unit 52, one conduction terminal connected to the high potential side power supply line VHL, and the other conduction terminal connected to the pixel electrode PIX. The switch SW26 has a control terminal connected to the output terminal selout1 of the data selection unit 52, one conduction terminal connected to the high potential side power supply line VHL, and the other conduction terminal connected to the pixel electrode PIX. A liquid crystal capacitance Clc is formed between the pixel electrode PIX and the counter electrode COM.

7 is the same as the driving method shown in FIG. 4 because the driving method of the liquid crystal display device having the pixel P according to Modification 1 of FIG. 7 is omitted.

(Modification 2)
FIG. 32 is an equivalent circuit diagram showing a second modification of the pixel P in FIG. In the liquid crystal display panel 100 having the pixel P according to the second modification, the gate bus line GLB and the image data selection line SELB are further provided for each pixel P in the liquid crystal display panel 100 shown in FIG. The gate bus line GLB is supplied with an inversion signal VGLB of the gate signal VGL supplied to the gate bus line GL, and the image data selection line SELB is inverted with the image data selection signal VSEL supplied to the image data selection line SEL. A signal VSELB is supplied.

32, the inverter circuits INV11 and INV21 of the switch unit 50 and the inverter circuit INV14 of the data selection unit 52 in the pixel P of FIG. 1 are omitted. The storage unit 51 and the display element unit 53 have the same configuration as the pixel P in FIG.

32, in the switch unit 50, an active gate signal VGL (H level) is supplied to the gate bus line GL, and an inactive gate signal VGLB (inversion signal of VGL; L level) is supplied to the gate bus line. When supplied to GLB, the switches SW11, SW12, SW21, and SW22 are turned on, the inactive gate signal VGL (L level) is supplied to the gate bus line GL, and the active gate signal VGLB (inverted signal of VGL). ; H level) is supplied to the gate bus line GLB, the switches SW11, SW12, SW21, SW22 are turned off.

In the data selection unit 52, an active image data selection signal VSEL (H level) is supplied to the image data selection line SEL, and an inactive image data selection signal VSELB (inverted signal of VSEL; L level) is selected for image data. When supplied to the line SELB, the switches SW13 and SW14 are turned on, and the switches SW23 and SW24 are turned off. Further, an inactive image data selection signal VSEL (L level) is supplied to the image data selection line SEL, and an active image data selection signal VSELB (inverted signal of VSEL; H level) is supplied to the image data selection line SELB. Then, the switches SW13 and SW14 are turned off, and the switches SW23 and SW24 are turned on.

32. The driving method of the liquid crystal display device having the pixel P according to the modified example 2 of FIG. 32 is the same as the driving method shown in FIG.

The configurations of Modification 1 and Modification 2 can be similarly applied to the liquid crystal display device according to each embodiment of the present invention.

The liquid crystal display device of the present invention is not limited to the configuration shown in this embodiment mode. Hereinafter, another embodiment of the liquid crystal display device of the present invention will be described. For convenience of explanation, the terms defined in this embodiment are used in accordance with the definitions in this embodiment unless otherwise specified.

[Embodiment 2]
In the first embodiment, two images (first image and second image) are switched and displayed. However, the present invention is not limited to this, and three images or more images are displayed. It is good also as a structure which switches and displays. The liquid crystal display device according to the present embodiment has a configuration in which three images are held and switched to be displayed.

The schematic configuration of the liquid crystal display device according to the present embodiment includes a liquid crystal display panel 100 and a display control circuit 200 as in the first embodiment shown in FIG. 2, and the liquid crystal display panel 100 includes a source driver 300 and A gate driver 400, a display unit 500, and a memory operation driver 600 are included. The display control circuit 200 includes a memory drive control unit 20.

Unlike the first embodiment, the display unit 500 includes a first source bus line (first data signal line) SL1, a second source bus line (second data signal line), and a third source bus line (third data signal). A signal line SL3, a gate bus line GL, a first image data selection line SEL1, a second image data selection line SEL2, a high potential side power supply line VHL, and a low potential side power supply line VLL are included. The first source bus line SL1, the second source bus line SL2, and the third source bus line SL3 are connected to the source driver 300, the gate bus line GL is connected to the gate driver 400, and the first image data selection line SEL1. The second image data selection line SEL2, the high potential side power supply line VHL, and the low potential side power supply line VLL are connected to the memory driving driver 600.

The display unit 500 includes a plurality of pixels P, and corresponding to each pixel P, one gate bus line GL and three source bus lines (first source bus line SL1, second source bus line SL2, 3 source bus lines SL3), two image data selection lines (first image data selection line SEL1, second image data selection line SEL2), high potential side power supply line VHL, and low potential side power supply line VLL. Is provided. Each pixel P includes a pixel electrode PIX, a common electrode COM, and a liquid crystal layer. In addition, a storage unit is provided for each pixel P, and the storage unit includes three memory circuits as a storage circuit capable of holding 1-bit data (first memory circuit, second memory circuit, third memory). Circuit). Hereinafter, the first memory circuit is referred to as a first pixel memory MR1, the second memory circuit is referred to as a second pixel memory MR2, and the third memory circuit is referred to as a third pixel memory MR3.

The liquid crystal display device 10 according to the present embodiment performs display by holding the image data written in the pixel P in the first pixel memory MR1, the second pixel memory MR2, and the third pixel memory MR3 in the pixel P. More specifically, the liquid crystal display device 10 has an image data writing period in which image data is written, and an image data holding period in which display is performed while holding the written image data. For image data (for convenience, the first image data corresponding to the first image, the second image data corresponding to the second image, and the third image data corresponding to the third image), the first image data is the first pixel. In the memory MR1, the second image data is written in the second pixel memory MR2, the third image data is written in the third pixel memory MR3, and the first pixel is displayed when the first image is displayed in the image data holding period. When displaying with the first image data held in the memory MR1 and displaying the second image, the second image data held in the second pixel memory MR2 is switched to the second image data. Instead it is used to display, when displaying the third image performs display is switched to the third image data stored in the third pixel memory MR3.

The display control circuit 200 receives the data signal DAT, the first image data selection signal VSEL1 and the second image data selection signal VSEL2 sent from the outside, and displays the digital video signal DV (image data) and the image display on the display unit 500. A source start pulse signal SSP, a source clock signal SCK, a latch strobe signal LS, a gate start pulse signal GSP, and a gate clock signal GCK for controlling, and images to be displayed on the display unit 500 (first image, second image, first image) The first image data selection signal VSEL1 and the second image data selection signal VSEL2 for selecting (three images) are output.

The source driver 300 receives the digital video signal DV, the source start pulse signal SSP, the source clock signal SCK, and the latch strobe signal LS output from the display control circuit 200, and receives each source bus line (first source bus line SL1, first source bus line SL1). A driving video signal (image data) is applied to the two source bus lines SL2 and the third source bus lines SL3). Specifically, the first image data is applied to the first source bus line SL1, the second image data is applied to the second source bus line SL2, and the third image data is applied to the third source bus line SL3.

The gate driver 400 sequentially selects each gate bus line GL by one horizontal scanning period when writing image data (first image data, second image data, third image data) (image data writing period). In addition, based on the gate start pulse signal GSP and the gate clock signal GCK output from the display control circuit 200, an active scanning signal is sequentially applied to each gate bus line GL. As a result, in each pixel P in the same row (horizontal line), the first image data is simultaneously written in the first pixel memory MR1, the second image data is written in the second pixel memory MR2, and the third pixel memory MR3. The third image data is written in. In the image data holding period, the gate driver 400 stops applying the active scanning signal to each gate bus line GL and deactivates all the gate bus lines GL.

(Pixel circuit configuration)
FIG. 8 is a schematic diagram showing the configuration of the pixels of the liquid crystal display panel 100, and shows two pixels P in each of the (n−1), n, and (n + 1) rows. FIG. 9 is an equivalent circuit diagram showing the configuration of one pixel P. The pixel P includes a switch unit 50, a storage unit 51, a data selection unit 52, and a display element unit 53.

The switch unit 50 includes a first switch unit SW10, a second switch unit SW20, and a third switch unit SW30. The first switch unit SW10 and the second switch unit SW20 have the same configuration as that of FIG. The third switch unit SW30 includes an N-type switch SW31, a P-type switch SW32, and an inverter circuit INV31.

The switch SW31 has a control terminal connected to the gate bus line GL, one conduction terminal connected to the third source bus line SL3, and the other conduction terminal connected to the output terminal swout3 of the third switch unit SW30. The switch SW32 has a control terminal connected to the output terminal of the inverter circuit INV31, one conduction terminal connected to the third source bus line SL3, and the other conduction terminal connected to the output terminal swout3 of the third switch unit SW30. Yes. The input terminal of the inverter circuit INV31 is connected to the gate bus line GL.

The storage unit 51 includes a first pixel memory MR1, a second pixel memory MR2, and a third pixel memory MR3. The first pixel memory MR1 and the second pixel memory MR2 have the same configuration as that shown in FIG. The third pixel memory MR3 includes two inverter circuits INV32 and INV33.

The inverter circuit INV32 has an input terminal connected to the output terminal swout3 of the third switch unit SW30, and an output terminal of the inverter circuit INV32 connected to the output terminal mout3 of the third pixel memory MR3. The inverter circuit INV33 has an input terminal connected to the output terminal of the inverter circuit INV32, and an output terminal connected to the input terminal of the inverter circuit INV32.

The data selection unit 52 includes N-type switches SW13, SW23, SW33, P-type switches SW14, SW24, SW34, inverter circuits INV16, INV26, INV36, and a decoder 5.

The decoder 5 includes three NOR

circuits

5a, 5b, and 5c and two inverter circuits INVb and INVc, and receives the first image data selection signal VSEL1 and the second image data selection signal VSEL2. The NOR circuit 5a has one input terminal connected to the first image data selection line SEL1, the other input terminal connected to the second image data selection line SEL2, and an output terminal connected to the output terminal dcout1 of the decoder 5. Yes. The input terminal of the inverter circuit INVb is connected to the second image data selection line SEL2, and the input terminal of the inverter circuit INVc is connected to the first image data selection line SEL1. The NOR circuit 5b has one input terminal connected to the first image data selection line SEL1, the other input terminal connected to the output terminal of the inverter circuit INVb, and the output terminal connected to the output terminal dcout2 of the decoder 5. . The NOR circuit 5c has one input terminal connected to the output terminal of the inverter circuit INVc, the other input terminal connected to the second image data selection line SEL2, and the output terminal connected to the output terminal dcout3 of the decoder 5. .

The switch SW13 has a control terminal connected to the output terminal dcout1 of the decoder 5, one conduction terminal connected to the output terminal mout1 of the first pixel memory MR1, and the other conduction terminal connected to the output terminal selout of the data selection unit 52. Has been. The switch SW14 has a control terminal connected to the output terminal of the inverter circuit INV16, one conduction terminal connected to the output terminal mout1 of the first pixel memory MR1, and the other conduction terminal connected to the output terminal selout of the data selection unit 52. Has been. The input terminal of the inverter circuit INV16 is connected to the output terminal dcout1 of the decoder 5.

The switch SW23 has a control terminal connected to the output terminal dcout2 of the decoder 5, one conduction terminal connected to the output terminal mout2 of the second pixel memory MR2, and the other conduction terminal connected to the output terminal selout of the data selection unit 52. Has been. The switch SW24 has a control terminal connected to the output terminal of the inverter circuit INV26, one conduction terminal connected to the output terminal mout2 of the second pixel memory MR2, and the other conduction terminal connected to the output terminal selout of the data selection unit 52. Has been. The input terminal of the inverter circuit INV26 is connected to the output terminal dcout2 of the decoder 5.

The switch SW33 has a control terminal connected to the output terminal dcout3 of the decoder 5, one conduction terminal connected to the output terminal mout3 of the third pixel memory MR3, and the other conduction terminal connected to the output terminal selout of the data selection unit 52. Has been. The switch SW34 has a control terminal connected to the output terminal of the inverter circuit INV36, one conduction terminal connected to the output terminal mout3 of the third pixel memory MR3, and the other conduction terminal connected to the output terminal selout of the data selection unit 52. Has been. The input terminal of the inverter circuit INV36 is connected to the output terminal dcout3 of the decoder 5.

The display element unit 53 has the same configuration as that of FIG. 1, and image display is performed based on the output signal of the data selection unit 52 described above.

10 is a circuit diagram of the decoder 5. FIG. 11 shows a combination of the first image data selection signal VSEL1 and the second image data selection signal VSEL2, output signals a, b, c of the decoder 5, and a storage unit 51. Is a table showing the relationship with the pixel memory MR (MR1, MR2, MR3) selected from.

For example, when VSEL1 is “0” and VSEL2 is “0”, the output signal a of the terminal dcout1 of the decoder 5 is “1” (H level), and the output signal b of the terminal dcout2 is “0” (L level). The output signal c of the terminal dcout3 becomes “0” (L level). In this case, the switches SW13 and SW14 are turned on, and the data signal of the first pixel memory MR10 is input to the display element unit 53. When VSEL1 is “0” and VSEL2 is “1”, the output signal a of the terminal dcout1 of the decoder 5 is “0” (L level), and the output signal b of the terminal dcout2 is “1” (H level). The output signal c of the terminal dcout3 becomes “0” (L level). In this case, the switches SW23 and SW24 are turned on, and the data signal of the second pixel memory MR20 is input to the display element unit 53. When VSEL1 is “1” and VSEL2 is “0”, the output signal a of the terminal dcout1 of the decoder 5 is “0” (L level), and the output signal b of the terminal dcout2 is “0” (L level). The output signal c from the terminal dcout3 becomes “1” (H level). In this case, the switches SW33 and SW34 are turned on, and the data signal of the third pixel memory MR30 is input to the display element unit 53.

With the above configuration, it is possible to switch and display three images. Here, even when four or more images are switched and displayed, the same configuration can be realized. Specifically, when n images are switched and displayed, each pixel P is supported. This can be realized by providing n pixel memories MR and n source bus lines SL and generating the image data selection signal VSEL by a combination of known logic circuits.

Here, in the pixel P shown in FIG. 9 described above, the decoder 5 is included in the data selection unit 52, but the present liquid crystal display device 10 is not limited to this, and may have the following configuration. FIG. 12 is an equivalent circuit diagram showing a modification of the pixel P shown in FIG. As shown in FIG. 12, the decoder 5 is not provided for each pixel P, and one decoder 5 is provided in the memory driving driver 600 (see FIG. 2), and the output of the decoder 5 is input to each pixel P. The Specifically, the first image data selection signal VSEL1 and the second image data selection signal VSEL2 are input to the decoder 5 via the display control circuit 200, and the output signals a, b, and c of the decoder 5 are respectively applied to the pixels P. Is input to the data selection unit 52. That is, the terminal dcout1 of the decoder 5 is connected to the first selection line SELa, and the first selection line SELa is connected to the control terminal of the switch SW13 of each pixel P and the input terminal of the inverter circuit INV16. The terminal dcout2 of the decoder 5 is connected to the second selection line SELb, and the second selection line SELb is connected to the control terminal of the switch SW23 of each pixel P and the input terminal of the inverter circuit INV26. The terminal dcout3 of the decoder 5 is connected to the third selection line SELc, and the third selection line SELc is connected to the control terminal of the switch SW33 of each pixel P and the input terminal of the inverter circuit INV36. The relationship between the combination of the first image data selection signal VSEL1 and the second image data selection signal VSEL2 and the output signals a, b, c of the decoder 5 is as shown in FIG. According to the configuration of FIG. 12, it is not necessary to provide each pixel P with the decoder 5, so that the circuit configuration can be simplified.

[Embodiment 3]
In the first embodiment, two images are obtained from different source bus lines (first source bus line SL1 and second source bus line SL2) in two pixel memories (first pixel memory MR1 and second pixel memory MR2). Each of the data (first image data and second image data) is written, but the present invention is not limited to this, and one source bus line and two gate bus lines per pixel P And two image data may be written in each of the two pixel memories at different timings (time). The liquid crystal display device according to the present embodiment has the above-described configuration.

The overall configuration of the liquid crystal display device according to the present embodiment includes a liquid crystal display panel 100 and a display control circuit 200, as in the first embodiment shown in FIG. 2. The liquid crystal display panel 100 includes a source driver 300 and A gate driver 400, a display unit 500, and a memory operation driver 600 are included. The display control circuit 200 includes a memory drive control unit 20.

The display unit 500 includes a source bus line (data signal line) SL, a first gate bus line (first scanning signal line) GL1, a second gate bus line (second scanning signal line) GL2, an image data selection line SEL, A high potential side power supply line VHL and a low potential side power supply line VLL are included. The source bus line SL is connected to the source driver 300, the first gate bus line GL1 and the second gate bus line GL2 are connected to the gate driver 400, the image data selection line SEL, the high potential side power supply line VHL, and the low The potential power supply line VLL is connected to the memory driving driver 600.

The display unit 500 includes a plurality of pixels P, and corresponding to each pixel P, there are two gate bus lines (first gate bus line GL1, second gate bus line GL2) and one source bus line SL. The image data selection line SEL, the high potential side power supply line VHL, and the low potential side power supply line VLL are provided. Each pixel P includes a pixel electrode PIX, a common electrode COM, and a liquid crystal layer. In addition, a storage unit is provided for each pixel P, and the storage unit is provided with two memory circuits (first memory circuit and second memory circuit) each as a storage circuit capable of holding 1-bit data. Yes. Hereinafter, the first memory circuit is referred to as a first pixel memory MR1, and the second memory circuit is referred to as a second pixel memory MR2.

The liquid crystal display device 10 according to the present embodiment performs display by holding the image data written in the pixel P in the first pixel memory MR1 and the second pixel memory MR2 in the pixel P. More specifically, the liquid crystal display device 10 has an image data writing period in which image data is written and an image data holding period in which display is performed while holding the written image data. For image data (first image data corresponding to the first image and second image data corresponding to the second image), the first image data is written in the first pixel memory MR1, and the second image data is stored in the second pixel. In the image data holding period written in the memory MR2, when displaying the first image, display is performed using the first image data held in the first pixel memory MR1, and when displaying the second image, The display is switched to the second image data held in the second pixel memory MR2.

As in the first embodiment, the display control circuit 200 receives the data signal DAT and the image data selection signal VSEL sent from the outside, and controls the digital video signal DV (image data) and the image display on the display unit 500. Source start pulse signal SSP, source clock signal SCK, latch strobe signal LS, gate start pulse signal GSP, and gate clock signal GCK, and an image (first image, second image) to be displayed on the display unit 500 The image data selection signal VSEL is output.

The source driver 300 receives the digital video signal DV, the source start pulse signal SSP, the source clock signal SCK, and the latch strobe signal LS output from the display control circuit 200, and drives the video signal (image) for each source bus line SL. Data). Each source bus line SL has a video signal (first image data) corresponding to the first image (white solid image) and a video signal (second image data) corresponding to the second image (black solid image). ) Are alternately supplied.

When the gate driver 400 writes image data (first image data, second image data) (image data writing period), the gate driver 400 sequentially selects each gate bus line GL one horizontal scanning period at a time. Based on the gate start pulse signal GSP output from the gate 200 and the gate clock signal GCK, an active scanning signal is sequentially applied to each gate bus line GL. Specifically, in each pixel, the second image data is first written in the second pixel memory MR2 when the second gate bus line GL2 is selected, and then the first gate bus line GL1 is selected. First image data is written into the one-pixel memory MR1. In the image data holding period, the gate driver 400 stops applying the active scanning signal to each gate bus line GL and deactivates all the gate bus lines GL.

(Pixel circuit configuration)
FIG. 13 is a schematic diagram showing the configuration of the pixels of the liquid crystal display panel 100, and shows two pixels in each of the (n−1) row, the n row, and the (n + 1) row. FIG. 14 is an equivalent circuit diagram showing a configuration of one pixel P. The pixel P includes a switch unit 50, a storage unit 51, a data selection unit 52, and a display element unit 53.

The switch unit 50 includes a first switch unit SW10 and a second switch unit SW20. The first switch unit SW10 includes switches SW11 and SW12 and an inverter circuit INV11. The second switch unit SW20 includes switches SW21, SW22, And an inverter circuit INV21.

The switch SW11 has a control terminal connected to the first gate bus line GL1, one conduction terminal connected to the source bus line SL, and the other conduction terminal connected to the output terminal swout1 of the first switch unit SW10. The switch SW12 has a control terminal connected to the output terminal of the inverter circuit INV11, one conduction terminal connected to the source bus line SL, and the other conduction terminal connected to the output terminal swout1 of the first switch unit SW10. The input terminal of the inverter circuit INV11 is connected to the first gate bus line GL1.

The switch SW21 has a control terminal connected to the second gate bus line GL2, one conduction terminal connected to the source bus line SL, and the other conduction terminal connected to the output terminal swout2 of the second switch unit SW20. The switch SW22 has a control terminal connected to the output terminal of the inverter circuit INV21, one conduction terminal connected to the source bus line SL, and the other conduction terminal connected to the output terminal swout2 of the second switch unit SW20. The input terminal of the inverter circuit INV21 is connected to the second gate bus line GL2.

The storage unit 51, the data selection unit 52, and the display element unit 53 have the same configuration as that of the first embodiment shown in FIG.

(Driving method)
Next, a driving method in the present embodiment will be described with reference to FIGS. FIG. 15 is a timing chart showing a driving method (normally black mode) of the liquid crystal display device 10 of FIG. VSL is the first image data (image data corresponding to white: H level (“1”)) and second image data (image data corresponding to black: L level (“0”) supplied to the source bus line SL. )), And VGL2 (n−1), VGL2n, and VGL2 (n + 1) are the second gate bus lines GL2 (n−) of the (n−1) th row, the nth row, and the (n + 1) th row, respectively. 1), the second gate signal (second scanning signal) supplied to GL2n, GL2 (n + 1), and VGL1 (n−1), VGL1n, VGL1 (n + 1) are respectively in the (n−1) th row, Indicates the first gate signal (first scanning signal) supplied to the first gate bus lines GL1 (n−1), GL1n, GL1 (n + 1) of the nth row and the (n + 1) th row, and VSEL indicates image data selection Image supplied to line SEL Indicates a data selection signal, VMR1 (n−1), VMR1n, VMR1 (n + 1) respectively indicate the potential of the first pixel memory MR1 in the (n−1) th row, the nth row, and the (n + 1) th row, VMR2 (n−1), VMR2n, VMR2 (n + 1) respectively indicate the potentials of the second pixel memory MR2 in the (n−1) th row, the nth row, and the (n + 1) th row, and VP (n−1) , VPn, VP (n + 1) respectively indicate the potentials (pixel potentials) of the pixel electrodes PIX in the (n−1) th row, the nth row, and the (n + 1) th row. As described above, the display image is switched between the first image data and the second image data, and this switching is performed based on the image data selection signal VSEL sent from the outside to the display control circuit 200. Hereinafter, the image data. Driving method for writing period 4 will be described in order, and in FIG.4, the first image displayed by the first image data is a white solid image, and the second image displayed by the second image data is A case of a black solid image is shown.

(Driving method for image data writing period)
In FIG. 15, image data is written from time t1 to time t2. In the image data writing period, active signals are sequentially supplied to the gate bus lines GL2 (n−1), GL1 (n−1), GL2n, GL1n, GL2 (n + 1), and GL1 (n + 1) in order for a predetermined period. . A high (H) level or low (L) level image data selection signal VSEL is supplied to the image data selection line SEL. Here, it is assumed that an H level image data selection signal VSEL is supplied.

Here, focusing on the pixel Pn in the n-th row, when an active signal (H level) is applied to the second gate bus line GL2n provided corresponding to the pixel Pn, the switch SW21 is turned on. . At the same time, the H level signal is input to the inverter circuit INV21, and the output signal of the inverted level (L level) is applied to the switch SW22, so that the switch SW22 is also turned on.

Thus, the second image data (image data corresponding to black: L level (“0”)) supplied to the source bus line SL is input to the second pixel memory MR2 of the storage unit 51 via the switch SW12. Is done.

In the second pixel memory MR2, when an L level signal is input to the inverter circuit INV22, an H level signal is input to the inverter circuit INV23, whereby an L level signal is input to the inverter circuit INV22 again. In this way, the L level signal is held in the second pixel memory MR2 (“VMR2n” in FIG. 15). The H level signal output from the inverter circuit INV22 is provided to the switches SW23 and SW24 of the data selection unit 52 as the output of the second pixel memory MR2.

Since the H-level image data selection signal VSEL is input to the data selection unit 52, the switch SW24 is turned off. Further, since the L level signal is supplied to the SW 23 via the inverter circuit INV14, the switch SW23 is turned off. Thereby, the H level signal of the second pixel memory MR2 is not output from the data selection unit 52.

Next, when an active signal (H level) is applied to the first gate bus line GLn1 provided corresponding to the pixel Pn, the switch SW11 is turned on. At the same time, an H level signal is input to the inverter circuit INV11, and an output signal of the inverted level (L level) is applied to the switch SW12, so that the switch SW12 is also turned on.

As a result, the first image data (image data corresponding to white: H level (“1”)) supplied to the source bus line SL is input to the first pixel memory MR1 of the storage unit 51 via the switch SW11. Is done.

In the first pixel memory MR1, when an H level signal is input to the inverter circuit INV12, an L level signal is input to the inverter circuit INV13, whereby an H level signal is input to the inverter circuit INV12 again. In this way, an H level signal is held in the first pixel memory MR1 (“VMR1n” in FIG. 15). The L level signal output from the inverter circuit INV12 is provided to the switches SW13 and SW14 of the data selection unit 52 as the output of the first pixel memory MR1.

Since the H-level image data selection signal VSEL is input to the data selection unit 52, the switch SW13 is turned on and the switch SW24 is kept off. Further, since the L level signal is supplied to the switches SW14 and SW23 via the inverter circuit INV14, the switch SW14 is turned on and the switch SW23 is kept off. As a result, an L level signal of the first pixel memory MR <b> 1 is output from the data selection unit 52 and input to the display element unit 53.

In the display element section 53, an L level signal is applied to the switches SW15 and SW26, and an H level signal is applied to the switches SW16 and SW25 via the inverter INV15. Therefore, the switches SW15 and SW16 are turned off, and the switches SW25 and SW26 are turned on. As a result, the voltage (H level) of the high potential side power supply line VHL is applied to the pixel electrode PIX, and white is displayed in the pixel Pn (“VPn” in FIG. 15). The same operation is performed on the pixels adjacent to the pixel Pn, and a white solid image is displayed.

(Driving method for image data retention period)
In the image data holding period, the same operation as that of the first embodiment shown in FIG. 4 is performed. That is, during the period from time t2 to time t3, the H level image data selection signal VSEL is supplied to the image data selection line SEL, whereby the output signal (L level) of the first pixel memory MR1 from the data selection unit 52. Is output. Thereby, the voltage (H level) of the high potential side power supply line VHL is continuously applied to the pixel electrode PIX, and white display is maintained in the pixel Pn (“VPn” in FIG. 15). On the other hand, after time point 2, the L-level image data selection signal VSEL is supplied to the image data selection line SEL, so that the output signal (H level) of the second pixel memory MR 2 is output from the data selection unit 52. . As a result, the voltage (L level) of the low potential side power supply line VLL is applied to the pixel electrode PIX, and the pixel Pn switches to black display (“VPn” in FIG. 15).

As described above, in the image data holding period, display is performed using the image data held in the storage unit 51, and the first image data held in the first pixel memory MR1 and the first image data based on the image data selection signal VSEL The second image data held in the second pixel memory MR2 can be switched and displayed.

Needless to say, the driving method shown in FIGS. 5 and 6 and the configuration of the modified example shown in FIG. 7 are also applicable to this embodiment.

[Embodiment 4]
In the liquid crystal display device according to the present embodiment, the liquid crystal display device according to the third embodiment has a configuration including three pixel memories MR, holds three images, and performs display by switching between them. is there.

Unlike the third embodiment, the display unit 500 includes a source bus line (data signal line) SL, a first gate bus line (first scanning signal line) GL1, and a second gate bus line (second scanning signal line). GL2, a third gate bus line (third scanning signal line) GL3, a first image data selection line SEL1, a second image data selection line SEL2, a high potential side power supply line VHL, and a low potential side power supply line VLL are included. Yes. The source bus line SL is connected to the source driver 300, and the first gate bus line GL1, the second gate bus line GL2, and the third gate bus line GL3 are connected to the gate driver 400, and the first image data selection line SEL1. The second image data selection line SEL2, the high potential side power supply line VHL, and the low potential side power supply line VLL are connected to the memory driving driver 600.

The display unit 500 includes a plurality of pixels P, and corresponding to each pixel P, three gate bus lines (first gate bus line GL1, second gate bus line GL2, third gate bus line GL3) and 1 There are provided one source bus line, two image data selection lines (first image data selection line SEL1, second image data selection line SEL2), a high potential side power supply line VHL, and a low potential side power supply line VLL. It has been. Each pixel P includes a pixel electrode PIX, a common electrode COM, and a liquid crystal layer. In addition, a storage unit is provided for each pixel P, and the storage unit includes three memory circuits as a storage circuit capable of holding 1-bit data (first memory circuit, second memory circuit, third memory). Circuit). Hereinafter, the first memory circuit is referred to as a first pixel memory MR1, the second memory circuit is referred to as a second pixel memory MR2, and the third memory circuit is referred to as a third pixel memory MR3.

The source driver 300 receives the digital video signal DV, the source start pulse signal SSP, the source clock signal SCK, and the latch strobe signal LS output from the display control circuit 200, and drives the video signal (image) for each source bus line SL. Data). Each source bus line SL has a video signal corresponding to the first image (first image data), a video signal corresponding to the second image (second image data), and a video signal corresponding to the third image. (Third image data) are supplied in order.

The gate driver 400 sequentially selects each gate bus line GL by one horizontal scanning period when writing image data (first image data, second image data, third image data) (image data writing period). In addition, based on the gate start pulse signal GSP and the gate clock signal GCK output from the display control circuit 200, an active scanning signal is sequentially applied to each gate bus line GL. Specifically, in each pixel, the third image data is written in the third pixel memory MR3 by first selecting the third gate bus line GL3, and then the second gate bus line GL2 is selected to select the second image data. Second image data is written to the two-pixel memory MR2, and then the first image data is written to the first pixel memory MR1 by selecting the first gate bus line GL1. In the image data holding period, the gate driver 400 stops applying the active scanning signal to each gate bus line GL and deactivates all the gate bus lines GL.

(Pixel circuit configuration)
FIG. 16 is a schematic diagram showing the configuration of the pixels of the liquid crystal display panel 100, and shows two pixels P in each of the (n−1) row, the n row, and the (n + 1) row. FIG. 17 is an equivalent circuit diagram showing the configuration of one pixel P. The pixel P includes a switch unit 50, a storage unit 51, a data selection unit 52, and a display element unit 53.

The switch unit 50 includes a first switch unit SW10, a second switch unit SW20, and a third switch unit SW30. The first switch unit SW10 and the second switch unit SW20 have the same configuration as that shown in FIG. The third switch unit SW30 includes an N-type switch SW31, a P-type switch SW32, and an inverter circuit INV31.

The switch SW31 has a control terminal connected to the third gate bus line GL3, one conduction terminal connected to the source bus line SL, and the other conduction terminal connected to the output terminal swout3 of the third switch unit SW30. The switch SW32 has a control terminal connected to the output terminal of the inverter circuit INV31, one conduction terminal connected to the source bus line SL, and the other conduction terminal connected to the output terminal swout3 of the third switch unit SW30. The input terminal of the inverter circuit INV31 is connected to the third gate bus line GL3.

The decoder 5 includes three NOR

circuits

The decoder 5 has the same configuration as in FIG. Therefore, the combination of the first image data selection signal VSEL1 and the second image data selection signal VSEL2, the output signals a, b, c of the decoder 5, and the pixel memory MR (MR1, MR2, MR3) selected from the storage unit 51. Is as shown in the table of FIG.

With the above configuration, it is possible to switch and display three images. Here, even when four or more images are switched and displayed, the same configuration can be realized. Specifically, when n images are switched and displayed, each pixel corresponds to each pixel. This can be realized by providing n pixel memories MR and n gate bus lines GL and generating the image data selection signal VSEL by a combination of known logic circuits.

Here, in the pixel P shown in FIG. 17, the decoder 5 is included in the data selection unit 52, but the present liquid crystal display device 10 is not limited to this, and may have the following configuration. FIG. 18 is an equivalent circuit diagram showing a modification of the pixel P shown in FIG. As shown in FIG. 18, the decoder 5 is not provided in each pixel P, and one decoder 5 is provided in the memory driving driver 600 (see FIG. 2). Since the connection relationship between the decoder 5 and the data selection unit 52 is the same as that shown in FIG. 12, the description thereof is omitted here. According to the configuration of FIG. 18, it is not necessary to provide each pixel P with the decoder 5, so that the circuit configuration can be simplified.

[Embodiment 5]
In the liquid crystal display device 10 according to the present embodiment, in addition to the function for performing still image display (memory operation mode) shown in Embodiment 1, the function for performing normal moving image (gradation) display (normal operation mode) And has a configuration for performing display by switching between the normal operation mode and the memory operation mode.

FIG. 19 is a block diagram showing an overall configuration of the liquid crystal display device according to the present embodiment. The liquid crystal display device 10 includes a liquid crystal display panel 100 and a display control circuit 200. The liquid crystal display panel 100 includes a source driver 300, a gate driver 400, a display unit 500, and a memory operation driver 600. . The display control circuit 200 includes a memory drive control unit 20.

The display unit 500 includes a first source bus line (first data signal line) SL1, a second source bus line (second data signal line), a gate bus line GL, an image data selection line SEL, and a high-potential-side power supply line VHL. , A low potential side power supply line VLL, a first operation mode switching line MSL1, and a second operation mode switching line MSL2. The first source bus line SL1 and the second source bus line SL2 are connected to the source driver 300, the gate bus line GL is connected to the gate driver 400, the image data selection line SEL, the high potential side power supply line VHL, the low The potential side power supply line VLL, the first operation mode switching line MSL1, and the second operation mode switching line MSL2 are connected to the memory driving driver 600.

The display unit 500 includes a plurality of pixels P, and corresponding to each pixel P, one gate bus line GL and two source bus lines (first source bus line SL1, second source bus line SL2), An image data selection line SEL, a high potential side power supply line VHL, a low potential side power supply line VLL, a first operation mode switching line MSL1, and a second operation mode switching line MSL2 are provided. Each pixel P includes a pixel electrode PIX, a common electrode COM, and a liquid crystal layer. If necessary, a storage capacitor (also referred to as an auxiliary capacitor) is provided in parallel with a liquid crystal capacitor Clc formed by the pixel electrode PIX and the common electrode COM. Is added). In addition, a storage unit is provided for each pixel P, and the storage unit is provided with two memory circuits (first memory circuit and second memory circuit) each as a storage circuit capable of holding 1-bit data. Yes. Hereinafter, the first memory circuit is referred to as a first pixel memory MR1, and the second memory circuit is referred to as a second pixel memory MR2.

The display control circuit 200 receives a data signal DAT, an image data selection signal VSEL, and an operation mode switching signal VMSL sent from the outside, and controls a digital video signal DV (image data) and an image display on the display unit 500. To select the start pulse signal SSP, the source clock signal SCK, the latch strobe signal LS, the gate start pulse signal GSP, and the gate clock signal GCK and an image (first still image and second still image) to be displayed on the display unit 500. Image data selection signal VSEL and an operation mode switching signal VMSL for switching between the normal operation mode and the memory operation mode are output.

The source driver 300 receives the digital video signal DV, the source start pulse signal SSP, the source clock signal SCK, and the latch strobe signal LS output from the display control circuit 200, and receives each source bus line (first source bus line SL1, first source bus line SL1). A driving video signal (image data) is applied to the 2-source bus line SL2). Specifically, moving image data (moving image data) and still image data (first still image data) are applied to the first source bus line SL1, and the second source bus line SL2 is stationary. Image image data (second still image data) is applied.

When the gate driver 400 writes image data (moving image data, first still image data, and second still image data), the gate driver 400 sequentially selects each gate bus line GL by one horizontal scanning period. Based on the gate start pulse signal GSP output from the gate 200 and the gate clock signal GCK, an active scanning signal is sequentially applied to each gate bus line GL. Thereby, in each pixel P in the same row (horizontal line), in the normal operation mode, moving image data (gradation data) is directly written to the pixel electrode, and in the memory operation mode, the first pixel memory MR1 has the first data. Still image data is written, and second still image data is written in the second pixel memory MR2. In the image data holding period in the memory operation mode, the gate driver 400 stops the application of the active scanning signal to each gate bus line GL and deactivates all the gate bus lines GL.

(Pixel circuit configuration)
FIG. 20 is a schematic diagram showing the configuration of the pixels of the liquid crystal display panel 100, and shows two pixels P in each of the (n−1) row, the n row, and the (n + 1) row. FIG. 21 is an equivalent circuit diagram showing a configuration of one pixel P. The pixel P includes a switch unit 50, a storage unit 51, a data selection unit 52, a display element unit 53, and a display mode switching unit 54.

The switch unit 50, the storage unit 51, and the data selection unit 52 have the same configuration as the pixel P in FIG.

The display mode switching unit 54 includes N-type switches SW1 and SW3 and P-type switches SW2 and SW4. The switch SW1 has a control terminal connected to the second operation mode switching line MSL2, one conduction terminal connected to the output terminal swout1 of the first switch unit SW10, and the other conduction terminal connected to the inverter circuit INV12 of the first pixel memory MR1. Connected to the input terminal. The switch SW2 has a control terminal connected to the first operation mode switching line MSL1, one conduction terminal connected to the output terminal swout1 of the first switch unit SW10, and the other conduction terminal connected to the inverter circuit INV12 of the first pixel memory MR1. Connected to the input terminal. The switch SW3 has a control terminal connected to the first operation mode switching line MSL1, one conduction terminal connected to the output terminal swout1 of the first switch unit SW10, and the other conduction terminal connected to the pixel electrode PIX. The switch SW4 has a control terminal connected to the second operation mode switching line MSL2, one conduction terminal connected to the output terminal swout1 of the first switch unit SW10, and the other conduction terminal connected to the pixel electrode PIX.

The display element unit 53 includes N-type switches SW15, SW25 and SW5, P-type switches SW16, SW26 and SW6, an inverter circuit INV15, a pixel electrode PIX, a counter electrode COM, a liquid crystal capacitor Clc, and a holding capacitor Ch. The switch SW15 has a control terminal connected to the output terminal selout of the data selection unit 52, and one conduction terminal connected to the low-potential side power supply line VLL. The switch SW16 has a control terminal connected to the output terminal of the inverter circuit INV15, and one conduction terminal connected to the low-potential-side power line VLL. The switch SW25 has a control terminal connected to the output terminal of the inverter circuit INV15, and one conduction terminal connected to the high potential side power supply line VHL. The switch SW26 has a control terminal connected to the output terminal selout of the data selection unit 52, and one conduction terminal connected to the high potential side power supply line VHL. The switch SW5 has a control terminal connected to the second operation mode switching line MSL2, one conduction terminal connected to the other conduction terminal of each of the switches SW15, SW16, SW25, and SW26, and the other conduction terminal connected to the pixel electrode PIX. It is connected. The switch SW6 has a control terminal connected to the first operation mode switching line MSL1, one conduction terminal connected to the other conduction terminal of each of the switches SW15, SW16, SW25, and SW26, and the other conduction terminal connected to the pixel electrode PIX. It is connected. A liquid crystal capacitor Clc is formed between the pixel electrode PIX and the counter electrode COM, and a holding capacitor Ch (also referred to as an auxiliary capacitor) is formed in parallel with the liquid crystal capacitor Clc.

(Driving method)
Next, a driving method in the present embodiment will be described with reference to FIGS. FIG. 22 is a timing chart showing a driving method (normally black mode) of the present liquid crystal display device 10. VSL1 is moving image data (gradation data) and first still image data supplied to the first source bus line SL1, and VSL2 is a signal of second still image data supplied to the second source bus line SL2. VGL (n−1), VGLn, and VGL (n + 1) are the gate bus lines GL (n−1), GLn, GL of the (n−1) th row, the nth row, and the (n + 1) th row, respectively. (N + 1) indicates a gate signal (scanning signal) supplied, VMSL1 indicates a first operation mode switching signal supplied to the first operation mode switching line MSL1, and VMSL2 is supplied to the second operation mode switching line MSL2 A second operation mode switching signal (inverted signal of VMSL1), VSEL indicates an image data selection signal supplied to the image data selection line SEL, and VMR1 (n− ), VMR1n, VMR1 (n + 1) indicate the potentials of the first pixel memory MR1 in the (n-1) th row, the nth row, and the (n + 1) th row, respectively. VMR2 (n-1), VMR2n, VMR2 ( n + 1) indicates the potential of the second pixel memory MR2 in the (n−1) th row, the nth row, and the (n + 1) th row, respectively, and VP (n−1), VPn, and VP (n + 1) are respectively ( The potential (pixel potential) of the pixel electrode PIX in the (n-1) th row, the nth row, and the (n + 1) th row is shown.

In the present embodiment, as described above, moving image (gradation) display is performed in the normal operation mode, and the first still image and the second still image are switched and displayed at a desired timing in the memory operation mode. . The switching of the operation mode and the switching between the first still image and the second still image are performed based on the operation mode switching signals VMSL1, VMSL2, and the image data selection signal VSEL sent from the outside to the display control circuit 200. Is called. Hereinafter, the driving method in the normal operation mode, the driving method in the image data writing period and the driving method in the image data holding period in the memory operation mode will be described in order. In FIG. 22, in the memory operation mode, the first still image displayed by the first still image data is a white solid image, and the second still image displayed by the second still image data is a black solid image. The case is shown.

(Driving method in normal operation mode)
In FIG. 22, a normal gradation display operation is performed from time t0 to time t1. An active signal is supplied to each gate bus line GL (n−1), GLn, GL (n + 1) in order for a predetermined period. A high (H) level or low (L) level image data selection signal VSEL is supplied to the image data selection line SEL. Here, it is assumed that an H level image data selection signal VSEL is supplied.

The first operation mode switching line MSL1 is supplied with a first (H) level first operation mode switching signal VMSL1, and the second operation mode switching line MSL2 is supplied with a second (L) level second operation mode switching signal VMSL2. Is supplied. As a result, the switches SW1, SW2, SW5, and SW6 are turned off, and the switches SW3 and SW4 are turned on.

As a result, the gradation data (image data corresponding to white) supplied to the first source bus line SL1 is applied to the pixel electrode PIX via the switches SW11, SW12, SW3, and SW4, and the white level is generated in the pixel Pn. Key is displayed ("VPn" in FIG. 22). In the normal operation mode, the supply of image data to the second source bus line SL2 is stopped.

(Memory operation mode; image data writing period driving method)
In FIG. 22, at time t1, the first operation mode switching signal VMSL1 at L level is supplied to the first operation mode switching line MSL1, and the second operation mode switching signal VMSL2 at H level is supplied to the second operation mode switching line MSL2. Supplied. As a result, the switches SW1, SW2, SW5, and SW6 are turned on, and the switches SW3 and SW4 are turned off. Then, an active signal is supplied to each gate bus line GL (n−1), GLn, GL (n + 1) in order for a predetermined period.

Focusing on the pixel Pn in the n-th row, when an active signal (H level) is applied to the gate bus line GLn provided corresponding to the pixel Pn, the switches SW11 and SW21 are turned on. At the same time, the H level signal is input to the inverter circuits INV11 and INV21, and the inverted level (L level) output signal is applied to the switches SW12 and SW22, so that the switches SW12 and SW22 are also turned on.

Accordingly, the first still image data (image data corresponding to white: H level (“1”)) supplied to the first source bus line SL1 is stored in the storage unit via the switches SW11, SW12, SW1, and SW2. The second still image data (image data corresponding to black: L level (“0”)) input to the first pixel memory MR1 of 51 and supplied to the second source bus line SL2 is supplied to the switches SW21 and SW22. To the second pixel memory MR2 of the storage unit 51.

In the first pixel memory MR1, when an H level signal is input to the inverter circuit INV12, an L level signal is input to the inverter circuit INV13, whereby an H level signal is input to the inverter circuit INV12 again. In this way, an H level signal is held in the first pixel memory MR1 (“VMR1n” in FIG. 22). The L level signal output from the inverter circuit INV12 is provided to the switches SW13 and SW14 of the data selection unit 52 as the output of the first pixel memory MR1.

In the second pixel memory MR2, when an L level signal is input to the inverter circuit INV22, an H level signal is input to the inverter circuit INV23, whereby an L level signal is input to the inverter circuit INV22 again. In this way, the L level signal is held in the second pixel memory MR2 (“VMR2n” in FIG. 22). The H level signal output from the inverter circuit INV22 is provided to the switches SW23 and SW24 of the data selection unit 52 as the output of the second pixel memory MR2.

In the display element section 53, an L level signal is applied to the switches SW15 and SW26, and an H level signal is applied to the switches SW16 and SW25 via the inverter INV15. Therefore, the switches SW15 and SW16 are turned off, and the switches SW25 and SW26 are turned on. Thereby, the voltage (H level) of the high potential side power supply line VHL is applied to the pixel electrode PIX, and white is displayed in the pixel Pn (“VPn” in FIG. 22). The same operation is performed on the pixels adjacent to the pixel Pn, and a white solid image is displayed.

(Memory operation mode; image data retention period driving method)
The image data holding period is the same as that shown in FIG. Thus, the display is performed by the first image data (white) stored in the first pixel memory MR1 from the time point t2 to the time point t3 (“VPn” in FIG. 22), and in the second pixel memory MR2 after the time point t3. Display is performed using the stored second image data (black) (“VPn” in FIG. 22). In other words, in the image data holding period, display is performed using still image data held in the storage unit 51, and the first still image data held in the first pixel memory MR1 is supported based on the image data selection signal VSEL. The first still image and the second still image corresponding to the second still image data held in the second pixel memory MR2 can be switched and displayed.

(Modification)
FIG. 23 is an equivalent circuit diagram showing a modification of the pixel P in FIG. In the pixel P of FIG. 23, the switches SW12, SW22, SW2, SW3, SW6, the inverter circuits INV11, INV21, and the first operation mode switching line MSL1 in the pixel P of FIG. 21 are schematically omitted.

According to this configuration, when the L-level second operation mode switching signal VMSL2 is supplied to the second operation mode switching line MSL2 (normal operation mode), the switches SW1 and SW5 are turned off and the switch SW4 is turned on. Become. Thereby, the gradation data (image data corresponding to white) supplied to the first source bus line SL1 is applied to the pixel electrode PIX via the switches SW11 and SW4, and the white gradation is displayed in the pixel Pn. The

Further, when the H-level second operation mode switching signal VMSL2 is supplied to the second operation mode switching line MSL2, the switches SW1 and SW5 are turned on, the switch SW4 is turned off, and the memory operation mode is entered. Subsequent operations are the same as those shown in FIG.

[Embodiment 6]
In the liquid crystal display device 10 according to the present embodiment, in addition to the function of performing still image display (memory operation mode) described in the second embodiment, a function of performing normal moving image (gradation) display (normal operation mode) And has a configuration for performing display by switching between the normal operation mode and the memory operation mode.

The schematic configuration of the liquid crystal display device according to the present embodiment includes a liquid crystal display panel 100 and a display control circuit 200, as in the fifth embodiment shown in FIG. 19, and the liquid crystal display panel 100 includes a source driver 300 and A gate driver 400, a display unit 500, and a memory operation driver 600 are included. The display control circuit 200 includes a memory drive control unit 20.

The display unit 500 includes a first source bus line (first data signal line) SL1, a second source bus line (second data signal line), a third source bus line (third data signal line) SL3, and a gate bus line. GL, first image data selection line SEL1, second image data selection line SEL2, high potential side power supply line VHL, low potential side power supply line VLL, first operation mode switching line MSL1, and second operation mode switching line MSL2 include. The first source bus line SL1, the second source bus line SL2, and the third source bus line SL3 are connected to the source driver 300, the gate bus line GL is connected to the gate driver 400, and the first image data selection line SEL1. The second image data selection line SEL2, the high potential side power supply line VHL, the low potential side power supply line VLL, the first operation mode switching line MSL1, and the second operation mode switching line MSL2 are connected to the memory driving driver 600. ing.

The display unit 500 includes a plurality of pixels P, and corresponding to each pixel P, one gate bus line GL and three source bus lines (first source bus line SL1, second source bus line SL2, 3 source bus lines SL3), two image data selection lines (first image data selection line SEL1, second image data selection line SEL2), high potential side power supply line VHL, low potential side power supply line VLL, A first operation mode switching line MSL1 and a second operation mode switching line MSL2 are provided. Each pixel P includes a pixel electrode PIX, a common electrode COM, and a liquid crystal layer. If necessary, a storage capacitor (also referred to as an auxiliary capacitor) is provided in parallel with a liquid crystal capacitor Clc formed by the pixel electrode PIX and the common electrode COM. Is added). In addition, a storage unit is provided for each pixel P, and the storage unit includes three memory circuits as a storage circuit capable of holding 1-bit data (first memory circuit, second memory circuit, third memory). Circuit).

The display control circuit 200 receives a data signal DAT, an image data selection signal VSEL, and an operation mode switching signal VMSL sent from the outside, and controls a digital video signal DV (image data) and an image display on the display unit 500. Start pulse signal SSP, source clock signal SCK, latch strobe signal LS, gate start pulse signal GSP, and gate clock signal GCK, and images to be displayed on display unit 500 (first still image, second still image, third still image) The first image data selection signal VSEL1 and the second image data selection signal VSEL2 for selecting, and the operation mode switching signal VMSL for switching between the normal operation mode and the memory operation mode are output.

The source driver 300 receives the digital video signal DV, the source start pulse signal SSP, the source clock signal SCK, and the latch strobe signal LS output from the display control circuit 200, and receives each source bus line (first source bus line SL1, first source bus line SL1). A driving video signal (image data) is applied to the two source bus lines SL2 and the third source bus lines SL3). Specifically, moving image data (moving image data) and still image data (first still image data) are applied to the first source bus line SL1, and the second source bus line SL2 is stationary. Image data for image (second still image data) is applied, and image data for still image (third still image data) is applied to the third source bus line SL3.

When writing image data (moving image data, first still image data, second still image data, and third still image data), the gate driver 400 sequentially selects each gate bus line GL by one horizontal scanning period. Therefore, based on the gate start pulse signal GSP and the gate clock signal GCK output from the display control circuit 200, an active scanning signal is sequentially applied to each gate bus line GL. As a result, in each pixel P in the same row (horizontal line), in the normal operation mode, moving image data (gradation data) is directly written to the pixel electrode, and in the memory operation mode, simultaneously in the first pixel memory MR1. The first image data is written, the second image data is written to the second pixel memory MR2, and the third image data is written to the third pixel memory MR3. In the image data holding period in the memory operation mode, the gate driver 400 stops the application of the active scanning signal to each gate bus line GL and deactivates all the gate bus lines GL.

(Pixel circuit configuration)
FIG. 24 is a schematic diagram showing the configuration of the pixels of the liquid crystal display panel 100, and shows two pixels P in each of the (n-1), n, and (n + 1) rows. FIG. 25 is an equivalent circuit diagram showing a configuration of one pixel P. The pixel P includes a switch unit 50, a storage unit 51, a data selection unit 52, a display element unit 53, and a display mode switching unit 54.

The display element unit 53 includes N-type switches SW15, SW25 and SW5, P-type switches SW16, SW26 and SW6, an inverter circuit INV15, a pixel electrode PIX, a counter electrode COM, a liquid crystal capacitor Clc, and a holding capacitor Ch. The switch SW15 has a control terminal connected to the output terminal selout of the data selection unit 52, and one conduction terminal connected to the low-potential side power supply line VLL. The switch SW16 has a control terminal connected to the output terminal of the inverter circuit INV15, and one conduction terminal connected to the low-potential-side power line VLL. The switch SW25 has a control terminal connected to the output terminal of the inverter circuit INV15, and one conduction terminal connected to the high potential side power supply line VHL. The switch SW26 has a control terminal connected to the output terminal selout of the data selection unit 52, and one conduction terminal connected to the high potential side power supply line VHL. The switch SW5 has a control terminal connected to the second operation mode switching line MSL2, one conduction terminal connected to the other conduction terminal of each of the switches SW15, SW16, SW25, and SW26, and the other conduction terminal connected to the pixel electrode PIX. It is connected. The switch SW6 has a control terminal connected to the first operation mode switching line MSL1, one conduction terminal connected to the other conduction terminal of each of the switches SW15, SW16, SW25, and SW26, and the other conduction terminal connected to the pixel electrode PIX. It is connected. A liquid crystal capacitor Clc is formed between the pixel electrode PIX and the counter electrode COM, and a holding capacitor Ch (also referred to as an auxiliary capacitor) is added in parallel to the liquid crystal capacitor Clc as necessary.

(Driving method)
In the present embodiment, as described above, moving image (gradation) display is performed in the normal operation mode, and the first still image, the second still image, and the third still image are switched at a desired timing in the memory operation mode. Displayed. The operation mode switching and the first still image, the second still image, and the third still image are switched from the outside to the display control circuit 200 by the operation mode switching signals VMSL1, VMSL2, and the image data selection signal VSEL. Based on. The driving method in the normal operation mode is the same as the driving method of the fifth embodiment shown in FIG. 22, and three images (first still image, second still image, and third still image) are displayed in the memory operation mode. The method of switching is as shown in FIG. 10 and FIG.

Note that the decoder 5 is not provided in each pixel P as shown in FIG. 12, and one decoder 5 may be provided in the memory driving driver 600.

[Embodiment 7]
In the liquid crystal display device 10 according to the present embodiment, in addition to the function for performing still image display (memory operation mode) described in the third embodiment, the function for performing normal moving image (gradation) display (normal operation mode) And has a configuration for performing display by switching between the normal operation mode and the memory operation mode.

The display unit 500 includes a source bus line (data signal line) SL, a first gate bus line (first scanning signal line) GL1, a second gate bus line (second scanning signal line) GL2, an image data selection line SEL, A high potential side power supply line VHL, a low potential side power supply line VLL, a first operation mode switching line MSL1, and a second operation mode switching line MSL2 are included. The source bus line SL is connected to the source driver 300, the first gate bus line GL1 and the second gate bus line GL2 are connected to the gate driver 400, the image data selection line SEL, the high potential side power supply line VHL, the low potential The side power supply line VLL, the first operation mode switching line MSL1, and the second operation mode switching line MSL2 are connected to the memory driving driver 600.

The display unit 500 includes a plurality of pixels P, and corresponding to each pixel P, there are two gate bus lines (first gate bus line GL1, second gate bus line GL2) and one source bus line SL. An image data selection line SEL, a high potential side power supply line VHL, a low potential side power supply line VLL, a first operation mode switching line MSL1, and a second operation mode switching line MSL2 are provided. Each pixel P includes a pixel electrode PIX, a common electrode COM, and a liquid crystal layer. If necessary, a storage capacitor (also referred to as an auxiliary capacitor) is provided in parallel with a liquid crystal capacitor Clc formed by the pixel electrode PIX and the common electrode COM. Is added). In addition, a storage unit is provided for each pixel P, and the storage unit is provided with two memory circuits (first memory circuit and second memory circuit) each as a storage circuit capable of holding 1-bit data. Yes.

The display control circuit 200 receives a data signal DAT, an image data selection signal VSEL, and an operation mode switching signal VMSL sent from the outside, and controls a digital video signal DV (image data) and an image display on the display unit 500. To select the start pulse signal SSP, the source clock signal SCK, the latch strobe signal LS, the gate start pulse signal GSP, and the gate clock signal GCK and an image (first still image and second still image) to be displayed on the display unit 500. The first image data selection signal VSEL1 and the second image data selection signal VSEL2 and an operation mode switching signal VMSL for switching between the normal operation mode and the memory operation mode are output.

The source driver 300 receives the digital video signal DV, the source start pulse signal SSP, the source clock signal SCK, and the latch strobe signal LS output from the display control circuit 200, and drives the video signal (image) for each source bus line SL. Data). Each source bus line SL is supplied with moving image data (moving image data) in the normal operation mode, and in the memory operation mode, the first still image data for the still image and the second still image for the still image. Data is supplied alternately.

When the gate driver 400 writes image data (moving image data, first still image data, and second still image data), the gate driver 400 sequentially selects each gate bus line GL by one horizontal scanning period. Based on the gate start pulse signal GSP output from the gate 200 and the gate clock signal GCK, an active scanning signal is sequentially applied to each gate bus line GL. Specifically, in the normal operation mode, display is performed based on moving image data by sequentially selecting the first gate bus line GL1 of each pixel. Further, in the image data writing period in the memory operation mode, first, in each pixel, the second gate bus line GL2 is selected, whereby the second image data is written into the second pixel memory MR2, and then the first gate bus line. When GL1 is selected, the first image data is written in the first pixel memory MR1. In the image data holding period in the memory operation mode, the gate driver 400 stops the application of the active scanning signal to each gate bus line GL and deactivates all the gate bus lines GL.

(Pixel circuit configuration)
FIG. 26 is a schematic diagram showing the configuration of the pixels of the liquid crystal display panel 100, and shows two pixels P in each of the (n−1) row, the n row, and the (n + 1) row. FIG. 27 is an equivalent circuit diagram showing the configuration of one pixel P. The pixel P includes a switch unit 50, a storage unit 51, a data selection unit 52, a display element unit 53, and a display mode switching unit 54.

The switch unit 50, the storage unit 51, and the data selection unit 52 have the same configuration as the pixel P in FIG. The connection relationship between the display element unit 53 and the display mode switching unit 54 is the same as that of the pixel P in FIG.

(Driving method)
Next, the driving method in the present embodiment will be described with reference to FIGS. FIG. 28 is a timing chart showing a driving method (normally black mode) of the liquid crystal display device 10 of FIG. VSL indicates gradation data and first still image data supplied to the source bus line SL, and VGL2 (n−1), VGL2n, and VGL2 (n + 1) are respectively in the (n−1) th row. , The second gate signal (second scanning signal) supplied to the second gate bus lines GL2 (n−1), GL2n, GL2 (n + 1) in the nth row and the (n + 1) th row, and VGL1 (n− 1), VGL1n and VGL1 (n + 1) are supplied to the first gate bus lines GL1 (n−1), GL1n and GL1 (n + 1) in the (n−1) th row, the nth row and the (n + 1) th row, respectively. VMSL1 indicates a first operation mode switching signal supplied to the first operation mode switching line MSL1, and VMSL2 is supplied to the second operation mode switching line MSL2. VSEL indicates an image data selection signal supplied to the image data selection line SEL, and VMR1 (n−1), VMR1n, and VMR1 (n + 1) are (n−1) rows, respectively. The potentials of the first pixel memory MR1 in the 1st, nth and (n + 1) th rows are shown, and VMR2 (n−1), VMR2n and VMR2 (n + 1) are respectively the (n−1) th, nth, The potential of the second pixel memory MR2 in the (n + 1) th row is shown, and VP (n−1), VPn, and VP (n + 1) are the (n−1) th row, the nth row, and the (n + 1) th row, respectively. The potential of the pixel electrode PIX (pixel potential) is shown.

In the present embodiment, as described above, moving image (gradation) display is performed in the normal operation mode, and the first still image and the second still image are switched and displayed at a desired timing in the memory operation mode. . The switching of the operation mode and the switching between the first still image and the second still image are performed based on the operation mode switching signals VMSL1, VMSL2, and the image data selection signal VSEL sent from the outside to the display control circuit 200. Is called. Hereinafter, the driving method in the normal operation mode, the driving method in the image data writing period and the driving method in the image data holding period in the memory operation mode will be described in order. In FIG. 28, in the memory operation mode, the first still image displayed by the first still image data is a white solid image, and the second still image displayed by the second still image data is a black solid image. The case is shown.

(Driving method in normal operation mode)
In FIG. 28, a normal gradation display operation is performed from time t0 to time t1. An active signal is supplied to each gate bus line GL1 (n−1), GL1n, GL1 (n + 1) in order for a predetermined period. That is, in the normal operation mode, one (first gate bus line) of the two gate bus lines GL provided in each pixel P is selected in order. A high (H) level or low (L) level image data selection signal VSEL is supplied to the image data selection line SEL. Here, it is assumed that an H level image data selection signal VSEL is supplied.

Here, paying attention to the pixel Pn in the n-th row, when an active signal (H level) is applied to the gate bus line GL1n provided corresponding to the pixel Pn, the switches SW11 and SW21 are turned on. . At the same time, an H level signal is input to the inverter circuit INV11, and an output signal of the inverted level (L level) is applied to the switch SW12, so that the switch SW12 is also turned on.

Thus, the gradation data (image data corresponding to white) supplied to the source bus line SL is applied to the pixel electrode PIX via the switches SW11, SW12, SW3, and SW4, and the white gradation is generated in the pixel Pn. Is displayed ("VPn" in FIG. 28).

(Memory operation mode; image data writing period driving method)
In FIG. 28, at time t1, the first operation mode switching signal VMSL1 at L level is supplied to the first operation mode switching line MSL1, and the second operation mode switching signal VMSL2 at H level is supplied to the second operation mode switching line MSL2. Supplied. As a result, the switches SW1, SW2, SW5, and SW6 are turned on, and the switches SW3 and SW4 are turned off. The gate bus lines GL2 (n−1), GL1 (n−1), GL2n, GL1n, GL2 (n + 1), and GL1 (n + 1) are sequentially supplied with active signals for a predetermined period. The subsequent operation is the same as the operation shown in FIG. 15, and white is displayed in the pixel Pn (“VPn” in FIG. 28). The same operation is performed on the pixels adjacent to the pixel Pn, and a white solid image is displayed.

(Memory operation mode; image data retention period driving method)
The image data holding period is the same as that shown in FIG. Thus, the display is performed from the time t2 to the time t3 by the first image data (white) stored in the first pixel memory MR1 (“VPn” in FIG. 28), and after the time t3, the second pixel memory MR2 is displayed. Display is performed using the stored second image data (black) (“VPn” in FIG. 28). In other words, in the image data holding period, display is performed using still image data held in the storage unit 51, and the first still image data held in the first pixel memory MR1 is supported based on the image data selection signal VSEL. The first still image and the second still image corresponding to the second still image data held in the second pixel memory MR2 can be switched and displayed.

[Embodiment 8]
In the liquid crystal display device 10 according to the present embodiment, in addition to the function for performing still image display (memory operation mode) described in the fourth embodiment, the function for performing normal moving image (gradation) display (normal operation mode) And has a configuration for performing display by switching between the normal operation mode and the memory operation mode.

The display unit 500 includes a source bus line (data signal line) SL, a first gate bus line (first scanning signal line) GL1, a second gate bus line (second scanning signal line) GL2, and a third gate bus line ( (Third scanning signal line) GL3, first image data selection line SEL1, second image data selection line SEL2, high potential side power supply line VHL, low potential side power supply line VLL, first operation mode switching line MSL1, and second An operation mode switching line MSL2 is included. The source bus line SL is connected to the source driver 300, and the first gate bus line GL1, the second gate bus line GL2, and the third gate bus line GL3 are connected to the gate driver 400, and the first image data selection line SEL1. The second image data selection line SEL2, the high potential side power supply line VHL, the low potential side power supply line VLL, the first operation mode switching line MSL1, and the second operation mode switching line MSL2 are connected to the memory driving driver 600. Yes.

The display unit 500 includes a plurality of pixels P, and corresponding to each pixel P, three gate bus lines (first gate bus line GL1, second gate bus line GL2, third gate bus line GL3) and 1 Source bus lines, two image data selection lines (first image data selection line SEL1, second image data selection line SEL2), high-potential-side power supply line VHL, low-potential-side power supply line VLL, A first operation mode switching line MSL1 and a second operation mode switching line MSL2 are provided. Each pixel P includes a pixel electrode PIX, a common electrode COM, and a liquid crystal layer. If necessary, a storage capacitor (also referred to as an auxiliary capacitor) is provided in parallel with a liquid crystal capacitor Clc formed by the pixel electrode PIX and the common electrode COM. Is added). In addition, a storage unit is provided for each pixel P, and the storage unit includes three memory circuits as a storage circuit capable of holding 1-bit data (first memory circuit, second memory circuit, third memory). Circuit).

The source driver 300 receives the digital video signal DV, the source start pulse signal SSP, the source clock signal SCK, and the latch strobe signal LS output from the display control circuit 200, and drives the video signal (image) for each source bus line SL. Data). Each source bus line SL is supplied with moving image data (moving image data) in the normal operation mode, and in the memory operation mode, still image first still image data, second still image data, and Third still image data is sequentially supplied.

When writing image data (moving image data, first still image data, second still image data, and third still image data), the gate driver 400 sequentially selects each gate bus line GL by one horizontal scanning period. Therefore, based on the gate start pulse signal GSP and the gate clock signal GCK output from the display control circuit 200, an active scanning signal is sequentially applied to each gate bus line GL. Specifically, in the normal operation mode, display is performed based on moving image data by sequentially selecting the first gate bus line GL1 of each pixel. Further, in the image data writing period in the memory operation mode, first, in each pixel, the third gate bus line GL3 is selected, so that the third image data is written in the third pixel memory MR3, and then the second gate bus line. The second image data is written in the second pixel memory MR2 by selecting GL2, and the first image data is written in the first pixel memory MR1 by selecting the first gate bus line GL1. In the image data holding period in the memory operation mode, the gate driver 400 stops the application of the active scanning signal to each gate bus line GL and deactivates all the gate bus lines GL.

(Pixel circuit configuration)
FIG. 29 is a schematic diagram showing the configuration of the pixels of the liquid crystal display panel 100, and shows two pixels P in each of the (n-1), n, and (n + 1) rows. FIG. 30 is an equivalent circuit diagram illustrating a configuration of one pixel P. The pixel P includes a switch unit 50, a storage unit 51, a data selection unit 52, a display element unit 53, and a display mode switching unit 54.

(Driving method)
In the present embodiment, as described above, moving image (gradation) display is performed in the normal operation mode, and the first still image, the second still image, and the third still image are switched at a desired timing in the memory operation mode. Displayed. The operation mode switching and the first still image, the second still image, and the third still image are switched from the outside to the display control circuit 200 by the operation mode switching signals VMSL1, VMSL2, and the image data selection signal VSEL. Based on. The driving method in the normal operation mode is the same as that in the seventh embodiment shown in FIG. 28, and three images (first still image, second still image, and third still image) are displayed in the memory operation mode. The method of switching is as shown in FIG. 10 and FIG.

Note that, as shown in FIG. 18, the decoder 5 is not provided in each pixel P, and one decoder 5 may be provided in the memory driving driver 600.

(Modification)
FIG. 31 is an equivalent circuit diagram showing a modification of the pixel P in FIG. In the pixel P of FIG. 31, the switches SW12, SW22, SW32, SW2, SW3, SW6, the inverter circuits INV11, INV21, INV31, and the first operation mode switching line MSL1 in the pixel P of FIG. 30 are schematically omitted. ing.

According to this configuration, when the L-level second operation mode switching signal VMSL2 is supplied to the second operation mode switching line MSL2 (normal operation mode), the switches SW1 and SW5 are turned off and the switch SW4 is turned on. Become. As a result, the gradation data (image data corresponding to white) supplied to the source bus line SL is applied to the pixel electrode PIX via the switches SW11 and SW4, and the white gradation is displayed in the pixel Pn.

Further, when the H-level second operation mode switching signal VMSL2 is supplied to the second operation mode switching line MSL2, the switches SW1 and SW5 are turned on, the switch SW4 is turned off, and the memory operation mode is entered. Subsequent operations are as described in the above driving method.

In the liquid crystal display device,
Each pixel further includes an image data selection unit for selecting an image to be displayed,
The image data selection unit selects image data held in a corresponding memory circuit based on a selection signal input from the outside,
A configuration may be adopted in which display is performed based on the selected image data.

In the liquid crystal display device,
In each pixel, the storage unit includes first and second memory circuits,
One scanning signal line and first and second data signal lines are provided corresponding to one pixel,
First image data is supplied to the first memory circuit via the first data signal line, and second image data is supplied to the second memory circuit via the second data signal line,
The first image data and the second image data may be switched and displayed.

In the liquid crystal display device,
In each pixel, the storage unit includes first, second, and third memory circuits,
One scanning signal line and first, second, and third data signal lines are provided corresponding to one pixel,
First image data is supplied to the first memory circuit via the first data signal line, and second image data is supplied to the second memory circuit via the second data signal line, Third image data is supplied to the third memory circuit via the third data signal line,
The first, second and third image data may be switched and displayed.

In the liquid crystal display device,
In each pixel, the storage unit includes first and second memory circuits,
Corresponding to one pixel, first and second scanning signal lines and a data signal line are provided,
The first memory circuit is provided at an intersection of the first scanning signal line and the data signal line, and the first image data is supplied through the data signal line,
The second memory circuit is provided at an intersection of the second scanning signal line and the data signal line, and second image data is supplied through the data signal line.
The first image data and the second image data may be switched and displayed.

In the liquid crystal display device,
In each pixel, the storage unit includes first, second, and third memory circuits,
Corresponding to one pixel, first, second and third scanning signal lines and a data signal line are provided,
The first memory circuit is provided at an intersection of the first scanning signal line and the data signal line, and the first image data is supplied through the data signal line,
The second memory circuit is provided at an intersection of the second scanning signal line and the data signal line, and second image data is supplied through the data signal line.
The third memory circuit is provided at an intersection of the third scanning signal line and the data signal line, and third image data is supplied through the data signal line.
The first, second and third image data may be switched and displayed.

In the liquid crystal display device,
A normal operation mode in which display is performed based on image data supplied via the data signal line and a memory operation mode in which display is performed based on the image data held in the storage unit may be included.

According to the above configuration, moving image display (gradation display) can be performed in the normal operation mode, and a plurality of still images can be switched and displayed in the memory operation mode while reducing power consumption. .

In the liquid crystal display device,
In the normal operation mode, image data may not be supplied to each memory circuit of the storage unit.

According to the above configuration, in the normal operation mode, image data is not supplied to each memory circuit of the storage unit, so that power consumption can be further reduced.

In the liquid crystal display device,
A normal operation mode for performing display based on image data supplied via a data signal line, and a memory operation mode for performing display based on image data held in the storage unit,
In the normal operation mode, when the scanning signal line becomes active, the first data signal line and the pixel electrode are electrically connected to supply image data from the first data signal line to the pixel electrode, Display based on the image data,
In the memory operation mode, the first image data is supplied from the first data signal line to the first memory circuit while the scanning signal line is active, and the second data signal line supplies the second image signal. Configuration in which display is performed based on the first and second image data held in the first and second memory circuits when the second image data is supplied to the memory circuit and the scanning signal line becomes inactive. It can also be.

In the liquid crystal display device,
A normal operation mode for performing display based on image data supplied via a data signal line, and a memory operation mode for performing display based on image data held in the storage unit,
In the normal operation mode, when the scanning signal line becomes active, the first data signal line and the pixel electrode are electrically connected to supply image data from the first data signal line to the pixel electrode, Display based on the image data,
In the memory operation mode, the first image data is supplied from the first data signal line to the first memory circuit while the scanning signal line is active, and the second data signal line supplies the second image signal. When the second image data is supplied to the memory circuit, the third image data is supplied from the third data signal line to the third memory circuit, and the scanning signal line becomes inactive, the first to A configuration may be adopted in which display is performed based on the first to third image data held in each of the third memory circuits.

In the liquid crystal display device,
A normal operation mode for performing display based on image data supplied via a data signal line, and a memory operation mode for performing display based on image data held in the storage unit,
In the normal operation mode, when the first scanning signal line becomes active, the data signal line and the pixel electrode are electrically connected to supply image data from the data signal line to the pixel electrode. Display based on the data,
In the memory operation mode, the first image data is supplied from the data signal line to the first memory circuit while the first scanning signal line is active, and the second scanning signal line is active during the active period. When the second image data is supplied from the data signal line to the second memory circuit and the first and second scanning signal lines become inactive, the first and second memory circuits respectively hold the second image data. A configuration may be adopted in which display is performed based on the first and second image data.

In the liquid crystal display device,
A normal operation mode for performing display based on image data supplied via a data signal line, and a memory operation mode for performing display based on image data held in the storage unit,
In the normal operation mode, when the first scanning signal line becomes active, the data signal line and the pixel electrode are electrically connected to supply image data from the data signal line to the pixel electrode. Display based on the data,
In the memory operation mode, the first image data is supplied from the data signal line to the first memory circuit while the first scanning signal line is active, and the second scanning signal line is active during the active period. The second image data is supplied from the data signal line to the second memory circuit, and the third image data is supplied from the data signal line to the third memory circuit while the third scanning signal line is active. In addition, when the first to third scanning signal lines become inactive, display can be performed based on the first to third image data held in the first to third memory circuits. .

The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and can be obtained by appropriately combining technical means disclosed in different embodiments. Embodiments are also included in the technical scope of the present invention.

The present invention can be suitably used for a mobile phone display or the like.

DESCRIPTION OF SYMBOLS 10 Liquid crystal display device 100 Liquid crystal display panel 200 Display control circuit 300 Source driver (data signal line drive circuit)
400 Gate driver (scanning signal line drive circuit)
500 Display unit 600 Memory drive driver 5 Decoder 50 Switch unit 51 Storage unit 52 Data selection unit 53 Display element unit 54 Display mode switching unit P Pixel PIX Pixel electrode COM Counter electrode (common electrode)
GL gate line (scanning signal line)
SL source line (data signal line)
SEL Image data selection line VHL High potential power line VLL Low potential power line SW Switch (transistor, TFT)
INV inverter circuit

Claims

A liquid crystal display device provided with a storage unit for holding image data in each pixel,
In each pixel, the storage unit includes a plurality of memory circuits each holding individual image data,
A liquid crystal display device that performs display based on image data held in each memory circuit.
Each pixel further includes an image data selection unit for selecting an image to be displayed,
The image data selection unit selects image data held in a corresponding memory circuit based on a selection signal input from the outside,
The liquid crystal display device according to claim 1, wherein display is performed based on the selected image data.
In each pixel, the storage unit includes first and second memory circuits,
One scanning signal line and first and second data signal lines are provided corresponding to one pixel,
First image data is supplied to the first memory circuit via the first data signal line, and second image data is supplied to the second memory circuit via the second data signal line,
2. The liquid crystal display device according to claim 1, wherein the first image data and the second image data are switched and displayed.
In each pixel, the storage unit includes first, second, and third memory circuits,
One scanning signal line and first, second, and third data signal lines are provided corresponding to one pixel,
First image data is supplied to the first memory circuit via the first data signal line, and second image data is supplied to the second memory circuit via the second data signal line, Third image data is supplied to the third memory circuit via the third data signal line,
The liquid crystal display device according to claim 1, wherein the first, second, and third image data are displayed while being switched to each other.
In each pixel, the storage unit includes first and second memory circuits,
Corresponding to one pixel, first and second scanning signal lines and a data signal line are provided,
The first memory circuit is provided at an intersection of the first scanning signal line and the data signal line, and the first image data is supplied through the data signal line,
The second memory circuit is provided at an intersection of the second scanning signal line and the data signal line, and second image data is supplied through the data signal line.
2. The liquid crystal display device according to claim 1, wherein the first image data and the second image data are switched and displayed.
In each pixel, the storage unit includes first, second, and third memory circuits,
Corresponding to one pixel, first, second and third scanning signal lines and a data signal line are provided,
The first memory circuit is provided at an intersection of the first scanning signal line and the data signal line, and the first image data is supplied through the data signal line,
The second memory circuit is provided at an intersection of the second scanning signal line and the data signal line, and second image data is supplied through the data signal line.
The third memory circuit is provided at an intersection of the third scanning signal line and the data signal line, and third image data is supplied through the data signal line.
The liquid crystal display device according to claim 1, wherein the first, second, and third image data are displayed while being switched to each other.
A normal operation mode in which display is performed based on image data supplied via a data signal line, and a memory operation mode in which display is performed based on image data held in the storage unit. 3. The liquid crystal display device according to 1 or 2.
The liquid crystal display device according to claim 7, wherein no image data is supplied to each memory circuit of the storage unit in the normal operation mode.
A normal operation mode for performing display based on image data supplied via a data signal line, and a memory operation mode for performing display based on image data held in the storage unit,
In the normal operation mode, when the scanning signal line becomes active, the first data signal line and the pixel electrode are electrically connected to supply image data from the first data signal line to the pixel electrode, Display based on the image data,
In the memory operation mode, the first image data is supplied from the first data signal line to the first memory circuit while the scanning signal line is active, and the second data signal line supplies the second image signal. When the second image data is supplied to the memory circuit and the scanning signal line becomes inactive, display is performed based on the first and second image data held in the first and second memory circuits, respectively. The liquid crystal display device according to claim 3.
A normal operation mode for performing display based on image data supplied via a data signal line, and a memory operation mode for performing display based on image data held in the storage unit,
In the normal operation mode, when the scanning signal line becomes active, the first data signal line and the pixel electrode are electrically connected to supply image data from the first data signal line to the pixel electrode, Display based on the image data,
In the memory operation mode, the first image data is supplied from the first data signal line to the first memory circuit while the scanning signal line is active, and the second data signal line supplies the second image signal. When the second image data is supplied to the memory circuit and the third image data is supplied from the third data signal line to the third memory circuit, and the scanning signal line becomes inactive, the first, 5. The liquid crystal display device according to claim 4, wherein display is performed based on the first, second, and third image data held in the second and third memory circuits, respectively.
A normal operation mode for performing display based on image data supplied via a data signal line, and a memory operation mode for performing display based on image data held in the storage unit,
In the normal operation mode, when the first scanning signal line becomes active, the data signal line and the pixel electrode are electrically connected to supply image data from the data signal line to the pixel electrode. Display based on the data,
In the memory operation mode, the first image data is supplied from the data signal line to the first memory circuit while the first scanning signal line is active, and the second scanning signal line is active during the active period. When the second image data is supplied from the data signal line to the second memory circuit and the first and second scanning signal lines become inactive, the first and second memory circuits respectively hold the second image data. 6. The liquid crystal display device according to claim 5, wherein display is performed based on the first and second image data.
A normal operation mode for performing display based on image data supplied via a data signal line, and a memory operation mode for performing display based on image data held in the storage unit,
In the normal operation mode, when the first scanning signal line becomes active, the data signal line and the pixel electrode are electrically connected to supply image data from the data signal line to the pixel electrode. Display based on the data,
In the memory operation mode, the first image data is supplied from the data signal line to the first memory circuit while the first scanning signal line is active, and the second scanning signal line is active during the active period. The second image data is supplied from the data signal line to the second memory circuit, and the third image data is supplied from the data signal line to the third memory circuit while the third scanning signal line is active. When the first, second, and third scanning signal lines become inactive, based on the first, second, and third image data held in the first, second, and third memory circuits, respectively. The liquid crystal display device according to claim 6, wherein display is performed.