JP2021092810A - Display - Google Patents

Abstract

To make it possible to change an image in short time.SOLUTION: A display comprises: a plurality of sub-pixels each including a first memory and a second memory that store sub-pixel data, a first memory switch that is provided between the first memory and a pixel electrode, and a second memory switch that is provided between the second memory and the pixel electrode; a first memory selection line that is connected with the first memory switches of the sub-pixels, and a second memory selection line that is connected with the second memory switches; and a memory selection circuit that is connected with the first memory selection line and the second memory selection line and supplies a memory selection signal to any one of the memory selection lines. The plurality of sub-pixels displays an image on the basis of the sub-pixel data stored in one of the first memory and the second memory in accordance with the memory selection line supplied with the memory selection signal. A length of a period during which the memory selection circuit supplies the memory selection signal to the first memory selection line is the same as a length of a period during which the memory selection circuit supplies the memory selection signal to the second memory selection line.SELECTED DRAWING: Figure 9

Description

The present invention relates to a display device.

A display device for displaying an image includes a plurality of pixels. The following Patent Document 1 describes a so-called MIP (Memory In Pixel) type display device in which each of a plurality of pixels includes a memory. In the display device described in Patent Document 1, each of the plurality of pixels includes a plurality of memories and a switching circuit for these memories.

Japanese Unexamined Patent Publication No. 9-212140

In the display device described in Patent Document 1, the memory of each pixel is switched by line sequential scanning in which the switching circuit is operated by a scanning signal. Therefore, in the display device described in Patent Document 1, one frame time is required to switch the memories of all the pixels. That is, in the display device described in Patent Document 1, one frame time is required to change the image (frame).

An object of the present invention is to provide a display device capable of changing an image in a short time.

The display device of one aspect of the present invention is provided between the pixel electrode, the first memory and the second memory for storing the sub-pixel data for controlling the display by the pixel electrode, and the first memory and the pixel electrode. A plurality of sub-pixels each including a first memory switch and a second memory switch provided between the second memory and the pixel electrode, and a first memory selection connected to the first memory switch of each sub-pixel. A memory selection line connected to a line, a second memory selection line connected to a second memory switch, a first memory selection line, and a second memory selection line to supply a memory selection signal to one of the memory selection lines. It is equipped with a circuit. The plurality of sub-pixels display an image based on the sub-pixel data stored in either the first memory or the second memory according to the memory selection line to which the memory selection signal is supplied from the memory selection circuit. The length of the period for supplying the memory selection signal to the first memory selection line by the memory selection circuit is the same as the length of the period for supplying the memory selection signal to the second memory selection line.

FIG. 1 is a diagram showing an outline of the overall configuration of the display device of the embodiment. FIG. 2 is a cross-sectional view of the display device of the embodiment. FIG. 3 is a diagram showing the arrangement of sub-pixels within the pixels of the display device of the embodiment. FIG. 4 is a diagram showing a circuit configuration of the display device of the embodiment. FIG. 5 is a diagram showing a circuit configuration of sub-pixels of the display device of the embodiment. FIG. 6 is a diagram showing a circuit configuration of a memory of sub-pixels of the display device of the embodiment. FIG. 7 is a diagram showing a circuit configuration of an inverting switch for sub-pixels of the display device of the embodiment. FIG. 8 is a diagram showing an outline of the layout of sub-pixels of the display device of the embodiment. FIG. 9 is a timing diagram showing the operation timing of the display device of the embodiment. FIG. 10 is a diagram showing an application example of the display device of the embodiment.

An embodiment (embodiment) for carrying out the present invention will be described in detail with reference to the drawings. The present invention is not limited to the contents described in the following embodiments. In addition, the components described below include those that can be easily assumed by those skilled in the art and those that are substantially the same. Furthermore, the components described below can be combined as appropriate. It should be noted that the disclosure is merely an example, and those skilled in the art can easily conceive of appropriate changes while maintaining the gist of the invention are naturally included in the scope of the present invention. Further, in order to clarify the explanation, the drawings may schematically represent the width, thickness, shape, etc. of each part as compared with the actual embodiment, but this is just an example, and the interpretation of the present invention is used. It is not limited. Further, in the present specification and each figure, the same elements as those described above with respect to the above-mentioned figures may be designated by the same reference numerals, and detailed description thereof may be omitted as appropriate.

(Embodiment)
[overall structure]
FIG. 1 is a diagram showing an outline of the overall configuration of the display device of the embodiment. The display device 1 includes a first panel 2 and a second panel 3 arranged to face the first panel 2. The display device 1 has a display area DA for displaying an image and a frame area GD outside the display area DA. In the display area DA, a liquid crystal layer is enclosed between the first panel 2 and the second panel 3.

In the embodiment, the display device 1 is a liquid crystal display device using a liquid crystal layer, but the present disclosure is not limited to this. The display device 1 may be an organic EL display device that uses an organic EL (Electro-Luminescence) element instead of the liquid crystal layer.

In the display area DA, a plurality of pixel Pix are arranged in N rows (N is a natural number) in the X direction parallel to the main surfaces of the first panel 2 and the second panel 3, and the first panel 2 and the second panel 3 are arranged. They are arranged in a matrix of M rows (M is a natural number) in the Y direction parallel to the main surface and intersecting the X direction. In the frame area GD, the interface circuit 4, the source line drive circuit 5, the common electrode drive circuit 6, the inverting drive circuit 7, the memory selection circuit 8, the gate line drive circuit 9, and the gate line selection circuit 10 And are arranged. Among these plurality of circuits, the interface circuit 4, the source line drive circuit 5, the common electrode drive circuit 6, the inverting drive circuit 7, and the memory selection circuit 8 are incorporated in the IC chip, and the gate line drive circuit 9 is incorporated. It is also possible to adopt a configuration in which the gate line selection circuit 10 is formed on the first panel. Alternatively, it is also possible to adopt a configuration in which a group of circuits incorporated in the IC chip is formed in a processor outside the display device and the circuits are connected to the display device.

Each of the M × N pixel Pix includes a plurality of sub-pixel SPix. In the embodiment, the plurality of sub-pixel SPix is R (red), G (green), and B (blue), but the present disclosure is not limited to this. The plurality of sub-pixel SPix may be four in which W (white) is added to R (red), G (green) and B (blue). Alternatively, the plurality of sub-pixel SPix may be five or more having different colors.

In the embodiment, since the plurality of sub-pixel SPix is 3, the sub-pixel SPix of M × N × 3 is arranged in the display area DA. Further, in the embodiment, since the three sub-pixel SPix of each of the M × N pixel Pix are arranged in the X direction, N × 3 are arranged in one row of the M × N pixel Pix. This means that the sub-pixel SPix of is arranged.

Each sub-pixel SPix includes a plurality of memories. In the embodiment, the plurality of memories are three from the first memory to the third memory, but the present disclosure is not limited to this. The plurality of memories may be two or four or more.

In the embodiment, since the plurality of memories are three, M × N × 3 × 3 memories are arranged in the display area DA. Further, in the embodiment, since each sub-pixel SPix includes three memories, N × 3 × 3 memories are arranged in one row of the M × N pixel Pix. Become.

Each sub-pixel SPix displays the sub-pixel SPix based on the sub-pixel data stored in one selected memory from the first memory to the third memory included in each sub-pixel SPix. To. That is, the set of M × N × 3 × 3 memories included in the M × N × 3 sub-pixel SPix is equivalent to the three frame memories.

The interface circuit 4 includes a serial-parallel conversion circuit 4a and a timing controller 4b. The timing controller 4b includes a setting register 4c. The command data CMD and the image data ID are serially supplied to the serial-parallel conversion circuit 4a from the external circuit. The external circuit is exemplified by a host CPU (Central Processing Unit) or an application processor, but the present disclosure is not limited thereto.

The serial-parallel conversion circuit 4a converts the supplied command data CMD into parallel and outputs it to the setting register 4c. Values for controlling the source line drive circuit 5, the inverting drive circuit 7, the memory selection circuit 8, the gate line drive circuit 9, and the gate line selection circuit 10 are set in the setting register 4c based on the command data CMD.

The serial-parallel conversion circuit 4a converts the supplied image data ID into parallel and outputs it to the timing controller 4b. The timing controller 4b outputs the image data ID to the source line drive circuit 5 based on the value set in the setting register 4c. Further, the timing controller 4b controls the inverting drive circuit 7, the memory selection circuit 8, the gate line drive circuit 9, and the gate line selection circuit 10 based on the values set in the setting register 4c.

The reference clock signal CLK is supplied from the external circuit to the common electrode drive circuit 6, the inverting drive circuit 7, and the memory selection circuit 8. The external circuit is exemplified by a clock generator, but the present disclosure is not limited to this.

Drive methods such as common inversion, column inversion, line inversion, dot inversion, and frame inversion are known as drive methods for suppressing screen burn-in of a liquid crystal display device.

The display device 1 can adopt any of the above-mentioned drive methods. In the embodiment, the display device 1 adopts a common reversal drive system. Since the display device 1 adopts the common inversion drive method, the common electrode drive circuit 6 inverts the potential of the common electrode (common potential) in synchronization with the reference clock signal CLK. Under the control of the timing controller 4b, the inverting drive circuit 7 inverts the potential of the sub-pixel electrode in synchronization with the reference clock signal CLK. As a result, the display device 1 can realize the common reversal drive system. In the embodiment, the display device 1 is a so-called normally black liquid crystal display device that displays black when a voltage is not applied to the liquid crystal and displays white when a voltage is applied to the liquid crystal. In the normally black liquid crystal display device, black is displayed when the potential of the sub-pixel electrode and the common potential are in phase, and white is displayed when the potential of the sub-pixel electrode and the common potential are out of phase. ..

The reference clock signal CLK corresponds to the reference signal of the present invention.

In order to display an image on the display device, it is necessary to store the sub-pixel data in the first memory to the third memory of each sub-pixel SPix. In order to store the sub-pixel data in each memory, the gate line drive circuit 9 outputs a gate signal for selecting one row among the M × N pixel Pix under the control of the timing controller 4b. ..

In a MIP type liquid crystal display device in which each sub-pixel has one memory, one gate line is arranged for each row (pixel row (sub-pixel row)). However, in the embodiment, each sub-pixel SPix includes three memories from the first memory to the third memory. Therefore, in the embodiment, three gate lines are arranged per row. The three gate lines are electrically connected to the first memory to the third memory of each of the sub-pixel SPix included in one row. When the sub-pixel SPix operates with an inverted gate signal in which the gate signal is inverted in addition to the gate signal, six gate lines are arranged per row.

Three or six gate lines arranged per row correspond to the gate line group of the present invention. In the embodiment, since the display device 1 has M rows of pixels Pix, the gate line group of the M group is arranged.

The gate line drive circuit 9 has M output terminals corresponding to the pixel Pix in the M row. Under the control of the timing controller 4b, the gate line drive circuit 9 sequentially outputs gate signals for selecting one of the M rows from the M output terminals.

The gate line selection circuit 10 selects one of the three gate lines arranged in one row under the control of the timing controller 4b. As a result, the gate signal output from the gate line drive circuit 9 is supplied to a selected one of the three gate lines arranged in one line.

The source line drive circuit 5 outputs sub-pixel data to the memory selected by the gate signal under the control of the timing controller 4b, respectively. As a result, the sub-pixel data is sequentially stored in the first memory to the third memory of each sub-pixel.

The display device 1 linearly scans the pixel Pix in the M row to convert the sub-pixel data of one frame data into the first memory of each sub-pixel SPix. Then, the display device 1 executes the line sequential scanning three times, so that three frame data are stored in the first memory to the third memory of each sub-pixel SPix.
At this time, the display device 1 can also adopt a procedure of writing to the first memory, writing to the second memory, and writing to the third memory for each scan of one line. By performing such scanning from the first column to the Mth column, the sub-pixel data can be stored in the first memory to the third memory of each sub-pixel SPix by one line sequential scanning.

In the embodiment, three memory selection lines are arranged per line. The three memory selection lines are electrically connected to the first memory to the third memory of each of the N × 3 sub-pixel SPix included in one line. When the sub-pixel SPix operates with an inverted memory selection signal in which the memory selection signal is inverted in addition to the memory selection signal, six memory selection lines are arranged per line.

Three or six memory selection lines arranged per line correspond to the memory selection line group of the present invention. In the embodiment, since the display device 1 has M rows of pixels Pix, the memory selection line group of the M group is arranged.

Under the control of the timing controller 4b, the memory selection circuit 8 simultaneously selects one of the first memory to the third memory of each sub-pixel SPix in synchronization with the reference clock signal CLK. More specifically, the first memory of all sub-pixel SPix is selected at the same time. Alternatively, the second memory of all sub-pixel SPix is selected at the same time. The third memory of all sub-pixel SPix is selected at the same time. Therefore, the display device 1 can display one of the three images by switching the selection from the first memory to the third memory of each sub-pixel SPix. As a result, the display device 1 can change the images all at once, and can change the images in a short time. Further, the display device 1 can perform animation display (moving image display) by sequentially switching the selection from the first memory to the third memory of each sub-pixel SPix.

[Cross-sectional structure]
FIG. 2 is a cross-sectional view of the display device of the embodiment. As shown in FIG. 2, the display device 1 includes a first panel 2, a second panel 3, and a liquid crystal layer 30. The second panel 3 is arranged so as to face the first panel 2. The liquid crystal layer 30 is provided between the first panel 2 and the second panel 3. One main surface of the second panel 3 is a display surface 1a for displaying an image.

The light incident from the outside on the display surface 1a side is reflected by the reflection electrode 15 of the first panel 2 and emitted from the display surface 1a. The display device 1 of the embodiment is a reflective liquid crystal display device that displays an image on the display surface 1a by using the reflected light. In the present specification, the direction parallel to the display surface 1a is defined as the X direction, and the direction intersecting the X direction on the surface parallel to the display surface 1a is defined as the Y direction. Further, the direction perpendicular to the display surface 1a is defined as the Z direction.

The first panel 2 has a first substrate 11, an insulating layer 12, a reflecting electrode 15, and an alignment film 18. The first substrate 11 is exemplified by a glass substrate or a resin substrate. Circuit elements (not shown) and various wirings such as gate lines and data lines are provided on the surface of the first substrate 11. The circuit element includes a switching element such as a TFT (Thin Film Transistor) and a capacitive element.

The insulating layer 12 is provided on the first substrate 11 and flattens the surfaces of circuit elements, various wirings, and the like as a whole. A plurality of reflective electrodes 15 are provided on the insulating layer 12. The alignment film 18 is provided between the reflective electrode 15 and the liquid crystal layer 30. The reflection electrode 15 is provided in a rectangular shape for each sub-pixel SPix. The reflective electrode 15 is made of a metal exemplified by aluminum (Al) or silver (Ag). Further, the reflective electrode 15 may have a configuration in which these metal materials and a translucent conductive material exemplified by ITO (Indium Tin Oxide) are laminated. The reflective electrode 15 is made of a material having good reflectance and functions as a reflector that diffusely reflects light incident from the outside.

Although the light reflected by the reflective electrode 15 is scattered by diffuse reflection, it travels in a uniform direction toward the display surface 1a side. Further, as the voltage level applied to the reflecting electrode 15 changes, the light transmitting state in the liquid crystal layer 30 on the reflecting electrode, that is, the light transmitting state for each sub-pixel changes. That is, the reflective electrode 15 also has a function as a sub-pixel electrode.

The second panel 3 includes a second substrate 21, a color filter 22, a common electrode 23, an alignment film 28, a 1/4 wave plate 24, a 1/2 wave plate 25, and a polarizing plate 26. A color filter 22 and a common electrode 23 are provided on both sides of the second substrate 21 facing the first panel 2 in this order. An alignment film 28 is provided between the common electrode 23 and the liquid crystal layer 30. The 1/4 wave plate 24, the 1/2 wave plate 25, and the polarizing plate 26 are laminated in this order on the surface of the second substrate 21 on the display surface 1a side.

The second substrate 21 is exemplified by a glass substrate or a resin substrate. The common electrode 23 is made of a translucent conductive material exemplified by ITO. The common electrode 23 is arranged to face the plurality of reflecting electrodes 15 and supplies a common potential for each sub-pixel SPix. It is exemplified that the color filter 22 has a filter of three colors of R (red), G (green), and B (blue), but the present disclosure is not limited to this.

It is exemplified that the liquid crystal layer 30 contains a Nematic liquid crystal. In the liquid crystal layer 30, the orientation state of the liquid crystal molecules changes by changing the voltage level between the common electrode 23 and the reflective electrode 15. As a result, the light transmitted through the liquid crystal layer 30 is modulated for each sub-pixel SPix.

External light or the like becomes incident light incident from the display surface 1a side of the display device 1, passes through the second panel 3 and the liquid crystal layer 30, and reaches the reflecting electrode 15. Then, the incident light is reflected by the reflecting electrode 15 of each sub-pixel SPix. The reflected light is modulated for each sub-pixel SPix and emitted from the display surface 1a. As a result, the image is displayed.

[Circuit configuration]
FIG. 3 is a diagram showing the arrangement of sub-pixels within the pixels of the display device of the embodiment. The pixel Pix includes an R (red) sub-pixel SPix _R , a G (green) sub-pixel SPix _G, and a B (blue) sub-pixel SPix _B. The sub-pixels SPix _R , SPix _G, and SPix _B are arranged in the X direction.

The sub-pixel SPix _R includes a memory block 50 and an inverting switch 61. The memory block 50 includes a first memory 51, a second memory 52, and a third memory 53. The inverting switch 61, the first memory 51, the second memory 52, and the third memory 53 are arranged in the Y direction.

Each of the first memory 51, the second memory 52, and the third memory 53 is a memory cell that stores 1-bit data, but the present disclosure is not limited thereto. Each of the first memory 51, the second memory 52, and the third memory 53 may be a memory cell that stores two or more bits of data.

The inverting switch 61 is electrically connected between the first memory 51, the second memory 52, and the third memory 53, and the sub-pixel electrode (reflection electrode) 15 (see FIG. 2). The inverting switch 61 is selected from the first memory 51, the second memory 52, and the third memory 53 based on the display signal supplied from the inverting drive circuit 7 and inverted in synchronization with the reference clock signal CLK. The sub-pixel data output from one memory is inverted at regular intervals and output to the sub-pixel electrode 15.

The period in which the display signal is inverted is the same as the period in which the potential (common potential) of the common electrode 23 is inverted.

The inverting switch 61 corresponds to the switch circuit of the present invention.

FIG. 4 is a diagram showing a circuit configuration of the display device of the embodiment. FIG. 4 shows 2 × 2 sub-pixel SPix in each sub-pixel SPix.

The sub-pixel SPix includes, in addition to the memory block 50 and the inverting switch 61, a liquid crystal LQ, a holding capacity C, and a sub-pixel electrode 15 (see FIG. 2).

The common electrode drive circuit 6 inverts the common potential VCOM common to each sub-pixel SPix in synchronization with the reference clock signal CLK, and outputs the common potential VCOM to the common electrode 23 (see FIG. 2). The common electrode drive circuit 6 may output the reference clock signal CLK to the common electrode 23 as it is as a common potential VCOM, or outputs the reference clock signal CLK to the common electrode 23 as a common potential VCOM via a buffer circuit that amplifies the current drive capability. Is also good.

The gate line drive circuit 9 has M output terminals corresponding to the pixel Pix in the M row. The gate line drive circuit 9 sequentially outputs gate signals for selecting one of the M rows from the M output terminals based on the _{control signal Sigma 4 supplied from the timing controller 4b.}

The gate line drive circuit 9 may be a scanner circuit that sequentially outputs gate signals from M output terminals based on _{the control signal Sigma 4 (scan start signal and clock pulse signal).} Alternatively, the gate line drive circuit 9 may be _{a decoder circuit that decodes the coded control signal Sigma 4} and outputs the gate signal to the output terminal designated by the control signal Sigma _4.

The gate line selection circuit 10, corresponding to the pixel Pix of M rows, including M switches _{SW 4_1, SW 4_2,} a .... M switches _{SW 4_1, SW 4_2,} ··· it is commonly controlled by the control signal Sig ₅ supplied from the timing controller 4b.

On the first panel 2, the gate line groups GL ₁ , GL ₂ , ... Of the M group are arranged corresponding to the pixel Pix of the M row. Each of the gate line groups GL ₁ , GL _{2 , ... Of the M group has a first gate line GCL a} electrically connected to the first memory 51 (see FIG. 3) of the row and a second memory 52. It includes a second gate line GCL _b electrically connected to (see FIG. 3) and a third gate line GCL _c electrically connected to a third memory 53 (see FIG. 3). Each of the gate line groups GL ₁ , GL ₂ , ... Of the M group follows the X direction in the display area DA (see FIG. 1).

M switches _{SW 4_1, SW 4_2,} each ..., when the control signal Sig ₅ of the first value, and an output terminal of the gate line driving circuit 9, a first gate line GCL _a, a Connect electrically. M switches _{SW 4_1, SW 4_2,} each ..., when the control signal Sig ₅ of the second value, the output terminal of the gate line driving circuit 9, and the second gate line GCL _b, the Connect electrically. M switches _{SW 4_1, SW 4_2,} each ..., when the control signal Sig ₅ of the third value, and an output terminal of the gate line driving circuit 9, and a third gate line GCL _c, a Connect electrically.

When the output terminal of the gate line drive circuit 9 and the first gate line GCL _a are electrically connected, a gate signal is supplied to the first memory 51 of each sub-pixel SPix. When the output terminal of the gate line drive circuit 9 and the second gate line GCL _b are electrically connected, a gate signal is supplied to the second memory 52 of each sub-pixel SPix. When the output terminal of the gate line drive circuit 9 and the third gate line GCL _c are electrically connected, a gate signal is supplied to the third memory 53 of each sub-pixel SPix.

_{On the first panel 2, N × 3 source lines SGL 1} , SGL ₂ , ... Are arranged corresponding to N × 3 rows of sub-pixel SPix. Each of the source lines SGL ₁ , SGL ₂ , ... Along the Y direction in the display area DA (see FIG. 1). The source line drive circuit 5 outputs sub-pixel data to each of the three memories of each sub-pixel SPix selected by the gate signal _{via the source lines SGL 1} , SGL _{2, ....}

The sub-pixel SPix in the row to which the gate signal is supplied transmits the sub-pixel data supplied to the source line SGL according to the gate line GCL to which the gate signal is supplied from the first memory 51 to the third memory 53. Store in one of the memories.

The memory selection circuit 8 includes a switch SW ₂ , a latch 71, and a switch SW ₃ . The switch SW ₂ is controlled by the control signal Sig ₂ supplied from the timing controller 4b.

A case of displaying an image, that is, a case of reading image data from any of M × N × 3 first memory 51, second memory 52, and third memory 53 will be described. In this case, the timing controller 4b outputs the control signal Sig ₂ having the first value to the switch SW ₂ . The switch SW ₂ is turned on based on the first value control signal Sig _{2 supplied from the timing controller 4b.} As a result, the reference clock signal CLK is supplied to the latch 71.

When the image is not displayed, that is, the image is displayed from any of the M × N × 3 first memory 51, the M × N × 3 second memory 52, and the M × N × 3 third memory 53. A case where the data is not read will be described. In this case, the timing controller 4b outputs the control signal Sig ₂ having a second value to the switch SW ₂ . The switch SW ₂ is turned off based on _{the control signal Sig 2} having a second value supplied from the timing controller 4b. As a result, the reference clock signal CLK is not supplied to the latch 71.

_{When the reference clock signal CLK is supplied while the switch SW 2} is on, the latch 71 holds the high level of the reference clock signal CLK for one cycle of the reference clock signal CLK. The latch 71 holds a high level when the reference clock signal CLK is not supplied when the switch SW _{2 is off.}

On the first panel 2, memory selection line groups SL ₁ , SL ₂ , ... Of the M group are arranged corresponding to the pixel Pix of the M row. Each of the memory selection lines SL ₁ , SL ₂ , ... Of the M group is electrically connected to the first memory selection line SEL _a and the second memory 52 electrically connected to the first memory 51 of the row. The second memory selection line SEL _b connected to the third memory 53 and the third memory selection line SEL _c electrically connected to the third memory 53 are included. Each of the memory selection line groups SL ₁ , SL ₂ , ... Of the M group follows the X direction in the display area DA (see FIG. 1).

The switch SW ₃ is controlled by the control signal Sig ₃ supplied from the timing controller 4b. When the control signal Sig ₃ has the first value, the switch SW ₃ has the output terminal of the latch 71 and the first memory selection line of each of the memory selection lines _{SL 1} , SL _{2, ... Of the M group.} The SEL _a is electrically connected. When the control signal Sig ₃ has a second value, the switch SW ₃ has the output terminal of the latch 71 and the second memory selection line of each of the memory selection lines _{SL 1} , SL _{2, ... Of the M group.} The SEL _b is electrically connected. When the control signal Sig ₃ has a third value, the switch SW ₃ has the output terminal of the latch 71 and the third memory selection line of each of the memory selection lines _{SL 1} , SL _{2, ... Of the M group.} It is electrically connected to the SEL _c.

Each sub-pixel SPix is a liquid crystal based on the sub-pixel data stored in one of the first memory 51 to the third memory 53 according to the memory selection line SEL to which the memory selection signal is supplied. Modulate layers. As a result, an image (frame) is displayed on the display surface.

On the first panel 2, M display signal lines FRP ₁ , FRP ₂ , ... Corresponding to the pixel Pix of the M line are arranged. Each of the M display signal lines FRP ₁ , FRP ₂ , ... Extends in the X direction in the display area DA (see FIG. 1). When the inversion switch 61 operates with an inverted display signal in which the display signal is inverted in addition to the display signal, a display signal line FRP and a second display signal line xFRP are provided per line.

One or two display signal lines arranged per line correspond to the display signal lines of the present invention.

The inverting drive circuit 7 includes a switch SW ₁ . The switch SW ₁ is controlled by the control signal Sig ₁ supplied from the timing controller 4b. When the control signal Sig ₁ has the first value, the switch SW ₁ supplies the reference clock signal CLK to the display signal lines FRP ₁ , FRP ₂ , .... As a result, the potential of the sub-pixel electrode 15 is inverted in synchronization with the reference clock signal CLK. When the control signal Sig ₁ has a second value, the switch SW ₁ supplies a reference potential (ground potential) GND to each display signal line FRP ₁ , FRP ₂ , ....

FIG. 5 is a diagram showing a circuit configuration of sub-pixels of the display device of the embodiment. FIG. 5 shows one sub-pixel SPix.

The sub-pixel SPix includes the memory block 50. The memory block 50 includes a first memory 51, a second memory 52, a third memory 53, switches Gsw ₁ to Gsw ₃ , and switches Msw ₁ to Msw ₃ .

The control input terminal of the switch Gsw ₁ is electrically connected to _{the first gate line GCL a.} The switch Gsw _{1 is turned on when a} high-level gate signal is supplied to the first gate line GCL _{a, and electrically connects the source line SGL 1} and the input terminal of the first memory 51. As a result, the sub-pixel data supplied to the _{source line SGL 1 is stored in the first memory 51.}

The control input terminal of the switch Gsw ₂ is electrically connected to _{the second gate line GCL b.} The switch Gsw ₂ is turned on when a high-level gate signal is supplied to the second gate line GCL _{b , and electrically connects the source line SGL 1} and the input terminal of the second memory 52. As a result, the sub-pixel data supplied to the _{source line SGL 1 is stored in the second memory 52.}

The control input terminal of the switch Gsw ₃ is electrically connected to _{the third gate line GCL c.} The switch Gsw ₃ is turned on when a high-level gate signal is supplied to the third gate line GCL _{c , and electrically connects the source line SGL 1} and the input terminal of the third memory 53. As a result, the sub-pixel data supplied to the _{source line SGL 1 is stored in the third memory 53.}

When switches Gsw ₁ to Gsw ₃ operate with a high-level gate signal, as shown in FIG. 5, the gate line group GL ₁ is from the first gate line GCL _a to the third gate line GCL _c. including. Switches operating with high-level gate signals are exemplified by N-channel transistors, but the present disclosure is not limited thereto.

On the other hand, when switches Gsw ₁ to Gsw ₃ operate with an inverted gate signal in which the gate signal is inverted in addition to the gate signal, the gate line group GL ₁ has the first gate line GCL _a to the third gate. In addition to the line GCL _{c, the fourth gate line xGCL a} to the sixth gate line xGCL _c to which the inverted gate signal is supplied is further included. The switch operated by the gate signal and the inverting gate signal is exemplified by a transfer gate, but the present disclosure is not limited thereto.

Input terminal is electrically connected to the first gate line GCL _a, an output terminal by providing the inverter circuit electrically connected to the fourth gate line xGCL _a, the inverted gate signal to the fourth gate line XGCL _a It is possible to supply. Similarly, by providing an inverter circuit in which the input terminal is electrically connected to the second gate line GCL _b and the output terminal is electrically connected to the fifth gate line, the inverted gate signal is transmitted to the fifth gate line x GCL _b. It is possible to supply to. Similarly, by providing an inverter circuit in which the input terminal is electrically connected to the third gate line GCL _c and the output terminal is electrically connected to the sixth gate line, the inverted gate signal is transmitted to the sixth gate line x GCL _c. It is possible to supply to.

The control input terminal of the switch Msw ₁ is electrically connected to _{the first memory selection line SEL a.} The switch Msw _{1 is turned on when a} high-level memory selection signal is supplied to the first memory selection line SEL a, and is electrically connected between the output terminal of the first memory 51 and the input terminal of the inverting switch 61. Connect to. As a result, the sub-pixel data stored in the first memory 51 is supplied to the inverting switch 61.

The control input terminal of the switch Msw ₂ is electrically connected to _{the second memory selection line SEL b.} The switch Msw ₂ is turned on when a high-level memory selection signal is supplied to the second memory selection line SEL _b , and is electrically connected between the output terminal of the second memory 52 and the input terminal of the inverting switch 61. Connect to. As a result, the sub-pixel data stored in the second memory 52 is supplied to the inverting switch 61.

The control input terminal of the switch Msw ₃ is electrically connected to _{the third memory selection line SEL c.} The switch Msw ₃ is turned on when a high-level memory selection signal is supplied to the third memory selection line SEL _c , and is electrically connected between the output terminal of the third memory 53 and the input terminal of the inverting switch 61. Connect to. As a result, the sub-pixel data stored in the third memory 53 is supplied to the inverting switch 61.

When switches Msw ₁ to Msw ₃ operate with a high-level memory selection signal, as shown in FIG. 5, the memory selection line group SL ₁ selects the third memory from the first memory selection line SEL _a. Includes up to line SEL _c. Switches operating with high-level gate signals are exemplified by N-channel transistors, but the present disclosure is not limited thereto.

On the other hand, when the switches Msw ₁ to Msw ₃ operate with the inverted memory selection signal in which the memory selection signal is inverted in addition to the memory selection signal, the memory selection line group SL ₁ has the first memory selection line SEL. _{In addition to a} to the third memory selection line SEL _c , the fourth memory selection line xSEL _a to the sixth memory selection line xSEL _c to which the inverted memory selection signal is supplied is further included. The switch that operates with the memory selection signal and the inverting memory selection signal is exemplified by a transfer gate, but the present disclosure is not limited thereto.

By providing an inverter circuit in which the input terminal is electrically connected to the first memory selection line SEL _a and the output terminal is electrically connected to the fourth memory selection line x SEL _a , the inverting memory selection signal is selected by the fourth memory. It is possible to supply the line xSEL _a. Similarly, by providing an inverter circuit in which the input terminal is electrically connected to the second memory selection line SEL _b and the output terminal is electrically connected to the fifth memory selection line x SEL _b , the inverting memory selection signal is transmitted. 5 It is possible to supply to the memory selection line xSEL _b. Similarly, by providing an inverter circuit in which the input terminal is electrically connected to the third memory selection line SEL _c and the output terminal is electrically connected to the sixth memory selection line x SEL _c , the inverting memory selection signal is transmitted to the third. 6 It is possible to supply to the memory selection line xSEL _c.

A display signal that reverses in synchronization with the reference clock signal CLK is supplied to the _{inverting switch 61 from the display signal line FRP 1.} The inverting switch 61 supplies the sub-pixel data stored in the first memory 51, the second memory 52, or the third memory 53 to the sub-pixel electrode 15 as it is or inverts based on the display signal. A liquid crystal LQ and a holding capacity C are provided between the sub-pixel electrode 15 and the common electrode 23. The holding capacitance C holds the voltage between the sub-pixel electrode 15 and the common electrode 23. The liquid crystal LQ changes the direction of the molecule based on the voltage between the sub-pixel electrode 15 and the common electrode 23, and displays the sub-pixel image.

When the inversion switch 61 operates with a display signal, one display signal line FRP ₁ is provided as shown in FIG. On the other hand, when the inversion switch 61 operates with an inverted display signal in which the display signal is inverted in addition to the display signal, a second display signal line xFRP ₁ is further provided in _{addition to the display signal line FRP 1.} Then, by providing an inverter circuit in which the input terminal is _{electrically connected to the display signal line FRP 1} and the output terminal is electrically connected to the second display signal line xFRP ₁ , the inverted display signal is transmitted to the second display signal line. It is possible to supply to xFRP _1.

FIG. 6 is a diagram showing a circuit configuration of a memory of sub-pixels of the display device of the embodiment. FIG. 6 is a diagram showing a circuit configuration of the first memory 51. Since the circuit configurations of the second memory 52 and the third memory 53 are the same as the circuit configurations of the first memory 51, illustration and description thereof will be omitted.

The first memory 51 has a SRAM (Static Random Access Memory) cell structure including an inverter circuit 81 and an inverter circuit 82 electrically connected in parallel to the inverter circuit 81 in the opposite direction. The input terminal of the inverter circuit 81 and the output terminal of the inverter circuit 82 form the node N1, and the output terminal of the inverter circuit 81 and the input terminal of the inverter circuit 82 form the node N2. The inverter circuits 81 and 82 operate using the power supplied from the power supply line VDD on the high potential side and the power supply line VSS on the low potential side.

Node N1 is electrically connected to the output terminal of the switch gsw _1. Node N2 is electrically connected to the input terminal of the switch Msw _1.

FIG. 6 shows an example in which a transfer gate is used as _{the switch Gsw 1.} One control input terminal of the switch Gsw ₁ is electrically connected to _{the first gate line GCL a.} The other control input terminal of the switch Gsw ₁ is electrically connected to _{the fourth gate line x GCL a.} An inverted gate signal, which is an inverted gate signal supplied to the first gate line GCL _a , is supplied to the fourth gate line xGCL _a.

The input terminal of the switch Gsw ₁ is electrically connected to _{the source line SGL 1.} The output terminal of the switch Gsw ₁ is electrically connected to the node N1. Switch gsw ₁ is the inverted gate signal gate signal supplied to the first gate line GCL _a is supplied to the high level and the fourth gate line XGCL _a becomes low level, turned on, and the source line SGL ₁ , Node N1 and the electrical connection. As a result, the _{sub-pixel data supplied to the source line SGL 1} is stored in the first memory 51.

FIG. 6 shows an example in which a transfer gate is used as _{the switch Msw 1.} One control input terminal of the switch Msw ₁ is electrically connected to _{the first memory selection line SEL a.} The other control input terminal of the switch Msw ₁ is electrically connected to _{the fourth memory selection line xSEL a.} An inverted memory selection signal obtained by inverting the memory selection signal supplied to the first memory selection line SEL _a is supplied to the fourth memory selection line xSEL _a.

The input terminal of the switch Msw ₁ is electrically connected to the node N2. The output terminal of the switch Msw ₁ is connected to the node N3. The node N3 is an output node of the first memory 51 and is electrically connected to the inverting switch 61 (see FIG. 5). The switch Msw ₁ is turned on when the memory selection signal supplied to the first memory selection line SEL _a becomes high level and the inverting memory selection signal supplied to _{the fourth memory selection line x SEL a becomes low level.} As a result, the node N2 is electrically connected to the input terminal of the inverting switch 61 via the _{switch Msw 1 and the node N3.} As a result, the sub-pixel data stored in the first memory 51 is supplied to the inverting switch 61.
When both the switches Gsw ₁ and Msw ₁ are in the off state, the sub-pixel data circulates in the loop composed of the inverter circuits 81 and 82. Therefore, the first memory 51 continues to hold the sub-pixel data.

In the embodiment, the case where the first memory 51 is an SRAM has been described as an example, but the present disclosure is not limited to this. Another example of the first memory 51 is a DRAM (Dynamic Random Access Memory).

FIG. 7 is a diagram showing a circuit configuration of an inverting switch for sub-pixels of the display device of the embodiment. The inverting switch 61 includes an inverter circuit 91, N-channel transistors 92 and 95, and P-channel transistors 93 and 94.

The input terminal of the inverter circuit 91, the gate terminal of the P channel transistor 94, and the gate terminal of the N channel transistor 95 are connected to the node N4. The node N4 is an input node of the inverting switch 61, and is electrically connected to the node N3 of the first memory 51, the second memory 52, and the third memory 53. Sub-pixel data is supplied to the node N4 from the first memory 51, the second memory 52, or the third memory 53. The inverter circuit 91 operates by using the power supplied from the power supply line VDD on the high potential side and the power supply line VSS on the low potential side.

One of the source and drain of the N-channel transistor 92 is electrically connected to _{the second display signal line xFRP 1.} The other of the source and drain of the N-channel transistor 92 is electrically connected to node N5.

One of the source and drain of the P-channel transistor 93 is electrically connected to the _{display signal line FRP 1.} The other of the source and drain of the P-channel transistor 93 is electrically connected to the node N5.

One of the source and drain of the P-channel transistor 94 is electrically connected to _{the second display signal line xFRP 1.} The other of the source and drain of the P-channel transistor 94 is electrically connected to node N5.

One of the source and drain of the N-channel transistor 95 is electrically connected to the _{display signal line FRP 1.} The other of the source and drain of the N-channel transistor 95 is electrically connected to node N5.

The node N5 is an output node of the inverting switch 61 and is electrically connected to the reflecting electrode (sub-pixel electrode) 15.

When the sub-pixel data supplied from the first memory 51, the second memory 52, or the third memory 53 is at a high level, the output signal of the inverter circuit 91 becomes a low level. When the output signal of the inverter circuit 91 is low level, the N-channel transistor 92 is turned off and the P-channel transistor 93 is turned on.

When the sub-pixel data supplied from the first memory 51, the second memory 52, or the third memory 53 is at a high level, the P-channel transistor 94 is turned off and the N-channel transistor 95 is turned on. Become.

Therefore, when the sub-pixel data supplied from the first memory 51, the second memory 52, or the third memory 53 is at a high level, the display signal _{supplied to the display signal line FRP 1} is the P channel transistor 93 and It is supplied to the sub-pixel electrode 15 via the N-channel transistor 95.

The display signal supplied to the display signal line FRP ₁ is synchronized with the reference clock signal CLK and inverted. The common potential supplied to the common electrode 23 is also synchronized with the reference clock signal CLK and inverted in phase with the display signal. When the display signal and the common potential are in phase, no voltage is applied to the liquid crystal LQ, so that the direction of the molecule does not change. As a result, the sub-pixels are displayed in black (a state in which the reflected light is not transmitted. A state in which the reflected light does not pass through the color filter and the color is not displayed). As a result, the display device 1 can realize the common reversal drive system.

When the sub-pixel data supplied from the first memory 51, the second memory 52, or the third memory 53 is at a low level, the output signal of the inverter circuit 91 becomes a high level. When the output signal of the inverter circuit 91 is at a high level, the N-channel transistor 92 is turned on and the P-channel transistor 93 is turned off.

When the sub-pixel data supplied from the first memory 51, the second memory 52, or the third memory 53 is at a low level, the P-channel transistor 94 is turned on and the N-channel transistor 95 is turned off. Become.

Therefore, when the sub-pixel data supplied from the first memory 51, the second memory 52, or the third memory 53 is at a low level, the inverted display signal supplied to _{the second display signal line xFRP 1 is N channel.} It is supplied to the sub-pixel electrode 15 via the transistor 92 and the P-channel transistor 94.

The inverted display signal supplied to the second display signal line xFRP ₁ is inverted in synchronization with the reference clock signal CLK. The common potential supplied to the common electrode 23 is synchronized with the reference clock signal CLK and inverted in phase with the display signal. When the display signal and the common potential are out of phase, a voltage is applied to the liquid crystal LQ, so that the direction of the molecule changes. As a result, the sub-pixels are displayed in white (a state in which the reflected light is transmitted. A state in which the reflected light is transmitted through the color filter and the color is displayed). As a result, the display device 1 can realize the common reversal drive system.

FIG. 8 is a diagram showing an outline of the layout of sub-pixels of the display device of the embodiment. The inverting switch 61, the first memory 51, the second memory 52, and the third memory 53 are arranged in the Y direction. The node N3, which is the output node of the first memory 51, the second memory 52, and the third memory 53, is electrically connected to the node N4, which is the input node of the inverting switch 61. The node N5, which is the output node of the inverting switch 61, is electrically connected to the sub-pixel electrode 15.

The first memory 51 includes a first gate line GCL _a , a fourth gate line xGCL _a , a first memory selection line SEL _a , a fourth memory selection line xSEL _a , a source line SGL _1, and a high potential side. It is electrically connected to the power supply line VDD and the power supply line VSS on the low potential side.

The second memory 52 includes a second gate line GCL _b , a fifth gate line xGCL _b , a second memory selection line SEL _b , a fifth memory selection line xSEL _b , a source line SGL _1, and a high potential side. It is electrically connected to the power supply line VDD and the power supply line VSS on the low potential side.

The third memory 53 includes a third gate line GCL _c , a sixth gate line xGCL _c , a third memory selection line SEL _c , a sixth memory selection line xSEL _c , a source line SGL _1, and a high potential side. It is electrically connected to the power supply line VDD and the power supply line VSS on the low potential side.

The inverting switch 61 is _{electrically connected to the display signal line FRP 1} , the second display signal line xFRP ₁ , the high potential side power supply line VDD, and the low potential side power supply line VSS.

[motion]
FIG. 9 is a timing diagram showing the operation timing of the display device of the embodiment. Throughout FIG. 9, the common electrode drive circuit 6 supplies the common electrode 23 with a common potential that inverts in synchronization with the reference clock signal CLK.

The period from the timing t ₀ to the timing t ₃ is the writing period of the sub-pixel data from the first memory 51 to the third memory 53 included in each of the N × 3 sub-pixel SPix in one line.

At the timing t ₀ , the timing controller 4b outputs the control signal Sig _{5 having the first value to the switch SW 4} in the gate line selection circuit 10. The switch SW ₄ electrically connects the output terminal of the gate line drive circuit 9 and the first gate line GCL _a. The gate line drive circuit 9 outputs a gate signal to the first gate line GCL _a of each line. _{When a} high-level gate signal is supplied to the first gate line GCL a, the first memory 51 of each of the sub-pixel SPix belonging to the line is selected as the write destination of the sub-pixel data.

Further, at the timing t ₀ , the source line drive circuit 5 outputs the sub-pixel data for displaying the image (frame) “A” to the source line SGL. As a result, the sub-pixel data for displaying the image "A" is written in the first memory 51 of each of the sub-pixel SPix belonging to each line.
Further, from the timing t _{0 to t 1} , such an operation is carried out in a line sequence from the first line to the M line. As a result, a signal for forming the image "A" is written and stored in the first memory of all the sub-pixel SPix.

At timing _{t 1,} the timing controller 4b is a control signal Sig ₅ of the second value, and outputs to the switch SW ₄ of the gate line selection circuit 10. The switch SW ₄ electrically connects the output terminal of the gate line drive circuit 9 and the second gate line GCL _b. The gate line drive circuit 9 outputs a gate signal to the second gate line GCL _b of each line. When a high-level gate signal is supplied to the second gate line GCL _b , the second memory 52 of each of the sub-pixel SPix belonging to the line is selected as the write destination of the sub-pixel data.

Further, at the timing t _1, the source line driver circuit 5, the sub-pixel data for displaying an image (frame) of "B" into the source line SGL. As a result, the sub-pixel data for displaying the image "B" is written in each of the second memory 52 of the sub-pixel SPix belonging to each line.
Further, from the first line to the Mth line, such an operation is carried out in line sequence from the first line to the Mth line over the timings t _{1 to t 2.} As a result, a signal for forming the image "B" is written and stored in the second memory of all the sub-pixel SPix.

At timing _{t 2,} the timing controller 4b is a control signal Sig ₅ of the third value, and outputs to the switch SW ₄ of the gate line selection circuit 10. The switch SW ₄ electrically connects the output terminal of the gate line drive circuit 9 and the third gate line GCL _c. The gate line drive circuit 9 outputs a gate signal to the third gate line GCL _c of each line. When a high-level gate signal is supplied to the third gate line GCL _c , the third memory 53 of each of the sub-pixel SPix belonging to the line is selected as the write destination of the sub-pixel data.

Further, at timing t _2, the source line driver circuit 5, the sub-pixel data for displaying an image (frame) "C" into the source line SGL. As a result, the sub-pixel data for displaying the image "C" is written in each of the third memory 53 of the sub-pixel SPix belonging to each line.
Furthermore, over the time t ₂ ~t _3, this operation is performed by the line sequential from the first row to the M line. As a result, a signal for forming the image "C" is written and stored in the third memory of all the sub-pixel SPix.

The display device 1 _{repeats the same operation as from timing t 0} to timing t ₃ M times, so that the first memory 51 to the third memory 53 included in each sub-pixel SPix are "A" and "B". And sub-pixel data for displaying the three images "C" can be written.

The period from timing t ₄ to timing t ₁₀ is an animation display (moving image display) period in which three images (three frames) of "A", "B", and "C" are sequentially switched and displayed.

At timing _{t 4,} the timing controller 4b is a control signal Sig ₂ for the first value, and outputs to the switch SW ₂ in the memory selection circuit 8. The switch SW ₂ is turned on based on the first value control signal Sig _{2 supplied from the timing controller 4b.} As a result, the reference clock signal CLK is supplied to the latch 71.

Further, at the timing _{t 4,} the timing controller 4b is a control signal Sig ₃ of the first value, and outputs to the switch SW ₃ in the memory selection circuit 8. The switch SW ₃ electrically connects the output terminal of the latch 71 and _{the first memory selection line SEL a} of each of the memory selection lines _{SL 1} , SL _{2, ... Of the M group.} As a result, the memory selection signal is supplied to the first memory selection line SEL _{a of each of the memory selection line groups SL 1} , SL _{2, ... Of the M group.}

Each first memory 51 connected to each first memory selection line SEL _a outputs sub-pixel data for displaying the image "A" to the inversion switch 61. Thus, at time t _4, the display device 1 displays the image "A".

At timing _{t 5,} the timing controller 4b is a control signal Sig ₂ for the second value, and outputs to the switch SW ₂ in the memory selection circuit 8. The switch SW ₂ is turned on based on the first value control signal Sig _{2 supplied from the timing controller 4b.} As a result, the reference clock signal CLK is supplied to the latch 71.

Further, at the timing _{t 5,} the timing controller 4b is a control signal Sig ₃ of the second value, and outputs to the switch SW ₃ in the memory selection circuit 8. The switch SW ₃ electrically connects the output terminal of the latch 71 and _{the second memory selection line SEL b} of each of the memory selection lines _{SL 1} , SL _{2, ... Of the M group.} As a result, the memory selection signal is supplied to the second memory selection line SEL _{b of each of the memory selection line groups SL 1} , SL _{2, ... Of the M group.}

Each second memory 52 connected to each second memory selection line SEL _b outputs sub-pixel data for displaying an image "B" to the inversion switch 61. Thus, at time t _5, the display device 1 displays an image of "B".

At timing _{t 6,} the timing controller 4b is a control signal Sig ₂ for the second value, and outputs to the switch SW ₂ in the memory selection circuit 8. The switch SW ₂ is turned on based on the first value control signal Sig _{2 supplied from the timing controller 4b.} As a result, the reference clock signal CLK is supplied to the latch 71.

Further, at the timing _{t 6,} the timing controller 4b is a control signal Sig ₃ of the third value, and outputs to the switch SW ₃ in the memory selection circuit 8. The switch SW ₃ electrically connects the output terminal of the latch 71 and _{the third memory selection line SEL c} of each of the memory selection lines _{SL 1} , SL _{2, ... Of the M group.} As a result, the memory selection signal is supplied to the third memory selection line SEL _{c of each of the memory selection line groups SL 1} , SL _{2, ... Of the M group.}

Each third memory 53 connected to the third memory selection line SEL _c outputs sub-pixel data for displaying the image "C" to the inversion switch 61. Thus, at time t _6, the display device 1 displays the image "C".

Since the operation of each section from the timing t ₇ to the time t ₉ is the same as the operation of each section from the timing t ₄ to time t _6, the description thereof is omitted.

As described above, the display device 1 sequentially switches and displays three images (three frames) of "A", "B", and "C" in the period _{from timing t 4} to timing t _10. (Video display) can be performed.

The period from timing t ₁₀ to timing t ₁₂ is a still image display period for displaying the image "A".

At timing _{t 10,} the timing controller 4b is a control signal Sig ₂ for the second value, and outputs to the switch SW ₂ in the memory selection circuit 8. The switch SW ₂ is turned off based on _{the control signal Sig 2} having a second value supplied from the timing controller 4b. As a result, the reference clock signal CLK is not supplied to the latch 71. The latch 71 holds a high level.

Further, at the timing t ₁₀ , the timing controller 4b outputs the control signal Sig _{3 having the first value to the switch SW 3} in the memory selection circuit 8. The switch SW ₃ electrically connects the output terminal of the latch 71 and _{the first memory selection line SEL a} of each of the memory selection lines _{SL 1} , SL _{2, ... Of the M group.} The same driving as the above, in the timing t ₁₀ to the timing t _12, the display device 1 is still image display the image "A".

In order to display the image (frame) of "X" in the second memory 52 included in each sub-pixel SPix at _{the timing t 11} within the still image display period in which the image of "A" is displayed. Sub-pixel data can be written.

At timing _{t 11,} the timing controller 4b is a control signal Sig ₅ of the second value, and outputs to the switch SW ₄ of the gate line selection circuit 10. The switch SW ₄ electrically connects the output terminal of the gate line drive circuit 9 and the second gate line GCL _b. The gate line drive circuit 9 outputs a gate signal to the second gate line GCL _b of each line. When a high-level gate signal is supplied to the second gate line GCL _b , the second memory 52 of each of the sub-pixel SPix belonging to the line is selected as the write destination of the sub-pixel data.

Further, at a timing t _11, the source line driving circuit 5, the sub-pixel data for displaying an image of "X" into the source line SGL. As a result, the sub-pixel data for displaying the image "X" is written in each of the second memory 52 of the sub-pixel SPix belonging to each line.

The display device 1 writes the sub-pixel data for displaying the image (frame) "X" in the second memory 52 included in each sub-pixel SPix by repeating the same operation as the _{timing t 11 M times.} be able to.

In FIG. 9, the image "X" is displayed in the second memory 52 included in each sub-pixel SPix at _{the timing t 11} within the still image display period in which the image "A" is displayed. The case of writing the sub-pixel data for the purpose has been described. However, for example, during the animation display (moving image display) period, from timing t _{6 to timing t 8} when the images "C" and "A" are displayed in animation (moving image display), each sub-pixel SPix is displayed. It is also possible to write sub-pixel data for displaying the image "X" in the included second memory 52.

Timing t ₁₂ after the "X", "C" and animated sequentially switching and displaying the three images of "A" (three frames) (moving image display) period.

At timing _{t 12,} the timing controller 4b is a control signal Sig ₂ for the second value, and outputs to the switch SW ₂ in the memory selection circuit 8. The switch SW ₂ is turned on based on the first value control signal Sig _{2 supplied from the timing controller 4b.} As a result, the reference clock signal CLK is supplied to the latch 71.

Further, at a timing _{t 12,} the timing controller 4b is a control signal Sig ₃ of the second value, and outputs to the switch SW ₃ in the memory selection circuit 8. The switch SW ₃ electrically connects the output terminal of the latch 71 and _{the second memory selection line SEL b} of each of the memory selection lines _{SL 1} , SL _{2, ... Of the M group.} As a result, the memory selection signal is supplied to the second memory selection line SEL _{b of each of the memory selection line groups SL 1} , SL _{2, ... Of the M group.}

Each second memory 52 connected to each second memory selection line SEL _b outputs sub-pixel data for displaying an image "X" to the inversion switch 61. Thus, at the timing t _12, the display device 1 displays an image of "X".

Since the operation of each part from timing t ₁₃ to timing t ₁₄ is the same as the operation of each part from timing t _{6 to timing t 7} , the description thereof will be omitted.

Since the operation of each part after the timing t ₁₅ is the same as the operation of each part _{from the timing t 12} to the timing t ₁₄ , the description thereof will be omitted.

In the display device described in Patent Document 1, switching of a plurality of memories included in each of the plurality of pixels is performed by line sequential scanning using a scanning signal. Therefore, in the display device described in Patent Document 1, one frame time is required to switch the plurality of memories of all the pixels. That is, in the display device described in Patent Document 1, one frame time is required to change the image (frame).

On the other hand, in the display device 1 of the embodiment, the memory selection circuit 8 provided outside the display area DA simultaneously selects one of the first memory 51 to the third memory 53 of each sub-pixel SPix. Therefore, the display device 1 displays one image (frame) out of the three images (three frames) by switching the selection of the first memory 51 to the third memory 53 of each sub-pixel SPix. Can be done. As a result, the display device 1 can change the images all at once, and can change the images in a short time. Further, the display device 1 can perform animation display (animation display) by sequentially switching the selection of the first memory 51 to the third memory 53 of each sub-pixel SPix.

Further, in the display device described in Patent Document 1, each pixel includes a memory selection control circuit and a rewrite instruction circuit in order to switch the memory. Therefore, the display device described in Patent Document 1 cannot meet the demand for miniaturization and high definition of the image display panel.

On the other hand, in the display device 1 of the embodiment, when writing the sub-pixel data, the gate line selection circuit 10 arranged in the frame area GD selects any of the first memory 51 to the third memory 53. Further, when reading the sub-pixel data, the memory selection circuit 8 arranged in the frame area GD selects any of the first memory 51 to the third memory 53. Therefore, each pixel Pix does not need to include a circuit for switching the memory. As a result, the display device 1 can meet the demand for further miniaturization and high definition of the image display panel in addition to the above-mentioned effects.

Further, in the display device 1 of the embodiment, from the first memory 51 during the period in which the image is displayed based on the sub-pixel data stored in any one of the first memory 51 to the third memory 53. Sub-pixel data can also be written to any one of the other up to the third memory 53. As a result, the display device 1 can write sub-pixel data of another image while displaying the image.

[Application example]
FIG. 10 is a diagram showing an application example of the display device of the embodiment. FIG. 10 is a diagram showing an example in which the display device 1 is applied to an electronic shelf label.

As shown in FIG. 10, the display devices 1A, 1B, and 1C are attached to the shelves 102, respectively. Each of the display devices 1A, 1B and 1C has the same configuration as the display device 1 described above. The display devices 1A, 1B, and 1C are installed so that the heights from the floor surface 103 are different from each other and the panel inclination angles are different from each other. Here, the panel tilt angle is an angle formed by the normal line of the display surface 1a and the horizontal direction. The display devices 1A, 1B, and 1C project the image 120 to the observer 105 side by reflecting the incident light 110 from the luminaire 100 as a light source.

Although preferred embodiments of the present invention have been described above, the present invention is not limited to such embodiments. The contents disclosed in the embodiments are merely examples, and various modifications can be made without departing from the spirit of the present invention. Appropriate changes made without departing from the spirit of the present invention naturally belong to the technical scope of the present invention. At least one of the various omissions, substitutions, and changes of the components can be made without departing from the gist of each of the above-described embodiments and modifications.

1, 1A, 1B, 1C Display device 1a Display surface 2 1st panel 3 2nd panel 4 Interface circuit 4a Serial-parallel conversion circuit 4b Timing controller 4c Setting register 5 Source line drive circuit 6 Common electrode drive circuit 7 Inversion drive circuit 8 Memory selection circuit 9 Gate line drive circuit 10 Gate line selection circuit 11 First substrate 15 Sub-pixel electrode (reflection electrode)
21 2nd substrate 23 Common electrode 30 Liquid crystal layer 50 Memory block 51 1st memory 52 2nd memory 53 3rd memory 61 Inversion switch FRP display signal line GL gate line group GCL gate line Pix pixel SPix sub-pixel SL memory selection line group SEL Memory selection line

Claims (5)

A pixel electrode, a first memory and a second memory for storing sub-pixel data for controlling display by the pixel electrode, a first memory switch provided between the first memory and the pixel electrode, and a second memory. A plurality of sub-pixels each including a second memory switch provided between the pixel electrodes and
A first memory selection line connected to the first memory switch of each sub-pixel, a second memory selection line connected to the second memory switch, and the like.
A memory selection circuit connected to the first memory selection line and the second memory selection line and supplying a memory selection signal to one of the memory selection lines.
With
The plurality of sub-pixels
An image is displayed based on the sub-pixel data stored in either the first memory or the second memory according to the memory selection line to which the memory selection signal is supplied from the memory selection circuit.
The length of the period for supplying the memory selection signal to the first memory selection line by the memory selection circuit is the same as the length of the period for supplying the memory selection signal to the second memory selection line.
Display device. The memory selection circuit
After supplying the memory selection signal to the first memory selection line, the memory selection signal is supplied to the second memory selection line, and immediately after that, the memory selection signal is supplied to the first memory selection line again. Item 1. The display device according to item 1. The display device according to claim 2, wherein the length of the period during which the memory selection circuit supplies a memory selection signal to each memory selection line is the same. Each sub-pixel is further provided with a third memory for storing sub-pixel data displayed by the pixel electrodes and a third memory switch provided between the third memory and the pixel electrodes.
A third memory switch and a third memory selection line connected to the memory selection circuit are further provided.
The plurality of sub-pixels
An image is created based on the sub-pixel data stored in any of the first memory, the second memory, and the third memory according to the memory selection line to which the memory selection signal is supplied from the memory selection circuit. Display and
The length of the period for supplying the memory selection signal to the first memory selection line by the memory selection circuit, the length of the period for supplying the memory selection signal to the second memory selection line, and the memory selection signal to the third memory selection line. The length of the supply period is the same,
The display device according to any one of claims 1 to 3. A common electrode provided so as to face the pixel electrodes of the plurality of sub-pixels,
A common electrode drive circuit that outputs a common potential that inverts at a predetermined cycle in synchronization with the reference signal to the common electrode, and
A first display signal line that supplies a display signal that is in phase with the common potential, and a second display signal line that supplies a display signal that is in phase opposite to the common potential.
Further prepare
Each of the sub-pixels
A switch circuit for connecting either the first display signal line or the second display signal line to the sub-pixel electrode is further provided based on the sub-pixel data output from either memory.
The memory selection circuit
It is synchronized with the common electrode drive circuit based on the reference signal, and the length of the inversion drive period of the common potential in the period of supplying the memory selection signal supplied to each memory selection line is the same.
The display device according to any one of claims 1 to 4.

Images