JP6978971B2 - Display device - Google Patents

Description

The present invention relates to a display device.

A display device for displaying an image includes a plurality of pixels. The following Patent Document 1 describes a so-called MIP (Memory In Pixel) type display device in which each of a plurality of pixels includes a memory. In the display device described in Patent Document 1, each of the plurality of pixels includes a plurality of memories and a switching circuit for these memories.

Japanese Unexamined Patent Publication No. 9-212140

In the display device, the pixel displays an image (frame) according to the voltage between the pixel electrode and the common electrode. Further, in the display device, in order to suppress the burn-in of the screen, a common inversion drive method that inverts the potential of the common electrode may be used. It is desirable that the frequency at which the frame is changed and the frequency at which the polarity of the common electrode is reversed can be different depending on the usage mode of the display device.

An object of the present invention is to provide a display device capable of making the frequency at which the frame is changed and the frequency at which the potential of the common electrode is inverted different.

The display device of one aspect of the present invention is based on a plurality of sub-pixels and a reference clock signal, each of which is arranged in a row direction and a column direction and includes a memory block having a plurality of memories for storing sub-pixel data. A clock signal output circuit that outputs a plurality of clock signals having different frequencies and a selection circuit that selects one of the plurality of clock signals as a selection clock signal are provided in each line. A plurality of memory selection line groups each including a plurality of memory selection lines electrically connected to the memory block of the sub-pixel belonging to the above, and a plurality of memories in the memory block in synchronization with the selection clock signal. A memory selection circuit that outputs a memory selection signal that selects one memory to multiple memory selection line groups at the same time, a common electrode that supplies a common potential to multiple sub-pixels, and a common potential synchronized with the reference clock signal. It is provided with a common electrode drive circuit that is inverted and output to the common electrode. The plurality of sub-pixels display an image based on the sub-pixel data stored in one of the plurality of memories according to the memory selection line to which the memory selection signal is supplied.

The display device of one aspect of the present invention is based on a plurality of sub-pixels and a reference clock signal, each of which is arranged in a row direction and a column direction and includes a memory block having a plurality of memories for storing sub-pixel data. A clock signal output circuit that outputs a plurality of clock signals having different frequencies, one of the plurality of clock signals is selected as the first selection clock signal, and one of the plurality of clock signals is selected as the first selection clock signal. 2 A plurality of memories including a selection circuit for selecting as a selection clock signal and a plurality of memory selection lines each provided in each row and electrically connected to a memory block of a sub-pixel belonging to the row. A memory selection circuit that simultaneously outputs a memory selection signal that selects one memory from a plurality of memories in a memory block in synchronization with the selection line group and the first selection clock signal to a plurality of memory selection line groups, and a plurality of memory selection circuits. It is provided with a common electrode to which a common common potential is supplied to the sub-pixels of the above, and a common electrode drive circuit that inverts the common potential in synchronization with the second selection clock signal and outputs it to the common electrode. The plurality of sub-pixels display an image based on the sub-pixel data stored in one of the plurality of memories according to the memory selection line to which the memory selection signal is supplied.

FIG. 1 is a diagram showing an outline of the overall configuration of the display device of the first embodiment. FIG. 2 is a cross-sectional view of the display device of the first embodiment. FIG. 3 is a diagram showing the arrangement of sub-pixels within the pixels of the display device of the first embodiment. FIG. 4 is a diagram showing a circuit configuration of a frequency dividing circuit and a selection circuit of the display device of the first embodiment. FIG. 5 is a diagram showing a waveform of a frequency-divided clock signal of the display device of the first embodiment. FIG. 6 is a diagram showing a module configuration of the display device of the first embodiment. FIG. 7 is a diagram showing a circuit configuration of the display device of the first embodiment. FIG. 8 is a diagram showing a circuit configuration of sub-pixels of the display device of the first embodiment. FIG. 9 is a diagram showing a circuit configuration of a memory of a sub-pixel of the display device of the first embodiment. FIG. 10 is a diagram showing a circuit configuration of an inverting switch for sub-pixels of the display device of the first embodiment. FIG. 11 is a diagram showing an outline of the layout of sub-pixels of the display device of the first embodiment. FIG. 12 is a timing diagram showing the first operation timing of the display device of the first embodiment. FIG. 13 is a timing diagram showing a second operation timing of the display device of the first embodiment. FIG. 14 is a diagram showing an outline of the overall configuration of the display device of the second embodiment. FIG. 15 is a diagram showing a circuit configuration of a frequency dividing circuit and a selection circuit of the display device of the second embodiment. FIG. 16 is a diagram showing a module configuration of the display device of the second embodiment. FIG. 17 is a diagram showing a circuit configuration of the display device of the second embodiment. FIG. 18 is a timing diagram showing the first operation timing of the display device of the second embodiment. FIG. 19 is a timing diagram showing a second operation timing of the display device of the second embodiment. FIG. 20 is a diagram showing a circuit configuration of the display device of the third embodiment. FIG. 21 is a diagram showing a circuit configuration of an inverting switch for sub-pixels of the display device of the third embodiment. FIG. 22 is a timing diagram showing the operation timing of the display device according to the third embodiment. FIG. 23 is a diagram showing an application example of the display device of the first to third embodiments.

An embodiment (embodiment) for carrying out the present invention will be described in detail with reference to the drawings. The disclosure is not limited by the content described in the following embodiments. In addition, the components described below include those that can be easily assumed by those skilled in the art and those that are substantially the same. Furthermore, the components described below can be combined as appropriate. It should be noted that the disclosure is merely an example, and those skilled in the art can easily conceive of appropriate changes while maintaining the gist of the invention are naturally included in the scope of the present disclosure. In addition, in order to clarify the explanation, the drawings may schematically represent the width, thickness, shape, etc. of each part as compared with the actual embodiment, but this is just an example, and the interpretation of the present disclosure is used. It is not limited. Further, in the present specification and each figure, the same elements as those described above with respect to the above-mentioned figures may be designated by the same reference numerals, and detailed description thereof may be omitted as appropriate.

(First Embodiment)
[overall structure]
FIG. 1 is a diagram showing an outline of the overall configuration of the display device of the first embodiment. The display device 1 includes a first panel 2 and a second panel 3 arranged to face the first panel 2. The display device 1 has a display area DA for displaying an image and a frame area GD outside the display area DA. In the display area DA, a liquid crystal layer is enclosed between the first panel 2 and the second panel 3.

In the first embodiment, the display device 1 is a liquid crystal display device using a liquid crystal layer, but the present disclosure is not limited to this. The display device 1 may be an organic EL display device that uses an organic EL (Electro-Luminescence) element instead of the liquid crystal layer.

In the display area DA, a plurality of pixels Pix are arranged in N columns (N is a natural number) in the X direction parallel to the main surfaces of the first panel 2 and the second panel 3, and the first panel 2 and the second panel 3 are arranged. They are arranged in a matrix of M rows (M is a natural number) in the Y direction parallel to the main surface and intersecting the X direction.

In the frame area GD, an interface circuit 4, a source line drive circuit 5, a common electrode drive circuit 6, an inverting drive circuit 7, a memory selection circuit 8, a gate line drive circuit 9, and a gate line selection circuit 10 are included. , The frequency dividing circuit 31, and the selection circuit 32 are arranged. Among these plurality of circuits, the interface circuit 4, the source line drive circuit 5, the common electrode drive circuit 6, the inverting drive circuit 7, the memory selection circuit 8, the frequency dividing circuit 31, and the selection circuit 32. It is also possible to adopt a configuration in which the gate line drive circuit 9 and the gate line selection circuit 10 are formed on the first panel 2 by incorporating the above into an IC chip. Alternatively, it is also possible to adopt a configuration in which a group of circuits incorporated in the IC chip is formed in a processor outside the display device and these are connected to the display device 1.

Each of the M × N pixel Pix includes a plurality of sub-pixel SPix. In the first embodiment, the plurality of sub-pixel SPix is R (red), G (green), and B (blue), but the present disclosure is not limited to this. The plurality of sub-pixel SPix may be four, which is R (red), G (green), B (blue) plus W (white). Alternatively, the plurality of sub-pixel SPix may be five or more having different colors.

In the first embodiment, since there are three sub-pixel SPix included in one pixel Pix, M × N × 3 sub-pixel SPix are arranged in the display area DA. Further, in the first embodiment, since the three sub-pixel SPix of each of the M × N pixel Pix are arranged in the X direction, N is included in one row of the M × N pixel Pix. × 3 sub-pixel SPix are arranged.

Each sub-pixel SPix includes a plurality of memories. In the first embodiment, the plurality of memories is three from the first memory to the third memory, but the present disclosure is not limited to this. The plurality of memories may be two or four or more.

In the first embodiment, since one sub-pixel SPix contains three memories, M × N × 3 × 3 memories are arranged in the display area DA. Further, in the first embodiment, since each sub-pixel SPix includes three memories, N × 3 × 3 memories are arranged in one row of M × N pixels Pix. Will be there.

Each sub-pixel SPix displays the sub-pixel SPix based on the sub-pixel data stored in one selected memory from the first memory to the third memory included in each sub-pixel SPix. That is, the set of M × N × 3 × 3 memories included in the M × N × 3 sub-pixel SPix is equivalent to the three frame memories.

The interface circuit 4 includes a serial-parallel conversion circuit 4a and a timing controller 4b. The timing controller 4b includes a setting register 4c. The command data CMD and the image data ID are supplied to the serial-parallel conversion circuit 4a as serial data from the external circuit. The external circuit is exemplified by a host CPU (Central Processing Unit) or an application processor, but the present disclosure is not limited thereto.

The serial-parallel conversion circuit 4a converts the supplied command data CMD into parallel data and outputs it to the setting register 4c. In the setting register 4c, values for controlling the source line drive circuit 5, the inverting drive circuit 7, the memory selection circuit 8, the gate line drive circuit 9, the gate line selection circuit 10 and the selection circuit 32 are set based on the command data CMD. Set.

The serial-parallel conversion circuit 4a converts the supplied image data ID into parallel data and outputs it to the timing controller 4b. The timing controller 4b outputs the image data ID to the source line drive circuit 5 based on the value set in the setting register 4c. Further, the timing controller 4b controls the inverting drive circuit 7, the memory selection circuit 8, the gate line drive circuit 9, the gate line selection circuit 10 and the selection circuit 32 based on the values set in the setting register 4c.

The reference clock signal CLK is supplied from the external circuit to the common electrode drive circuit 6, the inverting drive circuit 7, and the frequency dividing circuit 31. The external circuit is exemplified by a clock generator, but the present disclosure is not limited to this.

The frequency dividing circuit 31 outputs a plurality of clock signals having different frequencies to the selection circuit 32 based on the reference clock signal CLK. Specifically, the frequency dividing circuit 31 outputs a plurality of divided clock signals obtained by dividing the reference clock signal CLK by a plurality of dividing ratios to the selection circuit 32.

The selection circuit 32 selects one of the plurality of divided clock signals as the selection clock signal CLK-SEL under the control of the timing controller 4b. The selection circuit 32 outputs the selection clock signal CLK-SEL to the memory selection circuit 8.

In the first embodiment, the display device 1 adopts a common inversion drive system. Since the display device 1 adopts the common inversion drive method, the common electrode drive circuit 6 inverts the potential (common potential) of the common electrode in synchronization with the reference clock signal CLK. The inverting drive circuit 7 inverts the potential of the sub-pixel electrode in synchronization with the reference clock signal CLK under the control of the timing controller 4b. Thereby, the display device 1 can realize the common inversion drive system. In the first embodiment, the display device 1 is a so-called normally black liquid crystal display device that displays black when a voltage is not applied to the liquid crystal display and displays white color when a voltage is applied to the liquid crystal display. do. In the normally black liquid crystal display device, black is displayed when the potential of the sub-pixel electrode and the common potential are in phase, and white is displayed when the potential of the sub-pixel electrode and the common potential are out of phase. .. Not limited to this, when the potential of the sub-pixel electrode and the common potential are in phase, white is displayed, and when the potential of the sub-pixel electrode and the common potential are out of phase, black is displayed. A Marie White configuration is also available.

In order to display an image on the display device 1, it is necessary to store the sub-pixel data in the first memory to the third memory of each sub-pixel SPix. In order to store the sub-pixel data in each memory, the gate line drive circuit 9 outputs a gate signal for selecting one row among the M × N pixel Pix under the control of the timing controller 4b. ..

In a MIP type liquid crystal display device in which each sub-pixel has one memory, one gate line is arranged for one row (pixel row (sub-pixel row)). However, in the embodiment, each sub-pixel SPix includes three memories from the first memory to the third memory. Therefore, in the embodiment, three gate lines are arranged per row. The three gate lines are electrically connected to the first memory to the third memory of each of the sub-pixel SPix included in one row. When the sub-pixel SPix operates with an inverted gate signal in which the gate signal is inverted in addition to the gate signal, six gate lines are arranged per row.

Three or six gate lines arranged per row correspond to a group of gate lines. In the first embodiment, since the display device 1 has M rows of pixels Pix, the gate line group of the M group is arranged.

The gate line drive circuit 9 has M output terminals corresponding to the pixel Pix in the M row. The gate line drive circuit 9 sequentially outputs a gate signal for selecting one of the M rows from the M output terminals under the control of the timing controller 4b.

The gate line selection circuit 10 selects one of the three gate lines arranged in one row under the control of the timing controller 4b. As a result, the gate signal output from the gate line drive circuit 9 is supplied to the selected one of the three gate lines arranged in one row.

The source line drive circuit 5 outputs sub-pixel data to the memory selected by the gate signal under the control of the timing controller 4b, respectively. As a result, the sub-pixel data is sequentially stored in the first memory to the third memory of each sub-pixel SPix.

The display device 1 stores the sub-pixel data of one frame data in the first memory of each sub-pixel SPix by linearly scanning the pixel Pix in the M row. Then, the display device 1 executes the line sequential scan three times, so that three frame data are stored in the first memory to the third memory of each sub-pixel SPix.

At this time, the display device 1 can also adopt a procedure of writing to the first memory, writing to the second memory, and writing to the third memory for each scan of one line. By performing such scanning from the first row to the Mth row, the sub-pixel data can be stored in the first memory to the third memory of each sub-pixel SPix by one line sequential scan.

In the first embodiment, three memory selection lines are arranged per line. The three memory selection lines are electrically connected to the first memory to the third memory of each of the N × 3 sub-pixel SPix included in one row. When the sub-pixel SPix operates with an inverted memory selection signal in which the memory selection signal is inverted in addition to the memory selection signal, six memory selection lines are arranged per line.

Three or six memory selection lines arranged per line correspond to the memory selection line group. In the first embodiment, since the display device 1 has the pixel Pix of M rows, the memory selection line group of M group is arranged.

Under the control of the timing controller 4b, the memory selection circuit 8 simultaneously selects one of the first memory to the third memory of each sub-pixel SPix in synchronization with the selection clock signal CLK-SEL. More specifically, the first memory of all the sub-pixel SPix is selected at the same time. Alternatively, the second memory of all the sub-pixel SPix is selected at the same time. Alternatively, the third memory of all the sub-pixel SPix is selected at the same time. Therefore, the display device 1 can display one of the three images by switching the selection from the first memory to the third memory of each sub-pixel SPix. As a result, the display device 1 can change the images all at once, and can change the images in a short time. Further, the display device 1 can perform animation display (moving image display) by sequentially switching the selection from the first memory to the third memory of each sub-pixel SPix.

[Cross-sectional structure]
FIG. 2 is a cross-sectional view of the display device of the first embodiment. As shown in FIG. 2, the display device 1 includes a first panel 2, a second panel 3, and a liquid crystal layer 30. The second panel 3 is arranged to face the first panel 2. The liquid crystal layer 30 is provided between the first panel 2 and the second panel 3. One main surface of the second panel 3 is a display surface 1a for displaying an image.

The light incident from the outside on the display surface 1a side is reflected by the reflection electrode 15 of the first panel 2 and emitted from the display surface 1a. The display device 1 is a reflective liquid crystal display device that displays an image on the display surface 1a by using the reflected light. In the present specification, the direction parallel to the display surface 1a is defined as the X direction, and the direction intersecting the X direction on the surface parallel to the display surface 1a is defined as the Y direction. Further, the direction perpendicular to the display surface 1a is the Z direction.

The first panel 2 has a first substrate 11, an insulating layer 12, a reflecting electrode 15, and an alignment film 18. The first substrate 11 is exemplified by a glass substrate or a resin substrate. Circuit elements (not shown) and various wirings such as gate lines and data lines are provided on the surface of the first substrate 11. The circuit element includes a switching element such as a TFT (Thin Film Transistor) and a capacitive element.

The insulating layer 12 is provided on the first substrate 11 and flattens the surface of circuit elements, various wirings, and the like as a whole. A plurality of reflective electrodes 15 are provided on the insulating layer 12. The alignment film 18 is provided between the reflective electrode 15 and the liquid crystal layer 30. The reflection electrode 15 is provided in a rectangular shape for each sub-pixel SPix. The reflective electrode 15 is made of a metal exemplified by aluminum (Al) or silver (Ag). Further, the reflective electrode 15 may be configured by laminating these metal materials and a translucent conductive material exemplified by ITO (Indium Tin Oxide). The reflective electrode 15 is made of a material having good reflectance and functions as a reflector that diffusely reflects light incident from the outside.

The light reflected by the reflective electrode 15 is scattered by diffuse reflection, but travels in a uniform direction toward the display surface 1a side. Further, as the voltage level applied to the reflecting electrode 15 changes, the light transmission state in the liquid crystal layer 30 on the reflection electrode, that is, the light transmission state for each sub-pixel changes. That is, the reflective electrode 15 also has a function as a sub-pixel electrode.

The second panel 3 includes a second substrate 21, a color filter 22, a common electrode 23, an alignment film 28, a 1/4 wave plate 24, a 1/2 wave plate 25, and a polarizing plate 26. A color filter 22 and a common electrode 23 are provided on both sides of the second substrate 21 facing the first panel 2 in this order. An alignment film 28 is provided between the common electrode 23 and the liquid crystal layer 30. The 1/4 wave plate 24, the 1/2 wave plate 25, and the polarizing plate 26 are laminated in this order on the surface of the second substrate 21 on the display surface 1a side.

The second substrate 21 is exemplified by a glass substrate or a resin substrate. The common electrode 23 is made of a translucent conductive material exemplified by ITO. The common electrode 23 is arranged to face the plurality of reflective electrodes 15 and supplies a common potential for each sub-pixel SPix. It is exemplified that the color filter 22 has a filter of three colors of R (red), G (green), and B (blue), but the present disclosure is not limited to this.

It is exemplified that the liquid crystal layer 30 includes a Nematic liquid crystal. The liquid crystal layer 30 changes the orientation state of the liquid crystal molecules by changing the voltage level between the common electrode 23 and the reflective electrode 15. As a result, the light transmitted through the liquid crystal layer 30 is modulated for each sub-pixel SPix.

External light or the like becomes incident light incident from the display surface 1a side of the display device 1, passes through the second panel 3 and the liquid crystal layer 30, and reaches the reflective electrode 15. Then, the incident light is reflected by the reflection electrode 15 of each sub-pixel SPix. The reflected light is modulated for each sub-pixel SPix and emitted from the display surface 1a. As a result, the image is displayed.

[Circuit configuration]
FIG. 3 is a diagram showing the arrangement of sub-pixels within the pixels of the display device of the first embodiment. The pixel Pix includes an R (red) sub-pixel SPix _R , a G (green) sub-pixel SPix _G, and a B (blue) sub-pixel SPix _B. The sub-pixels SPix _R , SPix _G, and SPix _B are arranged in the X direction.

Each of the sub-pixels SPix _R , SPix _G, and SPix _B includes a memory block 50 and an inverting switch 61. The memory block 50 includes a first memory 51, a second memory 52, and a third memory 53. The inverting switch 61, the first memory 51, the second memory 52, and the third memory 53 are arranged in the Y direction.

Each of the first memory 51, the second memory 52, and the third memory 53 is a memory cell that stores 1-bit data, but the present disclosure is not limited thereto. Each of the first memory 51, the second memory 52, and the third memory 53 may be a memory cell that stores data of 2 bits or more.

The inverting switch 61 is electrically connected between the first memory 51, the second memory 52, and the third memory 53, and the sub-pixel electrode (reflection electrode) 15 (see FIG. 2). The inverting switch 61 is the first based on a display signal supplied from the inverting drive circuit 7 that changes in phase with the reference clock signal CLK and changes in phase with the reference clock signal CLK. The sub-pixel data output from one selected memory in the memory 51, the second memory 52, and the third memory 53 is inverted at regular intervals and output to the sub-pixel electrode 15. The cycle in which the display signal is inverted is the same as the cycle in which the potential (common potential) of the common electrode 23 is inverted.

The inverting switch 61 corresponds to the switch circuit.

FIG. 4 is a diagram showing a circuit configuration of a frequency dividing circuit and a selection circuit of the display device of the first embodiment.

Frequency dividing circuit 31 includes a daisy chain (daisy chain) connection, from the first 1/2 frequency divider 33 ₁ to the fourth 1/2 frequency divider 33 _4. Each of the first 1/2 frequency divider 33 ₁ to the fourth 1/2 frequency divider 33 ₄ may be constituted by a flip-flop.

The first 1/2 frequency divider 33 _1, a reference clock signal CLK, the first divided clock signal _{CLK-X 0} is supplied. The first divided clock signal CLK-X ₀ can be considered as a signal obtained by dividing the reference clock signal CLK by 1/1.

The first 1/2 frequency divider 33 _1, the second divided clock signal _{CLK-X 1} in which the first divided clock signal _{CLK-X 0} divided by 2, a second 1/2 frequency-divided and outputs the vessel 33 ₂ and the selection circuit 32. The second 1/2 divider 33 ₂ divides the second divided clock signal CLK-X ₁ by 1/2 and divides the third divided clock signal CLK-X ₂ by a third 1/2. Output to the device 33 ₃ and the selection circuit 32.

The third 1/2 divider 33 ₃ divides the 4th divided clock signal CLK-X ₃ by 1/2 divided by the 3rd divided clock signal CLK-X ₂ by the 4th 1/2 divider. and outputs the vessel 33 ₄ and the selection circuit 32. The fourth 1/2 frequency divider 33 ₄ of the fifth division clock signal _{CLK-X 4} in which the fourth frequency-divided clock signal _{CLK-X 3} divided by 2, and outputs to the selection circuit 32.

The frequency dividing circuit 31 corresponds to the clock signal output circuit.

Selection circuit 32 includes a selector 34 _1. The selector 34 _1, the first divided clock signal _{CLK-X 0} to the fifth division clock signal _{CLK-X 4} is supplied. The selector 34 _1, based on the control signal Sig ₆ is supplied from the timing controller 4b, 1 single divided clock of the from the first divided clock signal _{CLK-X 0} to the fifth division clock signal _{CLK-X 4} The signal is selected as the selection clock signal CLK-SEL. The selector ₃₄₁ outputs the selected clock signal CLK-SEL, the memory selection circuit 8.

In the first embodiment, the frequency divider circuit 31 includes the 1/2 frequency divider 33, but the present disclosure is not limited to this. The frequency divider circuit 31 may include a 1/3 divider or a 1/4 divider. Further, in the first embodiment, the frequency divider circuit 31 includes four 1/2 frequency dividers 33, but the present disclosure is not limited to this. The frequency divider circuit 31 may include three or less or five or more frequency dividers and output three or less or five or more frequency divider clock signals to the selection circuit 32. In the first embodiment, the frequency dividing circuit 31 is connected in a daisy chain, it was to contain the first 1/2 frequency divider 33 ₁ to the fourth 1/2 frequency divider 33 ₄ However, this disclosure is not limited to this. The creation of a plurality of divided clock signals can be realized by various circuit configurations.

Further, in the first embodiment, the display device 1 is provided with the frequency dividing circuit 31 as the clock signal output circuit, but the present disclosure is not limited to this. The display device 1 may include, instead of the frequency dividing circuit 31, a multiplication circuit as a clock signal output circuit, which outputs a plurality of multiplication clock signals obtained by multiplying the reference clock signal CLK by a plurality of multiplication ratios to the selection circuit 32. good. In this case, the multiplication circuit corresponds to the clock signal output circuit.

FIG. 5 is a diagram showing a waveform of a frequency-divided clock signal of the display device of the first embodiment.

The frequency of the reference clock signal CLK is N hertz (N is a positive number). The frequency of the first divided clock signal CLK-X ₀ is N hertz, which is the same as the frequency of the reference clock signal CLK.

The first 1/2 frequency divider 33 ₁ outputs the second divided clock signal _{CLK-X 1} in which the first divided clock signal _{CLK-X 0} divided by 2. The frequency of the second divided clock signal CLK-X ₁ is N / 2 hertz, which is ½ of the frequency of the first divided clock signal CLK-X _0. The second divided clock signal CLK-X ₁ rises _{at the timing t 0} , which is the falling edge of the first divided clock signal CLK-X _0. In the first embodiment, the second divided clock signal CLK-X ₁ rises at the falling edge of the first divided clock signal CLK-X ₀ , but the present disclosure is not limited to this. The second divided clock signal CLK-X ₁ may rise at the rising edge of the first divided clock signal CLK-X _0. The third divided clock signal CLK-X ₂ , the fourth divided clock signal CLK-X ₃ and the fifth divided clock signal CLK-X ₄ described below are also the same as the second divided clock signal CLK-X _1. Is.

₂ second 1/2 frequency divider 33 outputs a third frequency-divided clock signal _{CLK-X 2} in which the second frequency-divided clock signal _{CLK-X 1} divided by 2. The frequency of the third divided clock signal CLK-X ₂ is N / 4 hertz, which is ½ of the frequency of the second divided clock signal CLK-X _1. The third divided clock signal CLK-X ₂ rises _{at the timing t 1} , which is the falling edge of the second divided clock signal CLK-X _1.

The third 1/2 frequency divider 33 ₃ outputs the fourth frequency-divided clock signal _{CLK-X 3} in which the third frequency-divided clock signal _{CLK-X 2} divided by 2. The frequency of the fourth divided clock signal CLK-X ₃ is N / 8 hertz, which is ½ of the frequency of the third divided clock signal CLK-X _2. The fourth divided clock signal CLK-X ₃ rises _{at the timing t 2} which is the falling edge of the third divided clock signal CLK-X _2.

The fourth 1/2 frequency divider 33 ₄ outputs the fifth division clock signal _{CLK-X 4} in which the fourth frequency-divided clock signal _{CLK-X 3} divided by 2. The frequency of the fifth divided clock signal CLK-X ₄ is N / 16 hertz, which is ½ of the frequency of the fourth divided clock signal CLK-X _3. The fifth divided clock signal CLK-X ₄ rises _{at the timing t 3} which is the falling edge of the fourth divided clock signal CLK-X _3.

FIG. 6 is a diagram showing a module configuration of the display device of the first embodiment. In detail, FIG. 6 is a diagram showing the arrangement of the frequency dividing circuit 31 and the selection circuit 32 in the display device 1. The frequency dividing circuit 31 and the selection circuit 32 are arranged in a portion of the frame region GD where the first panel 2 does not overlap with the second panel 3. A flexible substrate F is attached to the first panel 2. The reference clock signal CLK is supplied to the frequency dividing circuit 31 via the flexible substrate F. The reference clock signal CLK is also supplied to the common electrode drive circuit 6 (see FIG. 1) and the inverting drive circuit 7 (see FIG. 1).

The frequency dividing circuit 31 outputs from the first divided clock signal CLK-X ₀ obtained by dividing the reference clock signal CLK to the fifth divided clock signal CLK-X ₄ to the selection circuit 32. The selection circuit 32 selects _{one of the first divided clock signal CLK-X 0} to the fifth divided clock signal CLK-X ₄ as the selected clock signal CLK-SEL. The selection circuit 32 outputs the selection clock signal CLK-SEL to the memory selection circuit 8 (see FIG. 1).

The frequency dividing circuit 31 and the selection circuit 32 may be mounted on the first panel 2 as COG (Chip On Glass). Further, the frequency dividing circuit 31 and the selection circuit 32 may be mounted on the flexible substrate F as a COF (Chip On Film).

FIG. 7 is a diagram showing a circuit configuration of the display device of the first embodiment. FIG. 7 shows 2 × 2 sub-pixel SPix in each sub-pixel SPix.

The sub-pixel SPix includes a liquid crystal LQ, a holding capacity C, and a sub-pixel electrode 15 (see FIG. 2) in addition to the memory block 50 and the inverting switch 61.

The common electrode drive circuit 6 changes the common potential VCOM common to each sub-pixel SPix in synchronization with the reference clock signal CLK in the same phase, and outputs the common potential VCOM to the common electrode 23 (see FIG. 2). The common electrode drive circuit 6 may output the reference clock signal CLK to the common electrode 23 as it is as a common potential VCOM, or outputs the reference clock signal CLK to the common electrode 23 as a common potential VCOM via a buffer circuit that amplifies the current drive capability. Is also good.

The gate line drive circuit 9 has M output terminals corresponding to the pixel Pix in the M row. The gate line drive circuit 9 sequentially outputs a gate signal for selecting one of the M rows from the M output terminals based on the _{control signal Sig 4 supplied from the timing controller 4b.}

The gate line drive circuit 9 may be a scanner circuit that sequentially outputs gate signals from M output terminals based on _{the control signal Sig 4 (scan start signal and clock pulse signal).} Alternatively, the gate line drive circuit 9 may be _{a decoder circuit that decodes the coded control signal Sig 4} and outputs the gate signal to the output terminal designated by the control signal Sig _4.

The gate line selection circuit 10, corresponding to the pixel Pix of M rows, including M switches _{SW 4_1, SW 4_2,} a .... M switches _{SW 4_1, SW 4_2,} ··· it is commonly controlled by the control signal Sig ₅ supplied from the timing controller 4b.

On the first panel 2, the gate line groups GL ₁ , GL ₂ , ... Of the M group are arranged corresponding to the pixel Pix in the M row. Each of the gate line groups GL ₁ , GL _{2 , ... Of the M group has a first gate line GCL a} electrically connected to the first memory 51 (see FIG. 3) of the row and a second memory 52. It includes a second gate line GCL _b electrically connected to (see FIG. 3) and a third gate line GCL _c electrically connected to a third memory 53 (see FIG. 3). Each of the gate line groups GL ₁ , GL ₂ , ... Of the M group is along the X direction in the display area DA (see FIG. 1).

M switches _{SW 4_1, SW 4_2,} each ..., when the control signal Sig ₅ of the first value, and an output terminal of the gate line driving circuit 9, a first gate line GCL _a, a Connect electrically. M switches _{SW 4_1, SW 4_2,} each ..., when the control signal Sig ₅ of the second value, the output terminal of the gate line driving circuit 9, and the second gate line GCL _b, the Connect electrically. M switches _{SW 4_1, SW 4_2,} each ..., when the control signal Sig ₅ of the third value, and an output terminal of the gate line driving circuit 9, and a third gate line GCL _c, a Connect electrically.

When the output terminal of the gate line drive circuit 9 and the first gate line GCL _a are electrically connected, a gate signal is supplied to the first memory 51 of each sub-pixel SPix. When the output terminal of the gate line drive circuit 9 and the second gate line GCL _b are electrically connected, a gate signal is supplied to the second memory 52 of each sub-pixel SPix. When the output terminal of the gate line drive circuit 9 and the third gate line GCL _c are electrically connected, a gate signal is supplied to the third memory 53 of each sub-pixel SPix.

On the first panel 2, N × 3 source lines SGL ₁ , SGL ₂ , ... Corresponding to N × 3 rows of sub-pixel SPix are arranged. Each of the source lines SGL ₁ , SGL ₂ , ... Is along the Y direction in the display area DA (see FIG. 1). The source line drive circuit 5 outputs sub-pixel data to each of the three memories of each sub-pixel SPix selected by the gate signal _{via the source lines SGL 1} , SGL _{2, ....}

The sub-pixel SPix in the row to which the gate signal is supplied transfers the sub-pixel data supplied to the source line SGL according to the gate line GCL to which the gate signal is supplied from the first memory 51 to the third memory 53. Store in one of the memories.

The memory selection circuit 8 includes a switch SW ₂ , a latch 71, and a switch SW ₃ . The switch SW ₂ is controlled by the control signal Sig ₂ supplied from the timing controller 4b.

A case of displaying an image, that is, a case of reading image data from any one of M × N × 3 first memory 51, second memory 52, and third memory 53 will be described. In this case, the timing controller 4b outputs the control signal Sig ₂ having the first value to the switch SW ₂ . The switch SW ₂ is turned on based on _{the control signal Sig 2} having the first value supplied from the timing controller 4b. As a result, the selection clock signal CLK-SEL is supplied to the latch 71.

A case where the image is not displayed, that is, a case where the image data is not read from any of the M × N × 3 first memory 51, the second memory 52, and the third memory 53 will be described. In this case, the timing controller 4b outputs the control signal Sig ₂ having a second value to the switch SW ₂ . The switch SW ₂ is turned off based on _{the control signal Sig 2} having a second value supplied from the timing controller 4b. As a result, the selection clock signal CLK-SEL is not supplied to the latch 71.

_{When the selection clock signal CLK-SEL is supplied while the switch SW 2} is on, the latch 71 holds the high level of the selection clock signal CLK-SEL for the time of one cycle of the selection clock signal CLK-SEL. do. The latch 71 _{holds a high level when the switch SW 2} is off and the selection clock signal CLK-SEL is not supplied.

On the first panel 2, memory selection line groups SL ₁ , SL ₂ , ... Of the M group are arranged corresponding to the pixel Pix in the M row. Each of the memory selection line groups SL ₁ , SL ₂ , ... Of the M group is electrically connected to the first memory selection line SEL _a electrically connected to the first memory 51 of the row and the second memory 52. The second memory selection line SEL _b connected to the third memory 53 and the third memory selection line SEL _c electrically connected to the third memory 53 are included. Each of the memory selection line groups SL ₁ , SL ₂ , ... Of the M group is along the X direction in the display area DA (see FIG. 1).

The switch SW ₃ is controlled by the control signal Sig ₃ supplied from the timing controller 4b. When the control signal Sig ₃ has the first value, the switch SW ₃ has the output terminal of the latch 71 and the first memory selection line of each of the memory selection lines _{SL 1} , SL _{2, ... Of the M group.} Electrically connect to SEL _a. When the control signal Sig ₃ has a second value, the switch SW ₃ has the output terminal of the latch 71 and the second memory selection line of each of the memory selection lines _{SL 1} , SL _{2, ... Of the M group.} The SEL _b and the SEL b are electrically connected. When the control signal Sig ₃ has a third value, the switch SW ₃ has the output terminal of the latch 71 and the third memory selection line of each of the memory selection lines _{SL 1} , SL _{2, ... Of the M group.} Electrically connect to SEL _c.

Each sub-pixel SPix is a liquid crystal display based on the sub-pixel data stored in one of the memories from the first memory 51 to the third memory 53 according to the memory selection line SEL to which the memory selection signal is supplied. Modulate layers. As a result, an image (frame) is displayed on the display surface.

On the first panel 2, M display signal lines FRP ₁ , FRP ₂ , ... Corresponding to the pixel Pix of the M line are arranged. Each of the M display signal lines FRP ₁ , FRP ₂ , ... Is along the X direction in the display area DA (see FIG. 1). When the inverting switch 61 operates with an inverted display signal in which the display signal is inverted in addition to the display signal, a first display signal line FRP and a second display signal line xFRP are provided for each line. ..

One or two display signal lines arranged per line correspond to the display signal lines.

The inverting drive circuit 7 includes a switch SW ₁ . The switch SW ₁ is controlled by the control signal Sig ₁ supplied from the timing controller 4b. When the control signal Sig ₁ has the first value, the switch SW ₁ supplies the reference clock signal CLK to each display signal line FRP ₁ , FRP ₂ , .... As a result, the potential of the sub-pixel electrode 15 is inverted in synchronization with the reference clock signal CLK. When the control signal Sig ₁ has a second value, the switch SW ₁ supplies a reference potential (ground potential) GND to each display signal line FRP ₁ , FRP ₂ , ....

FIG. 8 is a diagram showing a circuit configuration of sub-pixels of the display device of the first embodiment. FIG. 8 shows one sub-pixel SPix.

The sub-pixel SPix includes the memory block 50. The memory block 50 includes a first memory 51, a second memory 52, a third memory 53, switches Gsw ₁ to Gsw ₃ , and switches Msw ₁ to Msw ₃ .

The control input terminal of the switch Gsw ₁ is electrically connected to _{the first gate line GCL a.} The switch Gsw _{1 is turned on when a} high-level gate signal is supplied to the first gate line GCL _{a, and electrically connects the source line SGL 1} and the input terminal of the first memory 51. As a result, the sub-pixel data supplied to the _{source line SGL 1 is stored in the first memory 51.}

The control input terminal of the switch Gsw ₂ is electrically connected to _{the second gate line GCL b.} The switch Gsw ₂ is turned on when a high-level gate signal is supplied to the second gate line GCL _{b , and electrically connects the source line SGL 1} and the input terminal of the second memory 52. As a result, the sub-pixel data supplied to the _{source line SGL 1 is stored in the second memory 52.}

The control input terminal of the switch Gsw ₃ is electrically connected to _{the third gate line GCL c.} The switch Gsw ₃ is turned on when a high-level gate signal is supplied to the third gate line GCL _{c , and electrically connects the source line SGL 1} and the input terminal of the third memory 53. As a result, the sub-pixel data supplied to the _{source line SGL 1 is stored in the third memory 53.}

When the switches Gsw ₁ to Gsw ₃ operate with a high-level gate signal, as shown in FIG. 8, the gate line group GL ₁ is from the first gate line GCL _a to the third gate line GCL _c. including. Switches operating with high-level gate signals are exemplified by N-channel transistors, but the present disclosure is not limited thereto.

On the other hand, when the switches Gsw ₁ to Gsw ₃ operate with the inverted gate signal in which the gate signal is inverted in addition to the gate signal, the gate line group GL ₁ has the first gate line GCL _a to the third gate. In addition to the line GCL _{c, the fourth gate line xGCL a} to the sixth gate line xGCL _c to which the inverted gate signal is supplied is further included. The switch operated by the gate signal and the inverting gate signal is exemplified by a transfer gate, but the present disclosure is not limited thereto.

Input terminal is electrically connected to the first gate line GCL _a, an output terminal by providing the inverter circuit electrically connected to the fourth gate line xGCL _a, the inverted gate signal to the fourth gate line XGCL _a It is possible to supply. Similarly, by providing an inverter circuit in which the input terminal is electrically connected to the second gate line GCL _b and the output terminal is electrically connected to the fifth gate line x GCL _b , the inverted gate signal is transmitted to the fifth gate line. It is possible to supply xGCL _b. Similarly, by providing an inverter circuit in which the input terminal is electrically connected to the third gate line GCL _c and the output terminal is electrically connected to the sixth gate line x GCL _c , the inverted gate signal is transmitted to the sixth gate line. It is possible to supply to xGCL _c.

The control input terminal of the switch Msw ₁ is electrically connected to _{the first memory selection line SEL a.} The switch Msw _{1 is turned on when a} high-level memory selection signal is supplied to the first memory selection line SEL a, and is electrically connected between the output terminal of the first memory 51 and the input terminal of the inverting switch 61. Connect to. As a result, the sub-pixel data stored in the first memory 51 is supplied to the inverting switch 61.

The control input terminal of the switch Msw ₂ is electrically connected to _{the second memory selection line SEL b.} The switch Msw ₂ is turned on when a high-level memory selection signal is supplied to the second memory selection line SEL _b , and is electrically connected between the output terminal of the second memory 52 and the input terminal of the inverting switch 61. Connect to. As a result, the sub-pixel data stored in the second memory 52 is supplied to the inverting switch 61.

The control input terminal of the switch Msw ₃ is electrically connected to _{the third memory selection line SEL c.} The switch Msw ₃ is turned on when a high-level memory selection signal is supplied to the third memory selection line SEL _c , and is electrically connected between the output terminal of the third memory 53 and the input terminal of the inverting switch 61. Connect to. As a result, the sub-pixel data stored in the third memory 53 is supplied to the inverting switch 61.

When switches Msw ₁ to Msw ₃ operate with high-level memory selection signals, as shown in FIG. 8, the memory selection line group SL ₁ selects the third memory from the first memory selection line SEL _a. Includes up to line SEL _c. Switches operating with high-level gate signals are exemplified by N-channel transistors, but the present disclosure is not limited thereto.

On the other hand, when the switches Msw ₁ to Msw ₃ operate with the inverted memory selection signal in which the memory selection signal is inverted in addition to the memory selection signal, the memory selection line group SL ₁ is the first memory selection line SEL. _{In addition to a} to the third memory selection line SEL _c , the fourth memory selection line xSEL _a to the sixth memory selection line xSEL _c to which the inverted memory selection signal is supplied is further included. The switch operated by the memory selection signal and the inverting memory selection signal is exemplified by a transfer gate, but the present disclosure is not limited thereto.

By providing an inverter circuit in which the input terminal is electrically connected to the first memory selection line SEL _a and the output terminal is electrically connected to the fourth memory selection line x SEL _a , the inverting memory selection signal is selected by the fourth memory. It is possible to supply the line xSEL _a. Similarly, by providing an inverter circuit in which the input terminal is electrically connected to the second memory selection line SEL _b and the output terminal is electrically connected to the fifth memory selection line x SEL _b , the inverting memory selection signal is transmitted. 5 It is possible to supply to the memory selection line xSEL _b. Similarly, by providing an inverter circuit in which the input terminal is electrically connected to the third memory selection line SEL _c and the output terminal is electrically connected to the sixth memory selection line x SEL _c , the inverting memory selection signal is transmitted. 6 It is possible to supply to the memory selection line xSEL _c.

A display signal that is synchronized with the reference clock signal CLK and changes in phase is supplied to the _{inverting switch 61 from the first display signal line FRP 1.} Further, an inverted display signal that is synchronized with the reference clock signal CLK and changes in the opposite phase is supplied to _{the inverted switch 61 from the second display signal line xFRP 1.} The inverting switch 61 feeds the sub-pixel data stored in the first memory 51, the second memory 52, or the third memory 53 as it is or inverts it to the sub-pixel electrode 15 based on the display signal and the inverting display signal. do. A liquid crystal LQ and a holding capacity C are provided between the sub-pixel electrode 15 and the common electrode 23. The holding capacitance C holds the voltage between the sub-pixel electrode 15 and the common electrode 23. The liquid crystal LQ changes the direction of the molecule based on the voltage between the sub-pixel electrode 15 and the common electrode 23, and displays the sub-pixel image. A configuration without a holding capacity C can also be adopted.

When the inverting switch 61 operates on the display signal, the first display signal line FRP ₁ is provided. On the other hand, when the inverting switch 61 operates with an inverted display signal in which the display signal is inverted in addition to the display signal, a second display signal line xFRP ₁ is further provided _{in addition to the first display signal line FRP 1.} Be done. Then, by providing an inverter circuit in which the input terminal is electrically connected to the first display signal line FRP ₁ and the output terminal is electrically connected to the second display signal line xFRP ₁ , the inverted display signal is displayed second. It is possible to supply the signal line xFRP _1.

FIG. 9 is a diagram showing a circuit configuration of a memory of a sub-pixel of the display device of the first embodiment. FIG. 9 is a diagram showing a circuit configuration of the first memory 51. Since the circuit configurations of the second memory 52 and the third memory 53 are the same as the circuit configurations of the first memory 51, illustration and description thereof will be omitted.

The first memory 51 has a SRAM (Static Random Access Memory) cell structure including an inverter circuit 81 and an inverter circuit 82 electrically connected in parallel to the inverter circuit 81 in the opposite direction. The input terminal of the inverter circuit 81 and the output terminal of the inverter circuit 82 constitute the node N1, and the output terminal of the inverter circuit 81 and the input terminal of the inverter circuit 82 constitute the node N2. The inverter circuits 81 and 82 operate using the power supplied from the power supply line VDD on the high potential side and the power supply line VSS on the low potential side.

Node N1 is electrically connected to the output terminal of the switch gsw _1. Node N2 is electrically connected to the input terminal of the switch Msw _1.

FIG. 9 shows an example in which a transfer gate is used as _{the switch Gsw 1. One} of the control input terminals of the switch Gsw 1 is electrically connected to _{the first gate line GCL a.} The other control input terminal of the switch Gsw ₁ is electrically connected to _{the fourth gate line x GCL a.} An inverted gate signal obtained by inverting the gate signal supplied to the first gate line GCL _a is supplied to the fourth gate line xGCL _a.

The input terminal of the switch Gsw ₁ is electrically connected to _{the source line SGL 1.} The output terminal of the switch Gsw ₁ is electrically connected to the node N1. Switch gsw ₁ is the inverted gate signal gate signal supplied to the first gate line GCL _a is supplied to the high level and the fourth gate line XGCL _a becomes low level, turned on, and the source line SGL ₁ , And the node N1 are electrically connected. As a result, the _{sub-pixel data supplied to the source line SGL 1} is stored in the first memory 51.

FIG. 9 shows an example in which a transfer gate is used as _{the switch Msw 1. One} of the control input terminals of the switch Msw 1 is electrically connected to _{the first memory selection line SEL a.} The other control input terminal of the switch Msw ₁ is electrically connected to _{the fourth memory selection line xSEL a.} An inverted memory selection signal obtained by inverting the memory selection signal supplied to the first memory selection line SEL _a is supplied to the fourth memory selection line xSEL _a.

The input terminal of the switch Msw ₁ is electrically connected to the node N2. The output terminal of the switch Msw ₁ is connected to the node N3. The node N3 is an output node of the first memory 51 and is electrically connected to the inverting switch 61 (see FIG. 8). The switch Msw ₁ is turned on when the memory selection signal supplied to the first memory selection line SEL _a becomes high level and the inverting memory selection signal supplied to _{the fourth memory selection line xSEL a becomes low level.} As a result, the node N2 is electrically connected to the input terminal of the inverting switch 61 via the _{switch Msw 1 and the node N3.} As a result, the sub-pixel data stored in the first memory 51 is supplied to the inverting switch 61.

When both the switches Gsw ₁ and Msw ₁ are in the off state, the sub-pixel data circulates in the loop composed of the inverter circuits 81 and 82. Therefore, the first memory 51 continues to hold the sub-pixel data.

In the first embodiment, the case where the first memory 51 is an SRAM has been described as an example, but the present disclosure is not limited to this. Another example of the first memory 51 is a DRAM (Dynamic Random Access Memory).

FIG. 10 is a diagram showing a circuit configuration of an inverting switch for sub-pixels of the display device of the first embodiment. The inverting switch 61 includes an inverter circuit 91, N-channel transistors 92 and 95, and P-channel transistors 93 and 94.

The input terminal of the inverter circuit 91, the gate terminal of the P channel transistor 94, and the gate terminal of the N channel transistor 95 are connected to the node N4. The node N4 is an input node of the inverting switch 61, and is electrically connected to the node N3 of the first memory 51, the second memory 52, and the third memory 53. Sub-pixel data is supplied to the node N4 from the first memory 51, the second memory 52, or the third memory 53. The inverter circuit 91 operates using the power supplied from the power supply line VDD on the high potential side and the power supply line VSS on the low potential side.

One of the source and drain of the N-channel transistor 92 is electrically connected to _{the second display signal line xFRP 1.} The other of the sources and drains of the N-channel transistor 92 is electrically connected to the node N5.

One of the source and drain of the P channel transistor 93 is electrically connected to _{the first display signal line FRP 1.} The other of the source and drain of the P-channel transistor 93 is electrically connected to the node N5.

One of the source and drain of the P channel transistor 94 is electrically connected to _{the second display signal line xFRP 1.} The other of the source and drain of the P-channel transistor 94 is electrically connected to the node N5.

One of the source and drain of the N-channel transistor 95 is electrically connected to _{the first display signal line FRP 1.} The other of the sources and drains of the N-channel transistor 95 is electrically connected to the node N5.

The node N5 is an output node of the inverting switch 61 and is electrically connected to the reflecting electrode (sub-pixel electrode) 15.

When the sub-pixel data supplied from the first memory 51, the second memory 52, or the third memory 53 is at a high level, the output signal of the inverter circuit 91 becomes a low level. When the output signal of the inverter circuit 91 is low level, the N-channel transistor 92 is turned off and the P-channel transistor 93 is turned on.

When the sub-pixel data supplied from the first memory 51, the second memory 52, or the third memory 53 is at a high level, the P-channel transistor 94 is turned off and the N-channel transistor 95 is turned on. Become.

Therefore, when the sub-pixel data supplied from the first memory 51, the second memory 52, or the third memory 53 is at a high level, the display signal _{supplied to the first display signal line FRP 1} is the P channel transistor. It is supplied to the sub-pixel electrode 15 via the 93 and the N-channel transistor 95.

The display signal supplied to the first display signal line FRP ₁ changes synchronously and in phase with the reference clock signal CLK. The common potential supplied to the common electrode 23 also changes in phase with the reference clock signal CLK. When the display signal and the common potential are in phase, no voltage is applied to the liquid crystal LQ, so that the direction of the molecule does not change. As a result, the sub-pixels are displayed in black (a state in which the reflected light is not transmitted. A state in which the reflected light does not pass through the color filter and the color is not displayed). Thereby, the display device 1 can realize the common inversion drive system.

When the sub-pixel data supplied from the first memory 51, the second memory 52, or the third memory 53 is at a low level, the output signal of the inverter circuit 91 becomes a high level. When the output signal of the inverter circuit 91 is at a high level, the N-channel transistor 92 is turned on and the P-channel transistor 93 is turned off.

When the sub-pixel data supplied from the first memory 51, the second memory 52, or the third memory 53 is at a low level, the P-channel transistor 94 is turned on and the N-channel transistor 95 is turned off. Become.

Therefore, when the sub-pixel data supplied from the first memory 51, the second memory 52, or the third memory 53 is at a low level, the inverted display signal supplied to _{the second display signal line xFRP 1 is N channel.} It is supplied to the sub-pixel electrode 15 via the transistor 92 and the P-channel transistor 94.

The inverted display signal supplied to the second display signal line xFRP ₁ changes in synchronization with the reference clock signal CLK and in the opposite phase. The common potential supplied to the common electrode 23 changes synchronously and in phase with the reference clock signal CLK. When the inverted display signal and the common potential are out of phase, a voltage is applied to the liquid crystal LQ, so that the direction of the molecule changes. As a result, the sub-pixels are displayed in white (a state in which the reflected light is transmitted. A state in which the reflected light is transmitted through the color filter and the color is displayed). Thereby, the display device 1 can realize the common inversion drive system.

FIG. 11 is a diagram showing an outline of the layout of sub-pixels of the display device of the first embodiment.

The inverting switch 61, the first memory 51, the second memory 52, and the third memory 53 are arranged in the Y direction. The node N3, which is the output node of the first memory 51, the second memory 52, and the third memory 53, is electrically connected to the node N4, which is the input node of the inverting switch 61. The node N5, which is the output node of the inverting switch 61, is electrically connected to the sub-pixel electrode 15.

The first memory 51 includes a first gate line GCL _a , a fourth gate line xGCL _a , a first memory selection line SEL _a , a fourth memory selection line xSEL _a , a source line SGL _1, and a high potential side. It is electrically connected to the power supply line VDD and the power supply line VSS on the low potential side.

The second memory 52 includes a second gate line GCL _b , a fifth gate line xGCL _b , a second memory selection line SEL _b , a fifth memory selection line xSEL _b , a source line SGL _1, and a high potential side. It is electrically connected to the power supply line VDD and the power supply line VSS on the low potential side.

The third memory 53 includes a third gate line GCL _c , a sixth gate line xGCL _c , a third memory selection line SEL _c , a sixth memory selection line xSEL _c , a source line SGL _1, and a high potential side. It is electrically connected to the power supply line VDD and the power supply line VSS on the low potential side.

The inverting switch 61 is _{electrically connected to the display signal line FRP 1} , the second display signal line xFRP ₁ , the high potential side power supply line VDD, and the low potential side power supply line VSS.

[First operation example]
FIG. 12 is a timing diagram showing the first operation timing of the display device of the first embodiment.

Throughout FIG. 12, the common electrode drive circuit 6 supplies the common electrode 23 with a common potential that inverts in synchronization with the reference clock signal CLK. The timing controller 4b based on the value of the setting register 4c, the control signal Sig ₆ for selecting the first frequency-divided clock signal _{CLK-X 0,} and outputs to the selector 34 _1. Accordingly, the selector 34 ₁ selects the first frequency-divided clock signal _{CLK-X 0} as selected clock signal CLK-SEL. Therefore, the frequency of the selected clock signal CLK-SEL is the same as the frequency of the reference clock signal CLK. The selector ₃₄₁ outputs the selected clock signal CLK-SEL, the memory selection circuit 8.

The period from the timing t ₁₀ to the timing t ₁₃ is the writing period of the sub pixel data from the first memory 51 to the third memory 53 included in each of the N × 3 sub pixel SPix in one row.

At the timing t ₁₀ , the timing controller 4b outputs the control signal Sig _{5 having the first value to the switch SW 4} in the gate line selection circuit 10. The switch SW ₄ electrically connects the output terminal of the gate line drive circuit 9 and the first gate line GCL _a. The gate line drive circuit 9 outputs a gate signal to the first gate line GCL _a of each line. _{When a} high-level gate signal is supplied to the first gate line GCL a, the first memory 51 of each of the sub-pixel SPix belonging to the line is selected as the write destination of the sub-pixel data.

Further, at the timing t ₁₀ , the source line drive circuit 5 outputs sub-pixel data for displaying the image (frame) “A” to the source line SGL. As a result, the sub-pixel data for displaying the image "A" is written in the first memory 51 of each of the sub-pixel SPix belonging to each line.

Further, over the time t ₁₀ to t _11, this operation is performed by the line sequential from the first row to the M line. As a result, the signal for forming the image "A" is written and stored in the first memory 51 of all the sub-pixel SPix.

Further, from the timing t ₁₁ to t ₁₂ , the same operation as described above is _{performed in relation to the second gate line GCL b} and the image “B”. As a result, a signal for forming the image "B" is written and stored in the second memory 52 of all the sub-pixel SPix.

Further, from the timing t ₁₂ to t ₁₃ , the same operation as described above is _{performed in relation to the third gate line GCL c} and the image “C”. As a result, a signal for forming the image "C" is written and stored in the third memory 53 of all the sub-pixel SPix.

The period from timing t ₁₄ to timing t ₂₀ is an animation display (moving image display) period in which three images (three frames) of "A", "B", and "C" are sequentially switched and displayed.

At the timing t ₁₄ , the timing controller 4b outputs the control signal Sig _{2 having the first value to the switch SW 2} in the memory selection circuit 8. The switch SW ₂ is turned on based on _{the control signal Sig 2} having the first value supplied from the timing controller 4b. As a result, the selection clock signal CLK-SEL is supplied to the latch 71.

Further, at the timing t ₁₄ , the timing controller 4b outputs the control signal Sig _{3 having the first value to the switch SW 3} in the memory selection circuit 8. The switch SW ₃ electrically connects the output terminal of the latch 71 and the first memory selection line SEL _{a of each of the memory selection line groups SL 1} , SL _{2, ... Of the M group.} As a result, the memory selection signal is supplied to the first memory selection line SEL _{a of each of the memory selection line groups SL 1} , SL _{2, ... Of the M group.}

Each first memory 51 connected to each first memory selection line SEL _a outputs sub-pixel data for displaying the image "A" to the inversion switch 61. As a result, at the timing t ₁₄ , the display device 1 displays the image “A”.

By the same operation, the image B _{is selected and displayed at the timing t 15} to the timing t ₁₆ , and the image C is selected and displayed at _{the timing t 16} to the timing t _17.

Since the operation of each part from timing t ₁₇ to timing t ₁₉ is the same as the operation of each part from timing t _{14 to timing t 16} , the description thereof will be omitted.

As described above, the display device 1 sequentially switches and displays three images (three frames) of "A", "B", and "C" in the period _{from timing t 14} to timing t _20. (Video display) can be performed.

The period from the timing t ₂₀ to the timing t ₂₂ is a still image display period for displaying the image "A".

At the timing t ₂₀ , the timing controller 4b outputs the control signal Sig _{2 having a second value to the switch SW 2} in the memory selection circuit 8. The switch SW ₂ is turned off based on _{the control signal Sig 2} having a second value supplied from the timing controller 4b. As a result, the selection clock signal CLK-SEL is not supplied to the latch 71. The latch 71 holds a high level.

Further, at the timing t ₂₀ , the timing controller 4b outputs the control signal Sig _{3 having the first value to the switch SW 3} in the memory selection circuit 8. The switch SW ₃ electrically connects the output terminal of the latch 71 and the first memory selection line SEL _{a of each of the memory selection line groups SL 1} , SL _{2, ... Of the M group.} By the same drive as described above, the display device 1 displays the image "A" as a still image _{from the timing t 20} to the timing t _22.

In order to display the image (frame) of "X" in the second memory 52 included in each sub-pixel SPix at _{the timing t 21} within the still image display period in which the image of "A" is displayed. Sub-pixel data can be written.

At the timing t ₂₁ , the timing controller 4b outputs the control signal Sig _{5 having a second value to the switch SW 4} in the gate line selection circuit 10. The switch SW ₄ electrically connects the output terminal of the gate line drive circuit 9 and the second gate line GCL _b. The gate line drive circuit 9 outputs a gate signal to the second gate line GCL _b of each line. When a high-level gate signal is supplied to the second gate line GCL _b , the second memory 52 of each of the sub-pixel SPix belonging to the line is selected as the write destination of the sub-pixel data.

Further, at the timing t ₂₁ , the source line drive circuit 5 outputs the sub-pixel data for displaying the image “X” to the source line SGL. As a result, the sub-pixel data for displaying the image "X" is written in the second memory 52 of each sub-pixel SPix belonging to each line.

The display device 1 writes the sub-pixel data for displaying the image (frame) "X" in the second memory 52 included in each sub-pixel SPix by repeating the same operation as the _{timing t 21 M times.} be able to.

In FIG. 12, the image "X" is displayed in the second memory 52 included in each sub-pixel SPix at _{the timing t 21} within the still image display period in which the image "A" is displayed. The case of writing the sub-pixel data for the purpose has been described. However, for example, during the animation display (moving image display) period, from the timing t _{16 to the timing t 18} when the images "C" and "A" are displayed in animation (moving image display), each sub-pixel SPix is displayed. It is also possible to write sub-pixel data for displaying the image "X" in the included second memory 52.

The timing t ₂₂ or later is an animation display (moving image display) period in which three images (three frames) of “X”, “C”, and “A” are sequentially switched and displayed. Since the operation of each part from the timing t ₂₂ to the timing t ₃₀ is the same as the operation of each part _{from the timing t 14} to the timing t ₁₆ , the description thereof will be omitted.

[Second operation example]
FIG. 13 is a timing diagram showing a second operation timing of the display device of the first embodiment.

Throughout FIG. 13, the common electrode drive circuit 6 supplies the common electrode 23 with a common potential that inverts in synchronization with the reference clock signal CLK. The timing controller 4b based on the value of the setting register 4c, the control signal Sig ₆ for selecting a third frequency-divided clock signal _{CLK-X 2,} and outputs to the selector 34 _1. Accordingly, the selector 34 ₁ selects the third frequency-divided clock signal _{CLK-X 2} as the selected clock signal CLK-SEL. Therefore, the frequency of the selected clock signal CLK-SEL is 1/4 of the frequency of the reference clock signal CLK. The selector ₃₄₁ outputs the selected clock signal CLK-SEL, the memory selection circuit 8.

For example, the frequency of the reference clock signal CLK is exemplified by 1 Hz. Therefore, the frequency at which the common potential of the common electrode 23 is inverted is 1 Hz. The frequency of the selected clock signal CLK-SEL is 0.25 Hz, which is 1/4 of the frequency of the reference clock signal CLK. Therefore, the frequency at which the frame changes is 0.25 Hz.

The period from timing t ₄₀ to timing t ₄₃ is an animation display (moving image display) period in which three images (three frames) of "A", "B", and "C" are sequentially switched and displayed.

At the timing t ₄₀ , the timing controller 4b outputs the control signal Sig _{2 having the first value to the switch SW 2} in the memory selection circuit 8. The switch SW ₂ is turned on based on _{the control signal Sig 2} having the first value supplied from the timing controller 4b. As a result, the selection clock signal CLK-SEL is supplied to the latch 71.

Further, at the timing t ₄₀ , the timing controller 4b outputs the control signal Sig _{3 having the first value to the switch SW 3} in the memory selection circuit 8. The switch SW ₃ electrically connects the output terminal of the latch 71 and the first memory selection line SEL _{a of each of the memory selection line groups SL 1} , SL _{2, ... Of the M group.} As a result, the memory selection signal is supplied to the first memory selection line SEL _{a of each of the memory selection line groups SL 1} , SL _{2, ... Of the M group.}

Each first memory 51 connected to each first memory selection line SEL _a outputs sub-pixel data for displaying the image "A" to the inversion switch 61. As a result, at the timing t ₄₀ , the display device 1 displays the image "A".

At the timing t ₄₁ , the same operation as described above is _{performed in relation to the second memory selection line SEL b} and the image “B”. As a result, at the timing t ₄₁ , the display device 1 displays the image "B".

At the timing t ₄₂ , the same operation as described above is _{performed in relation to the third memory selection line SEL c} and the image “C”. As a result, at the timing t ₄₂ , the display device 1 displays the image "C".

Since the operation of each part after the timing t ₄₃ is the same as the operation of each part _{from the timing t 40} to the timing t ₄₂ , the description thereof will be omitted.

As described above, the display device 1 sequentially switches and displays three images (three frames) of "A", "B", and "C" in the period _{from timing t 40} to timing t _43. (Video display) can be performed.

In the display device 1 of the first embodiment, the memory selection circuit 8 provided outside the display area DA simultaneously selects one of the first memory 51 to the third memory 53 of each sub-pixel SPix. Therefore, the display device 1 displays one image (frame) out of the three images (three frames) by switching the selection from the first memory 51 to the third memory 53 of each sub-pixel SPix. Can be done. As a result, the display device 1 can change the images all at once, and can change the images in a short time. Further, the display device 1 can perform animation display (moving image display) by sequentially switching the selection from the first memory 51 to the third memory 53 of each sub-pixel SPix.

Further, in the display device 1 of the first embodiment, when writing the sub-pixel data, the gate line selection circuit 10 arranged in the frame area GD selects any of the first memory 51 to the third memory 53. .. Further, when reading the sub-pixel data, the memory selection circuit 8 arranged in the frame area GD selects any of the first memory 51 to the third memory 53. Therefore, each pixel Pix does not need to include a circuit for switching the memory. As a result, the display device 1 can meet the demand for further miniaturization and higher definition of the image display panel in addition to the above-mentioned effects.

Further, in the display device 1 of the first embodiment, the first is during the period in which the image is displayed based on the sub-pixel data stored in any one of the first memory 51 to the third memory 53. Sub-pixel data can also be written to any one of the other memory 51 to the third memory 53. Thereby, the display device 1 can write the sub-pixel data of another image while displaying the image.

In the display device 1 of the first embodiment, the selector 34 _1, based on the control signal Sig _6, among the first divided clock signal _{CLK-X 0} to the fifth division clock signal _{CLK-X 4} Select one of the above as the selection clock signal CLK-SEL. The selector ₃₄₁ outputs the selected clock signal CLK-SEL, the memory selection circuit 8. As a result, the display device 1 can change the frequency at which the image (frame) is changed without changing the frequency of the reference clock signal CLK supplied from the outside. Further, the display device 1 can make the frequency at which the frame is changed different from the frequency at which the potential of the common electrode 23 is inverted. As a result, the display device 1 can make the frequency at which the frame is changed and the frequency at which the potential of the common electrode 23 is inverted different according to the usage mode without changing the frequency of the reference clock signal CLK. .. Therefore, the display device 1 can make the frequency for changing the frame and the frequency for reversing the polarity of the common electrode 23 different depending on the usage mode.

Further, the display device 1 of the first embodiment can change the frequency at which the frame is changed based on the value of the setting register 4c. Therefore, the display device 1 can change the frequency at which the frame is changed even during the display of the frame by updating the value of the setting register 4c from the external circuit. Therefore, the display device 1 can dynamically change the frequency at which the frame is changed according to the usage mode.

The display device 1 may be used for an electronic shelf label. In electronic shelf labels, there is a demand to dynamically change the frequency at which the frame is changed. The display device 1 can respond to such a request.

In the first embodiment, the reference clock signal CLK is supplied to the common electrode drive circuit 6 and the inverting drive circuit 7, and the selection clock signal CLK-SEL is supplied to the memory selection circuit 8. Is not limited to this. The reference clock signal CLK may be supplied to the memory selection circuit 8, and the selection clock signal CLK-SEL may be supplied to the common electrode drive circuit 6 and the inverting drive circuit 7. Thereby, the display device 1 can make the frequency of changing the frame different from the frequency of inverting the potential of the common electrode 23 according to the usage mode without changing the frequency of the reference clock signal CLK. ..

(Second embodiment)
[overall structure]
FIG. 14 is a diagram showing an outline of the overall configuration of the display device of the second embodiment.

The display device 1A includes a selection circuit 32A instead of the selection circuit 32 of the display device 1 of the first embodiment.

The timing controller 4b controls the selection circuit 32A based on the value set in the setting register 4c.

Under the control of the timing controller 4b, the selection circuit 32A selects _{one of the first divided clock signal CLK-X 0} to the fifth divided clock signal CLK-X ₄ as the first selected clock signal CLK-SEL _1. Select as. Then, the selection circuit 32A outputs the first selection clock signal CLK-SEL ₁ to the memory selection circuit 8. Further, under the control of the timing controller 4b, the selection circuit 32A selects _{one of the first divided clock signal CLK-X 0} to the fifth divided clock signal CLK-X ₄ as the second selected clock signal CLK-. Select as SEL _2. Then, the selection circuit 32A outputs the second selection clock signal CLK-SEL ₂ to the common electrode drive circuit 6 and the inverting drive circuit 7. The frequency of the first selection clock signal CLK-SEL _{1 and} the frequency of the second selection clock signal CLK-SEL ₂ may be the same or different.

FIG. 15 is a diagram showing a circuit configuration of a frequency dividing circuit and a selection circuit of the display device of the second embodiment.

Frequency dividing circuit 31 is connected in a daisy chain, containing from ₁ to first 1/2 frequency divider 33 to the fourth 1/2 frequency divider 33 _4. Selection circuit 32A includes ₁ a first selector 34, ₂ and the second selector 34.

The first selector 34 _1, the first divided clock signal _{CLK-X 0} to the fifth division clock signal _{CLK-X 4} is supplied. The first selector 34 _1, based on the control signal Sig ₆ is supplied from the timing controller 4b, the one of from the first divided clock signal _{CLK-X 0} to the fifth division clock signal _{CLK-X 4} min The peripheral clock signal is selected as the first selection clock signal CLK-SEL ₁ . The first selector 34 _1, a first selected clock signal CLK-SEL _1, and outputs to the memory selection circuit 8.

The ₂ second selector 34, the first divided clock signal _{CLK-X 0} to the fifth division clock signal _{CLK-X 4} is supplied. ₂ The second selector 34, based on the control signal Sig ₇ supplied from the timing controller 4b, the one of from the first divided clock signal _{CLK-X 0} to the fifth division clock signal _{CLK-X 4} min The peripheral clock signal is selected as the second selection clock signal CLK-SEL ₂ . The second selector 34 _2, a second selected clock signal CLK-SEL _2, and outputs to the common electrode driving circuit 6 and the inverted drive circuit 7.

FIG. 16 is a diagram showing a module configuration of the display device of the second embodiment. In detail, FIG. 16 is a diagram showing the arrangement of the frequency dividing circuit 31 and the selection circuit 32A in the display device 1A.

The frequency dividing circuit 31 and the selection circuit 32A are arranged in a portion of the frame region GD where the first panel 2 does not overlap with the second panel 3. A flexible substrate F is attached to the first panel 2. The reference clock signal CLK is supplied to the frequency dividing circuit 31 via the flexible substrate F.

The frequency dividing circuit 31 outputs from the first divided clock signal CLK-X ₀ obtained by dividing the reference clock signal CLK to the fifth divided clock signal CLK-X ₄ to the selection circuit 32A. The selection circuit 32A selects _{one of the first divided clock signal CLK-X 0} to the fifth divided clock signal CLK-X ₄ as the first selected clock signal CLK-SEL ₁ . The selection circuit 32A outputs the first selection clock signal CLK-SEL ₁ to the memory selection circuit 8 (see FIG. 14). The selection circuit 32A selects _{one of the first divided clock signal CLK-X 0} to the fifth divided clock signal CLK-X ₄ as the second selected clock signal CLK-SEL ₂ . The selection circuit 32A outputs the second selection clock signal CLK-SEL ₂ to the common electrode drive circuit 6 (see FIG. 14) and the inverting drive circuit 7 (see FIG. 14).

The frequency dividing circuit 31 and the selection circuit 32A may be mounted on the first panel 2 as a COG. Further, the frequency dividing circuit 31 and the selection circuit 32A may be mounted on the flexible substrate F as a COF.

FIG. 17 is a diagram showing a circuit configuration of the display device of the second embodiment.

The memory selection circuit 8 includes a switch SW ₂ . The switch SW ₂ is controlled by the control signal Sig ₂ supplied from the timing controller 4b.

A case of displaying an image, that is, a case of reading image data from any one of M × N × 3 first memory 51, second memory 52, and third memory 53 will be described. In this case, the timing controller 4b outputs the control signal Sig ₂ having the first value to the switch SW ₂ . The switch SW ₂ is turned on based on _{the control signal Sig 2} having the first value supplied from the timing controller 4b. As a result, the first selection clock signal CLK-SEL ₁ is supplied to the latch 71.

A case where the image is not displayed, that is, a case where the image data is not read from any of the M × N × 3 first memory 51, the second memory 52, and the third memory 53 will be described. In this case, the timing controller 4b outputs the control signal Sig ₂ having a second value to the switch SW ₂ . The switch SW ₂ is turned off based on _{the control signal Sig 2} having a second value supplied from the timing controller 4b. As a result, the first selection clock signal CLK-SEL ₁ is not supplied to the latch 71.

Latch 71, when the switch SW ₂ is first selected clock signal CLK-SEL ₁ is provided in the on state, the first high level of the selected clock signal CLK-SEL _1, first selected clock signal CLK-SEL _{It is} held for the time of one cycle of 1. The latch 71 holds a high level when _{the switch SW 2} is off and the first selection clock signal CLK-SEL _{1 is not supplied.}

The common electrode drive circuit 6 inverts the common potential VCOM common to each sub-pixel SPix _{in synchronization with the second selection clock signal CLK-SEL 2} and outputs it to the common electrode 23 (see FIG. 2). The common electrode drive circuit 6 may output the second selection clock signal CLK-SEL ₂ to the common electrode 23 as it is as a common potential VCOM, or may output the common potential to the common electrode 23 via a buffer circuit that amplifies the current drive capability. It may be output as VCOM.

The inverting drive circuit 7 includes a switch SW ₁ . The switch SW ₁ is controlled by the control signal Sig ₁ supplied from the timing controller 4b. When the control signal Sig ₁ has the first value, the switch SW ₁ supplies the second selection clock signal CLK-SEL ₂ to the display signal lines FRP ₁ , FRP ₂ , .... As a result, the potential of the sub-pixel electrode 15 is inverted in synchronization with the second selection clock signal CLK-SEL _2. When the control signal Sig ₁ has a second value, the switch SW ₁ supplies a reference potential (ground potential) GND to each display signal line FRP ₁ , FRP ₂ , ....

[First operation example]
FIG. 18 is a timing diagram showing the first operation timing of the display device of the second embodiment.

Throughout the 18, the timing controller 4b based on the value of the setting register 4c, the control signal Sig ₆ for selecting the second frequency-divided clock signal _{CLK-X 1,} and outputs to the first selector 34 _1. Accordingly, the first selector 34 _1, the second divided clock signal _{CLK-X 1,} is selected as a first selected clock signal CLK-SEL _1. Therefore, the frequency of the first selection clock signal CLK-SEL ₁ is ½ of the frequency of the reference clock signal CLK. The first selector 34 _1, a first selected clock signal CLK-SEL _1, and outputs to the memory selection circuit 8.

The timing controller 4b based on the value of the setting register 4c, the control signal Sig ₇ for selecting the fourth frequency-divided clock signal _{CLK-X 3,} and outputs to the ₂ second selector 34. Accordingly, the second selector 34 _2, the fourth frequency-divided clock signal _{CLK-X 3,} is selected as the second selected clock signal CLK-SEL _2. Therefore, the frequency of the second selection clock signal CLK-SEL ₂ is 1/8 of the frequency of the reference clock signal CLK. The second selector 34 _2, a second selected clock signal CLK-SEL _2, and outputs to the common electrode driving circuit 6 and the inverted drive circuit 7. The common electrode drive circuit 6 supplies the common electrode 23 with a common potential that inverts in synchronization with the first selection clock signal CLK-SEL _1.

The period from timing t ₅₀ to timing t ₅₄ is an animation display (moving image display) period in which three images (three frames) of "A", "B", and "C" are sequentially switched and displayed.

At timing _{t 50,} the timing controller 4b is a control signal Sig ₂ for the first value, and outputs to the switch SW ₂ in the memory selection circuit 8. The switch SW ₂ is turned on based on _{the control signal Sig 2} having the first value supplied from the timing controller 4b. As a result, the first selection clock signal CLK-SEL ₁ is supplied to the latch 71.

Further, at a timing _{t 50,} the timing controller 4b is a control signal Sig ₃ of the first value, and outputs to the switch SW ₃ in the memory selection circuit 8. The switch SW ₃ electrically connects the output terminal of the latch 71 and the first memory selection line SEL _{a of each of the memory selection line groups SL 1} , SL _{2, ... Of the M group.} As a result, the memory selection signal is supplied to the first memory selection line SEL _{a of each of the memory selection line groups SL 1} , SL _{2, ... Of the M group.}

Each first memory 51 connected to each first memory selection line SEL _a outputs sub-pixel data for displaying the image "A" to the inversion switch 61. Thus, at time _{t 50,} the display device 1A displays the image "A".

At the timing t ₅₁ , the same operation as described above is _{performed in relation to the second memory selection line SEL b} and the image “B”. As a result, at the timing t ₅₁ , the display device 1A displays the image "B".

At timing t ₅₂ , the second selection clock signal CLK-SEL ₂ changes from low level to high level. As a result, the common electrode drive circuit 6 inverts the common potential of the common electrode 23 at the _{timing t 52.}

At the timing t ₅₃ , the same operation as described above is _{performed in relation to the third memory selection line SEL c} and the image “C”. As a result, at the timing t ₅₃ , the display device 1A displays the image "C".

Since the operation of the memory selection circuit 8 after the timing t _{54 is the same as the operation from the timing t 50} to the timing t ₅₄ , the description thereof will be omitted.

At timing t ₅₅ , the second selection clock signal CLK-SEL ₂ changes from low level to high level. As a result, the common electrode drive circuit 6 inverts the common potential of the common electrode 23 at the _{timing t 55.}

Since the operation of the common electrode drive circuit 6 after the timing t _{55 is the same as the operation from the timing t 52} to the timing t ₅₅ , the description thereof will be omitted.

As described above, the display device 1A sequentially switches and displays three images (three frames) of "A", "B", and "C" in the period _{from timing t 50} to timing t _54. (Video display) can be performed.

[Second operation example]
FIG. 19 is a timing diagram showing a second operation timing of the display device of the second embodiment.

Throughout the 19, the timing controller 4b based on the value of the setting register 4c, the control signal Sig ₆ for selecting a third frequency-divided clock signal _{CLK-X 2,} and outputs to the first selector 34 _1. Accordingly, the first selector 34 _1, the third frequency-divided clock signal _{CLK-X 2,} selected as a first selected clock signal CLK-SEL _1. Therefore, the frequency of the first selection clock signal CLK-SEL ₁ is 1/4 of the frequency of the reference clock signal CLK. The first selector 34 _1, a first selected clock signal CLK-SEL _1, and outputs to the memory selection circuit 8.

The timing controller 4b based on the value of the setting register 4c, the control signal Sig ₇ for selecting the first frequency-divided clock signal _{CLK-X 0,} and outputs to the ₂ second selector 34. Accordingly, the second selector 34 _2, the first divided clock signal _{CLK-X 0,} is selected as the second selected clock signal CLK-SEL _2. Therefore, the frequency of the second selection clock signal CLK-SEL ₂ is the same as the frequency of the reference clock signal CLK. The second selector 34 _2, a second selected clock signal CLK-SEL _2, and outputs to the common electrode driving circuit 6 and the inverted drive circuit 7. The common electrode drive circuit 6 supplies the common electrode 23 with a common potential that inverts in synchronization with the first selection clock signal CLK-SEL _1.

For example, the frequency of the reference clock signal CLK and the second selection clock signal CLK-SEL ₂ is exemplified by 1 Hz. Therefore, the frequency at which the common potential of the common electrode 23 is inverted is 1 Hz. The frequency of the first selection clock signal CLK-SEL ₁ is 0.25 Hz, which is 1/4 of the frequency of the reference clock signal CLK. Therefore, the frequency at which the frame changes is 0.25 Hz.

The period from timing t ₆₀ to timing t ₆₄ is an animation display (moving image display) period in which three images (three frames) of "A", "B", and "C" are sequentially switched and displayed.

At timing _{t 60,} the timing controller 4b is a control signal Sig ₂ for the first value, and outputs to the switch SW ₂ in the memory selection circuit 8. The switch SW ₂ is turned on based on _{the control signal Sig 2} having the first value supplied from the timing controller 4b. As a result, the first selection clock signal CLK-SEL ₁ is supplied to the latch 71.

Further, at a timing _{t 60,} the timing controller 4b is a control signal Sig ₃ of the first value, and outputs to the switch SW ₃ in the memory selection circuit 8. The switch SW ₃ electrically connects the output terminal of the latch 71 and the first memory selection line SEL _{a of each of the memory selection line groups SL 1} , SL _{2, ... Of the M group.} As a result, the memory selection signal is supplied to the first memory selection line SEL _{a of each of the memory selection line groups SL 1} , SL _{2, ... Of the M group.}

Each first memory 51 connected to each first memory selection line SEL _a outputs sub-pixel data for displaying the image "A" to the inversion switch 61. Thus, at time _{t 60,} the display device 1A displays the image "A".

At timing _{t 60,} the second selected clock signal CLK-SEL ₂ is changed from the high level to the low level. Thus, the common electrode drive circuit 6, at a timing t _60, reversing the common potential of the common electrode 23.

At timing t ₆₁ , the second selection clock signal CLK-SEL ₂ changes from high level to low level. As a result, the common electrode drive circuit 6 inverts the common potential of the common electrode 23 at the _{timing t 61.}

Since the operation of the common electrode drive circuit 6 after the timing t _{61 is the same as the operation from the timing t 60} to the timing t ₆₁ , the description thereof will be omitted.

At the timing t ₆₂ , the same operation as described above is _{performed in relation to the second memory selection line SEL b} and the image “B”. Thus, at time _{t 62,} the display device 1A displays an image of "B".

At the timing t ₆₃ , the same operation as described above is _{performed in relation to the third memory selection line SEL c} and the image “C”. As a result, at the timing t ₆₃ , the display device 1A displays the image "C".

Since the operation of the memory selection circuit 8 after the timing t _{64 is the same as the operation from the timing t 60} to the timing t ₆₄ , the description thereof will be omitted.

As described above, the display device 1A sequentially switches and displays three images (three frames) of "A", "B", and "C" in the period _{from timing t 60} to timing t _64. (Video display) can be performed.

In the display device 1A of the second embodiment, the first selector 34 _1, controlled based on the signal Sig _6, among the first divided clock signal _{CLK-X 0} to the fifth division clock signal _{CLK-X 4} Is selected as the first selection clock signal CLK-SEL ₁ and output to the memory selection circuit 8. As a result, the display device 1A can change the frequency at which the image (frame) is changed without changing the frequency of the reference clock signal CLK supplied from the outside.

In the display device 1A of the second embodiment, the second selector 34 _2, based on the control signal Sig _7, the first divided clock signal _{CLK-X 0} to the fifth division clock signal _{CLK-X 4} One of the above is selected as the second selection clock signal CLK-SEL ₂ and output to the common electrode drive circuit 6 and the inverting drive circuit 7. As a result, the display device 1A can change the frequency at which the common potential of the common electrode 23 is inverted without changing the frequency of the reference clock signal CLK supplied from the outside.

As a result, the display device 1A can make the frequency at which the frame is changed and the frequency at which the potential of the common electrode 23 is inverted different according to the usage mode without changing the frequency of the reference clock signal CLK. .. Therefore, the display device 1A can make the frequency for changing the frame and the frequency for reversing the polarity of the common electrode 23 different depending on the usage mode.

The liquid crystal element deteriorates when the voltage is continuously applied in the same direction, and the screen of the liquid crystal display device is burned. The common inversion drive is carried out in order to suppress the burn-in of the screen of this liquid crystal display device. When the sub-pixel SPix performs multi-gradation display such as 6 bits, 8 bits, or 10 bits, the deterioration of the liquid crystal element has a great influence on the visual sense of the observer. Therefore, it is necessary to increase the frequency at which the polarity of the common electrode is inverted.

On the other hand, when the sub-pixel SPix performs a 1-bit binary display as in a reflective liquid crystal display device used for an electronic shelf label or the like, the deterioration of the liquid crystal element has a small effect on the observer's vision. .. Therefore, the frequency for reversing the polarity of the common electrode may be low.

In the display device 1A of the second embodiment, the frequency at which the polarity of the common electrode 23 is inverted can be changed according to the usage mode.

Further, the display device 1A of the second embodiment can change the frequency at which the frame is changed and the frequency at which the common potential of the common electrode 23 is inverted based on the value of the setting register 4c. Therefore, the display device 1A can change the frequency for changing the frame and the frequency for reversing the polarity of the common electrode 23 even during the display of the frame by updating the value of the setting register 4c from the external circuit. can. Therefore, the display device 1A can dynamically change the frequency for changing the frame and the frequency for reversing the polarity of the common electrode 23 according to the usage mode.

(Third embodiment)
FIG. 20 is a diagram showing a circuit configuration of the display device of the third embodiment.

The display device of the third embodiment does not include the inverting drive circuit 7 as compared with the display device of the second embodiment (see FIG. 17).

A display signal that changes in phase with the common potential supplied to the common electrode 23 is supplied to the first display signal line FRP from the common electrode drive circuit 6. A common potential supplied to the common electrode 23 is supplied to the inverter 200. An inverted display signal that changes in synchronization with the common potential supplied to the common electrode 23 and in the opposite phase is supplied to the second display signal line xFRP from the inverter 200.

FIG. 21 is a diagram showing a circuit configuration of an inverting switch for sub-pixels of the display device of the third embodiment. The inverting switch 61A includes an N-channel transistor 201 and a P-channel transistor 202.

Sub-pixel data is supplied from the first memory 51, the second memory 52, or the third memory 53 to the gate terminal of the N-channel transistor 201 and the gate terminal of the P-channel transistor 202.

One of the source and drain of the N-channel transistor 201 is electrically connected to _{the second display signal line xFRP 1.} The other of the source and drain of the N-channel transistor 201 is electrically connected to the sub-pixel electrode 15.

One of the source and drain of the P channel transistor 202 is electrically connected to _{the first display signal line FRP 1.} The other of the source and drain of the P-channel transistor 202 is electrically connected to the sub-pixel electrode 15.

When the sub-pixel data supplied from the first memory 51, the second memory 52, or the third memory 53 is at a high level, the N-channel transistor 201 is turned on and the P-channel transistor 202 is turned off. Therefore, the inverted display signal supplied to the second display signal line xFRP ₁ is supplied to the sub-pixel electrode 15 via the N-channel transistor 201.

The inverted display signal supplied to the second display signal line xFRP ₁ changes synchronously and in reverse phase with the common potential supplied to the common electrode 23. When the inverted display signal and the common potential are in different phases, a voltage is applied to the liquid crystal LQ, so that the direction of the liquid crystal molecules changes from the initial orientation state. As a result, the sub-pixel SPix is displayed in white (a state in which the reflected light is transmitted. A state in which the reflected light is transmitted through the color filter and the color is displayed). Thereby, the display device 1A can realize the common inversion drive system.

When the sub-pixel data supplied from the first memory 51, the second memory 52, or the third memory 53 is at a low level, the N-channel transistor 201 is turned off and the P-channel transistor 202 is turned on. Therefore, the display signal supplied to the first display signal line FRP ₁ is supplied to the sub-pixel electrode 15 via the P-channel transistor 202.

The display signal supplied to the first display signal line FRP ₁ changes synchronously and in phase with the common potential supplied to the common electrode 23. When the display signal and the common potential are in phase, no voltage is applied to the liquid crystal LQ, so that the direction of the liquid crystal molecules does not change from the initial orientation state. As a result, the sub-pixel SPix is displayed in black (a state in which the reflected light is not transmitted. A state in which the reflected light does not pass through the color filter and the color is not displayed). Thereby, the display device 1A can realize the common inversion drive system. The above shows the so-called normally black configuration in which light is not transmitted when the liquid crystal molecules are in the initial orientation state. Not limited to this, a so-called normally white configuration is also adopted in which light is transmitted when the liquid crystal molecules are in the initial orientation state, and when a voltage is applied to change the orientation state of the liquid crystal molecules from the initial orientation state, the display becomes black. Can be done.

FIG. 22 is a timing diagram showing the operation timing of the display device according to the third embodiment. As shown in FIG. 22, the display signal supplied to the first display signal line FRP changes synchronously and in phase with the common potential supplied to the common electrode 23. The inverted display signal supplied to the second display signal line xFRP changes synchronously and in reverse phase with the common potential supplied to the common electrode 23. Others are the same as the operation timing of the display device of the second embodiment (see FIGS. 18 and 19), and thus the description thereof will be omitted.

Since the display device of the third embodiment operates in the same manner as the display device of the second embodiment, it has the same effect as the display device of the second embodiment. Further, since the first display signal line FRP and the second display signal line xFRP are formed by being connected to a wiring that supplies a common potential to the common electrode, the common potential is based on the second selection clock signal CLK-SEL ₂ . These signals can be changed at the same time, and the circuit can be miniaturized and the synchronization characteristics can be improved.

(Application example of the first to third embodiments)
FIG. 23 is a diagram showing an application example of the display device of the first to third embodiments. FIG. 23 is a diagram showing an example in which the display device 1 or 1A is applied to an electronic shelf label.

As shown in FIG. 23, the display devices 1B, 1C and 1D are attached to the shelves 102, respectively. Each of the display devices 1B, 1C and 1D has the same configuration as the display device 1 or 1A described above. The display devices 1B, 1C, and 1D are installed so that the heights from the floor surface 103 are different from each other and the panel inclination angles are different from each other. Here, the panel inclination angle is an angle formed by the normal line of the display surface 1a and the horizontal direction. The display devices 1B, 1C, and 1D emit the image 120 to the observer 105 side by reflecting the incident light 110 from the lighting fixture 100 as a light source.

Although the preferred embodiments of the present invention have been described above, the present disclosure is not limited to such embodiments. The contents disclosed in the embodiments are merely examples, and various changes can be made without departing from the spirit of the present invention. Appropriate changes made without departing from the spirit of the present invention naturally belong to the technical scope of the present invention. At least one of the various omissions, substitutions and modifications of the components may be made without departing from the gist of each of the embodiments and modifications described above.

1, 1A, 1B, 1C, 1D Display device 1a Display surface 2 1st panel 3 2nd panel 4 Interface circuit 4a Serial-parallel conversion circuit 4b Timing controller 4c Setting register 5 Source line drive circuit 6 Common electrode drive circuit 7 Inverted drive Circuit 8 Memory selection circuit 9 Gate line drive circuit 10 Gate line selection circuit 11 First board 15 Sub-pixel electrode (reflection electrode)
21 2nd substrate 23 Common electrode 30 Liquid crystal layer 31 Divider circuit 32 Selection circuit 33 1/2 divider 34 Selector 50 Memory block 51 1st memory 52 2nd memory 53 3rd memory 61, 61A Inverting switch FRP display signal line GL gate line group GCL gate line Pix pixel SPix sub-pixel SL memory selection line group SEL memory selection line

Claims (8)

A plurality of sub-pixels, each of which is arranged in the row and column directions and has a memory block having a plurality of memories for storing sub-pixel data.
A clock signal output circuit that outputs multiple clock signals with different frequencies based on the reference clock signal,
A selection circuit that selects one of the plurality of clock signals as the selection clock signal, and
A plurality of memory selection lines, each of which is provided in each line and includes a plurality of memory selection lines electrically connected to the memory block of the sub-pixel belonging to the line, and a plurality of memory selection lines.
A memory selection circuit that simultaneously outputs a memory selection signal that selects one memory from a plurality of memories in the memory block to a plurality of memory selection line groups in synchronization with the selection clock signal.
A common electrode to which a common potential common to the plurality of sub-pixels is supplied, and
A common electrode drive circuit that inverts the common potential in synchronization with the reference clock signal and outputs it to the common electrode.
Equipped with
The plurality of sub-pixels are
An image is displayed based on the sub-pixel data stored in one of the plurality of memories according to the memory selection line to which the memory selection signal is supplied.
Display device. Each of the plurality of sub-pixels
Sub-pixel electrode and
A switch circuit that outputs the sub-pixel data output from the memory block to the sub-pixel electrode, and a switch circuit.
Including
A plurality of display signal lines provided in each line and electrically connected to the switch circuit, respectively.
An inversion drive circuit that inverts a display signal for inverting the sub-pixel data supplied to the sub-pixel electrode in synchronization with the reference clock signal and outputs it to the plurality of display signal lines.
Further prepare
The switch circuit is
Based on the display signal, the sub-pixel data is output to the sub-pixel electrode as it is or inverted.
The display device according to claim 1. A plurality of sub-pixels, each of which is arranged in the row and column directions and has a memory block having a plurality of memories for storing sub-pixel data.
A clock signal output circuit that outputs multiple clock signals with different frequencies based on the reference clock signal,
A selection circuit that selects one of the plurality of clock signals as the first selection clock signal and selects one of the plurality of clock signals as the second selection clock signal.
A plurality of memory selection lines, each of which is provided in each line and includes a plurality of memory selection lines electrically connected to the memory block of the sub-pixel belonging to the line, and a plurality of memory selection lines.
A memory selection circuit that simultaneously outputs a memory selection signal that selects one memory from a plurality of memories in the memory block to a plurality of memory selection line groups in synchronization with the first selection clock signal.
A common electrode to which a common potential common to the plurality of sub-pixels is supplied, and
A common electrode drive circuit that inverts the common potential in synchronization with the second selection clock signal and outputs it to the common electrode.
Equipped with
The plurality of sub-pixels are
An image is displayed based on the sub-pixel data stored in one of the plurality of memories according to the memory selection line to which the memory selection signal is supplied.
Display device. Each of the plurality of sub-pixels
Sub-pixel electrode and
A switch circuit that outputs the sub-pixel data output from the memory block to the sub-pixel electrode, and a switch circuit.
Including
A plurality of display signal lines provided in each line and electrically connected to the switch circuit, respectively.
An inversion drive circuit that inverts a display signal for inverting the sub-pixel data supplied to the sub-pixel electrode in synchronization with the second selection clock signal and outputs it to the plurality of display signal lines. ,
Further prepare
The switch circuit is
Based on the display signal, the sub-pixel data is output to the sub-pixel electrode as it is or inverted.
The display device according to claim 3. The clock signal output circuit is
The plurality of clock signals obtained by dividing the reference clock signal by a plurality of division ratios are output to the selection circuit.
The display device according to any one of claims 1 to 4. A plurality of gate line groups, each of which is provided in each row and includes a plurality of gate wires electrically connected to the memory block of the sub-pixel belonging to the row.
A gate line drive circuit that sequentially outputs a gate signal that selects one row among a plurality of rows toward the plurality of rows when the sub-pixel data is written to the memory block.
Multiple source lines in each column,
A source line drive circuit that outputs a plurality of the sub-pixel data to the plurality of source lines when the sub-pixel data is written to the memory block.
When writing the sub-pixel data to the memory block, a gate line selection circuit that electrically connects one gate line in each of the plurality of gate line groups and the gate line drive circuit, and a gate line selection circuit.
Further prepare
The sub-pixel in the row to which the gate signal is supplied is
The sub-pixel data supplied to the source line is stored in one of the plurality of memories according to the gate line to which the gate signal is supplied.
The display device according to any one of claims 1 to 5. The plurality of sub-pixels are
The gate signal is supplied while displaying an image based on the sub-pixel data stored in one of the plurality of memories according to the memory selection line to which the memory selection signal is supplied. The sub-pixel data supplied to the source line is stored in another one of the plurality of memories according to the gate line.
The display device according to claim 6. The memory selection circuit is
Among each of the plurality of memory selection lines, the memory selection line to which the memory selection signal is output is sequentially switched.
The plurality of sub-pixels are
A moving image is displayed based on a plurality of sub-pixel data stored in each of the plurality of memories in response to the sequential switching of the memory selection lines to which the memory selection signal is output.
The display device according to any one of claims 1 to 7.

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