JP3292093B2 - Liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an active matrix liquid crystal display device, and more particularly to an active matrix liquid crystal display device with a built-in memory.

[0002]

2. Description of the Related Art A conventional active matrix driving system is described in "Color Liquid Crystal Display" (Sangyo Tosho) by Shusuke Kobayashi published in 1990. However, when driving an active matrix type liquid crystal display, scanning is performed. The line applies a scan pulse once every frame time. Usually, the timing of this pulse is sequentially shifted from the upper side of the panel toward the lower side. 1/60 second is often used as the time for one frame. In a color panel of 640 × 480 dots, which is a typical pixel configuration, 480 scans are performed in one frame time, so the time width of the scan pulse is (1/60) / 480 s = about 35 μs.

On the other hand, a liquid crystal driving voltage to be applied to the liquid crystal of one row of pixels to which the scanning pulse is applied is simultaneously applied to the signal line in synchronization with the scanning pulse. In the selected pixel to which the gate pulse is applied, the gate electrode voltage of the TFT connected to the scanning line increases, and the TFT is turned on. At this time,
A liquid crystal driving voltage is applied to a display electrode via a source and a drain of the TFT, and a liquid crystal capacitance formed between the display electrode and a counter electrode formed on a counter substrate, and a load capacitance disposed in a pixel. And the pixel capacitance is charged. By repeating this operation, a voltage is repeatedly applied to the liquid crystal to the pixel capacitance on the entire panel every frame time.

The alternating voltage is applied to the liquid crystal applied voltage by inverting the polarity every frame time. As a result,
In general, when the frame frequency is 60 Hz, the liquid crystal driving frequency is 30 Hz which is 1/2 of this frequency. In the case of the above-mentioned 640 × 480 dot panel, the polarity of this signal electrode is inverted every 35 μs during one scanning period, so that the driving frequency of the signal electrode is 640 × 60/2 Hz = 14.4 kHz.
z and about 500 times the liquid crystal driving frequency. That is, even when the displayed image does not change, the potential of the signal electrode line is changed at high speed.

[0005]

Since power consumption is proportional to frequency, a great deal of power is consumed in the prior art.
Accordingly, the present applicant has filed Japanese Patent Application Nos. 8-62996 and 8-1.
No. 5979 proposes a liquid crystal display that significantly reduces power consumption. This liquid crystal display device includes a display data holding circuit for each pixel and a switch unit controlled by the held display data. According to this device, an AC voltage for driving the liquid crystal is applied to the counter electrode, which is one electrode of the liquid crystal, and the display electrode, which is the other electrode, is controlled by the switch means. That is, the AC voltage of the counter electrode is applied to the liquid crystal when the switch is on, and no voltage is applied to the liquid crystal when the switch is off.

In this method, when there is no change in the contents of the display data, it is not necessary to change the potential of the signal line or the scanning line, and the power consumption can be reduced.

However, in order to perform multi-tone display by this method,
Since the same number of capacitors as the switch means are formed, the circuit area becomes large, the wiring pattern becomes complicated, the yield decreases, and the manufacturing cost increases. In addition, in order to form a transmissive type, the aperture ratio is reduced, and even in the case of a reflective type, it is necessary to form a pixel electrode on the substrate surface with a small size, or to form a thick insulating film and form an upper layer.

An object of the present invention is to reduce the circuit area and reduce the manufacturing cost when realizing multi-tone display with a liquid crystal display device having a built-in memory.

[0009]

According to a first configuration, in a liquid crystal display device having at least one pair of transparent substrates and a liquid crystal layer sandwiched between the pair of substrates, one of the pair of substrates is provided. A plurality of scanning lines, a plurality of data signal line groups that intersect the plurality of scanning lines in a matrix, a plurality of timing line groups formed between the plurality of scanning lines, and the plurality of scanning lines. A memory connected to the corresponding scanning line and the data signal line group in a region surrounded by the plurality of data signal line groups, and capturing and holding display data from the data signal line group in response to the scanning signal; A sample-and-hold circuit connected to the memory, fetching data held in the memory, and having an output controlled by a timing signal of a timing line group corresponding to the region; A first switching means controlled by the output of the hold circuit, a is configured to have its first pixel electrode connected to the switching means.

According to a second configuration, in a liquid crystal display device having at least one of a pair of transparent substrates and a liquid crystal layer sandwiched between the pair of substrates, one of the pair of substrates has a plurality of substrates. Scanning lines, a plurality of data signal line groups intersecting the plurality of scanning lines in a matrix, and a plurality of timing line groups formed between the plurality of scanning lines,
In a region surrounded by the plurality of scanning lines and the plurality of data signal lines, the display data from the data signal lines is connected to the corresponding scanning lines and data signal lines in response to the scanning signal. A selection circuit connected to the memory for capturing and holding the data, capturing the data held in the memory, and controlling the output by the timing signals of the plurality of timing line groups; and a control circuit controlled by the output of the selection circuit. A first switching means, and a pixel electrode connected to the first switching means.

[0011] In addition to these configurations, a configuration may be added in which the other substrate has a counter electrode facing the pixel electrode.

In the first configuration, a plurality of second switching means connected to the memory may be formed in the sample and hold circuit.

In the second configuration, a plurality of second switching means connected to the memory may be formed in the selection circuit.

Further, a plurality of common lines are formed between the scanning lines of both configurations, and the first switching means is connected to the common lines corresponding to a region surrounded by the data signal line group and the scanning lines. Configuration.

Further, when driving these liquid crystal display devices, it is desirable to adopt the following driving method.

(1) The amplitude of the liquid crystal drive voltage applied to the counter electrode and the pixel electrode is made substantially equal to each other, the frame period is divided into a plurality of subframes, and the lengths of the divided subframe periods are made different. .

(2) The amplitude of the liquid crystal drive voltage applied to the counter electrode and the pixel electrode is made different from each other, the frame period is divided into a plurality of subframes, and the lengths of the divided subframe periods are made substantially equal. .

(3) The waveforms of the liquid crystal driving voltages applied to the counter electrode and the pixel electrode are made equal to each other, the frame period is divided into a plurality of subframes, and the lengths of the divided subframe periods are changed. The effective value of the voltage during the subframe period is changed in proportion to the square of the subframe period.

(4) At the beginning of each sub-frame, a period is provided in which the liquid crystal drive voltage is equal to the center voltage.

These driving methods will be described in detail.
The liquid crystal drive voltage is an AC voltage in which a voltage waveform of one frame including n sub-frames is periodically repeated, and the time integration of the absolute value of the difference from the center voltage in each sub-frame period is different from each other. I do. Further, a period in which the voltage applied to the liquid crystal at the beginning of each subframe becomes 0 (reset period), that is, a period in which the liquid crystal driving voltage is equal to the center voltage is provided.

The first switching means formed for driving the pixel controls connection between the pixel electrode and the center voltage of the liquid crystal driving voltage.

The timing signal is connected to the pixel drive so that a voltage equal to the center voltage is applied to the pixel electrode when the i-bit display data of the memory is "1" during the i-th subframe period. The first switching means for driving the pixel is controlled such that a voltage equal to the liquid crystal driving voltage is applied to the pixel electrode when the i-bit display data of the memory is "0". Control.

For example, the operation will be described by taking a case where the number of subframes n = 3 as an example.

One frame is divided into first, second and third subframes. The liquid crystal drive voltage is such that the time integral of the absolute value of the difference from the center voltage in each subframe period is V ₁ ,
It is set so that V ₂ = 2V ₁ and V ₃ = 4V ₁ .

When the content of the memory is "011", the first switching means for driving the pixel is O in the first sub-frame.
The FF state, the O state in the second subframe, and the ON state in the third subframe. Therefore, the second and third liquid crystals are provided.
The difference between the liquid crystal driving voltage and the center voltage is applied only to the sub-frame, and no voltage is applied to the first sub-frame. That is, the voltage in the first sub-frame 0, the voltage 2V ₁ in the second sub-frame, 4V ₁ is applied in the third sub-frame. Accordingly, the average value of the voltage applied in one frame becomes _{(0 + 2V 1 + 4V 1} ) / 3 = 2V 1. Thus, when n = 3, 2 ⁿ = 2 ³ = 8 voltages can be applied to the liquid crystal, and eight levels of gray scale can be displayed.

From the third sub-frame to the first of the next frame
When switching to the sub-frame, the first switching means for driving the pixel changes from the ON state to the OFF state. At this time, if there is no reset period, the voltage of the third sub-frame is held in the first sub-frame, and desired driving cannot be performed.

[0027]

Embodiments of the present invention will be described below in detail.

A pair of substrates at least one of which is transparent, a liquid crystal layer sandwiched between the pair of substrates, a plurality of scanning lines formed in a scanning circuit on one of the pair of substrates, and a matrix-like arrangement of these scanning lines. And a plurality of data signal line groups consisting of n data signal lines intersecting with each other, and n
A plurality of timing line groups consisting of the timing lines are formed. Further, in a region surrounded by the scanning line and the n data signal line groups, the corresponding scanning line and the n data signal line group are connected, and in response to the scanning signal applied to the scanning line,
a memory for capturing and holding n display data from the n data signal line groups, and a display data signal connected to the memory for capturing and holding the display data signal held in the memory;
A sample and hold circuit whose output is controlled by a timing signal of a group of timing lines, first switching means controlled by the output of the sample and hold circuit, a pixel electrode connected to the first switching means, and a scanning line , A data signal circuit for driving the data signal lines, a liquid crystal driving AC voltage source for supplying a liquid crystal driving AC voltage VCP for driving the liquid crystal to the common electrode, and timing signals VF ₁ and VF _2. , VF ₃ ... VF
It comprises a timing circuit for generating n and a center voltage circuit for supplying a center voltage VCNT of the liquid crystal drive AC voltage VCP to the pixel circuit.

Further, the scanning lines and the data signal line groups are made orthogonal to each other, and the pixel circuit is provided at the intersection thereof. Further, a common line for supplying a center voltage and a group of timing lines for supplying a timing signal are arranged in parallel with the scanning line and connected to the pixel circuit.

The pixel circuit includes a memory for storing voltages VM ₁ , VM ₂ , VM _3, ..., VMn corresponding to n pieces of display data VF ₁ , VF ₂ , VF ₃ ,. From the memory, the voltages VM ₁ , VM ₂ , VM ₃ ... VM
and a sample-and-hold circuit for selecting and taking out the n, and a voltage VS held by the sample-and-hold circuit
And switching means for controlling the connection state between the pixel electrode and the common line. Sample-and-hold circuit, when the VF ₁ = _"1", samples the VM _1, and held as VS = VM _1, when VFn = "1", samples the VMn, held as VS = VMn.

When the voltage of the scanning voltage VG of the scanning line in the first sub-field T ₁ is VG ₁ = "1", that is, when the memory takes a voltage value for operating the memory, the memory receives the data signal line group. sampling the data signal voltage VD _1,
VM ₁ = VD ₁ is held in the memory. When the scan voltage VG of the scan line is VGn = “1” in the n-th subfield Tn, the memory samples the data signal voltage VDn of the data signal line group and holds it as VMn = VDn.

The sampling hold circuit takes a voltage value when the voltage VF ₁ of the timing line group in the _first subfield T ₁ is VF ₁ = "1", that is, the voltage applied to the memory is turned on. At this time, the voltage VM ₁ held in the memory is sampled and held as VS = VM ₁ .

When the voltage VFn of the timing line group in the n-th subfield Tn is VFn = “1”, that is, when the voltage applied to the memory takes a voltage value that turns on the memory, the voltage VM ₁ held in the sampling and holding as VS = VMn.

The first switching means is turned on when the voltage VS held in the sampling and holding circuit is VS = "1", connects the pixel electrode to the common line, and sets the VS.
When it is "0", it is turned off, and the connection between the pixel electrode and the common line is released.

At this time, the sample and hold circuit can be realized by n pieces of second switching means and at least one first capacity, and the memory is composed of n pieces of third switching means and the same number of second capacity. Can be configured.

It is preferable that the first and second capacitors and the first switching means are connected to a common line or grounded.

Also, instead of the sample and hold circuit, A
It is also conceivable to use a selection circuit such as an ND circuit.

<Embodiment 1> FIG. 1 is a block diagram showing a liquid crystal display device according to an embodiment of the present invention.

The present liquid crystal display device has one substrate on which pixel circuits 50 are arranged in a matrix in a matrix, the other substrate having a transparent counter electrode 70, a liquid crystal layer inserted between both substrates, and a scanning line 100. , A data circuit 2 for driving the data signal line group 200, a liquid crystal driving AC voltage source 5 for supplying a liquid crystal driving AC voltage VCP for driving the liquid crystal to the counter electrode 70, and timing signals VF ₁ , VF ₂ ,
A timing circuit ₃ for generating VF ₃ and the pixel circuit 5
And a center voltage circuit 4 for supplying the center voltage VCNT of the liquid crystal drive AC voltage VCP to the center voltage VCNT.

The scanning lines 100 and the data signal line groups 20
0 are perpendicular to each other, and the pixel circuit 5
0 is provided. Further, a common line 40 for supplying a center voltage
0 and a timing line group 300 for supplying a timing signal are arranged in parallel with the scanning lines, and are connected to the pixel circuit 50.

FIG. 2 shows three data signal lines according to the present invention.
FIG. 3 is a block diagram illustrating a configuration of a pixel circuit 50 of a liquid crystal display device when applying individual display data. Pixel circuit 50
Represents three display data VF applied to the data signal line group.
₁ , VF ₂ , and VF ₃ corresponding to voltages VM ₁ , VM ₂ , V
A memory 10 for storing the M _3, the voltage VM _1, VM _2, V
M ₃ is selected and taken out, and is held by a sample and hold circuit 20, and a first switching means 3 controlled by a voltage VS held by the sample and hold circuit 20 to determine a connection state between the pixel electrode 40 and the common line 400.
Consists of zero. The sample and hold circuit 20 calculates VF ₁ =
When "1", the VM ₁ samples, VS = retained as VM _1, when VF ₂ = "1", the VM ₂ samples, holds as VS = VM _2, the VF ₃ = "1" At this time, VM ₃ is sampled and held as VS = VM ₃ .

FIG. 3 is a circuit diagram for realizing the pixel circuit 50 shown in the block diagram of FIG. The memory 10 includes three sets of memory TFTs 11 and 12 as third switching means.
13 and memory capacities 14, 15, 16 as second capacities
Consists of The sample hold circuit 20 includes three sampling TFTs 21 and 2 as second switching means.
2, 23 and one hold capacitor 24 as the first capacitor
Consists of Further, a switch TFT 31 was formed as first switching means 30 for controlling the voltage of the pixel electrode. In this embodiment, a TFT is used as the first, second, and third switching means, but any means having a switching function may be used. In addition, the first
The second capacitance may be any element having a storage function such as a capacitor.

The memory TFT 11 determines that the scanning voltage VG of the scanning line 100 is equal to VG ₁ = V in the first subfield T _1.
When the value is “1”, that is, when a voltage value for operating the memory TFT 11 is taken, the data signal voltage VD ₁ of the data signal line group 200 is sampled and held in the memory capacitor 14 as VM ₁ = VD ₁ .

The memory TFT 12 determines that the scanning voltage VG of the scanning line 100 is equal to VG ₂ = ₂ in the _second subfield T _2.
When “1”, the data signal voltage VD ₂ of the data signal line group 200 is sampled and held in the memory capacity 15 as VM ₂ = VD ₂ .

The memory TFT 13 determines that the scanning voltage VG of the scanning line 100 is VG ₃ = ₃ in the _third subfield T _3.
When “1”, the data signal voltage VD ₃ of the data signal line group 200 is sampled and held in the memory capacity 16 as VM ₃ = VD ₃ .

When the voltage VF ₁ of the timing line group 300 is VF ₁ = "1", that is, when the memory TFT 11 takes a voltage value for operating the ON state, the sampling TFT 21 holds the voltage VM ₁ held in the memory capacitor 14. the sampled and held at the hold capacitor 24 as a VS = VM _1. The sampling TFT 22 includes a timing line group 30.
0 when the voltage VF ₂ is VF ₂ = "1", that is, when the memory T
When the voltage value for operating the FT 12 is taken, the memory capacity 1
5 voltage VM ₂ held in the sampling, VS = V
Held at the hold capacitor 24 as M _2. The sampling TFT 23 detects that the voltage VF ₃ of the timing line group 300 is V
When F ₃ = “1”, that is, when the voltage value for operating the memory TFT 13 is taken, the voltage VM ₃ held in the memory capacitor 16 is sampled and held as VS = VF ₃ in the hold capacitor 24.

The switch TFT 31 is turned on when the voltage VS held in the hold capacitor 24 is VS = “1”, connects the pixel electrode 40 to the common line 400, and sets VS =
When it is “0”, it is turned off, and the connection between the pixel electrode 40 and the common line 400 is released.

The operation of the first embodiment of the present invention configured as described above is replaced with the operation of the first embodiment shown in FIG.
This will be described in detail with reference to the timing chart of the signal waveform of FIG. The signals shown in FIG. 4 are the outputs VF ₁ , VF ₂ , V
F ₃ , the voltage V held in the memory capacities 14, 15, 16
M ₁ , VM ₂ , VM ₃ , the voltage VS held in the hold capacitor 24, the counter electrode 70 supplied from the AC voltage circuit 5
The liquid crystal drive AC voltage VCP, the pixel electrode drive voltage VPX of the pixel electrode 40, and the liquid crystal applied voltage VLC can be expressed by the following equation: VLC = VCP−VPX. Output VCP of the alternating voltage is an AC voltage based on the voltage VCNT of the center voltage circuit, the period T ₀ of a frame which is the period, flicker upon displaying, is determined from conditions such as power consumption Here, T ₀ = 1/60 s = 16.6 ms.

The first sub-frame of one frame period T _1, the second sub-frame period of T _2, a third period T3
It is divided into subframes. Here, T ₂ = 2T ₁ , T
₃ = was set 4T ₁ and.

Outputs VF ₁ , VF ₂ , V of the timing circuit
Period of F ₃ is T _0, VF ₁ the first period t ₀ to "1" and the first sub-frame, VF ₂ the first period t ₀ to "1" and the second sub-frame, VF ₃ Becomes “1” during the first period t ₀ of the third subframe. here,
t ₀ is a time sufficiently shorter than T ₁ , T ₂ , and T ₃ .

The voltage VCP applied to the counter electrode 70 is
An AC voltage whose amplitude value with respect to the center voltage VCNT is ± V _{0 and} whose polarity is inverted during each subframe period, and VF
_1, VF ₂ or VF ₃ is set to be equal to the center voltage value VCNT in the state of "1".

In FIG. 4, the outputs VM ₃ and VM _{3 of the} memory 10 are shown.
₂ , VM ₁ changes from “110” to “000” as an example. Outputs VM ₁ , VM ₂ , VM of memory 10
_{Timing 3} changes are dependent on the write operation of the memory _{10, VF 1, VF 2,} VF 3 and VCP especially a need not be synchronized.

First, in the first sub-frame, the output VM _{1 of the} memory 10 is “0”, so that VS = VM ₁ =
“0” is held, and the switch TFT 31 is turned off. Therefore, the voltage applied to the liquid crystal during this period is VLC
= 0. In the second sub-frame, the memory 10
Since the output VM ₂ of “1” is “1”, VS = VM ₂ = “1” is held, and the switch TFT 31 is turned on. Therefore, the voltage applied to the liquid crystal during this period is VLC = ± V ₀ . In the third sub-frame, output VM ₃ of the memory 10 because "1", VS = the VM ₃ = "1" is held, the switch TFT31 is in an ON state. Therefore, the voltage applied to the liquid crystal during this period is VLC = ± V ₀ . Therefore, the average value of the absolute value of the voltage applied to the liquid crystal in the first frame is VAV = (V ₀ × T ₃ + V ₀ × T + 0 × T ₁ ) / T
₀ = 6V ₀ × T ₁ / T ₀ (= 6α). According to this method, n = n held in the memory capacities 14, 15, 16
According to a combination of three display data, VAV = 0 when “000”, VAV = α when “001”, and
VAV = 2α when “010”, VAV = 3α when “011”, VAV = 4α when “100”, “10
VAV = 5α when “1”, VAV when “110”
= 6α, ²ⁿ = 2 ³ = Vα = 7α when “111”
Eight different average voltages can be applied to the liquid crystal, thereby displaying a gray scale.

When switching from the third subframe of the first frame to the first subframe of the second frame, VS = "1" changes to VS = "0", and the switch TFT 31 changes from the ON state to the OFF state. Switch. For example, if a voltage is applied to the liquid crystal at this timing,
When the switch TFT 31 is switched to the OFF state, this voltage is held, and the voltage applied to the liquid crystal during the period of the first sub-frame of the second frame cannot be set to a desired value of zero. According to the present invention, when VF ₁ , VF ₂ or VF ₃ becomes “1” and VS changes, V
Since CP = VCNT, that is, the voltage is set so as not to be applied to the liquid crystal, the voltage applied to the liquid crystal during the first sub-frame of the second frame can be set to a desired value of zero.

In FIG. 4, VM ₂ and VM ₃ are switched from “1” to “0” during the third frame of the second frame. At this time, VF ₁ , VF ₂ , and VF
₃ = "0", and the sampling TFTs 21, 22, 2,
3 is in the OFF state, the change of VM ₂ and VM ₃ is V
Does not affect S. That is, the switch TFT 31
Does not change and does not affect the liquid crystal. These changes will be applied to VF ₂ or VF _{3 in the} next frame.
Becomes "1" and affects the liquid crystal only. As described above, since the memory 10 and the switch 31 are separated, the contents of the memory 10 can be written asynchronously with the voltage applied to the liquid crystal.

After the third frame in which the state of the memory becomes "000", the switch TFT 31 is always OFF and VLC = 0.

With this configuration, the memory capacity 14,
If VM ₁ , VM ₂ , and VM ₃ are well maintained by the steps 15 and 16, there is no need to rewrite the contents of the memory unless the displayed image changes. That is, by using the present invention, a ^2n- level gradation display can be performed with a liquid crystal display device with a built-in memory, and a liquid crystal display device with small size and low power consumption can be provided.

For each subframe, the memory capacity 14,1
Since VS is changed by moving the electric charge between 5, 1 and the hold capacitor 24, VM ₁ , V
The voltage levels of M ₂ , VM ₃ are gradually averaged, and the voltage levels of VM ₁ , VM ₂ , VM ₃ are reduced due to leakage of the memory TFTs 11, 12, 13, but this is prevented. Memory capacity 14,1
A large capacity may be used as 5 and 16, and a small capacity may be used as the hold capacity 24. Further, even when the display image does not change, the display data in the memory may be rewritten every fixed number of frames or when the voltage becomes equal to or lower than a certain voltage. Furthermore, if the rewriting is performed to such an extent that power consumption does not increase, not only the size can be reduced but also the effect of low power consumption can be maintained.

FIG. 5 is a timing chart showing a second signal waveform for operating the first embodiment.

VF ₁ , VF ₂ , VF ₃ , VM ₁ , V
M ₂ , VM ₃ , and VS are the same as the first signal waveform shown in FIG. 4, but have different VCPs. In the first signal waveform, VCP
Is a symmetrical waveform whose polarity is inverted during the sub-frame period, and is an AC waveform having no DC component during the sub-frame period. However, in the second signal waveform, the VCP does not reverse the polarity during the sub-frame period, and therefore, , 1st, 2nd
The waveform includes a DC component in one frame period including the third subframe. To compensate for this DC component, FIG.
As shown in (1), the polarity is inverted for each frame, and the AC waveform has no DC component and the period of two frames is one cycle. If the second signal waveform is used, the frequency of the VCP can be reduced as compared with the first signal waveform, so that the power consumption can be further reduced.

FIG. 6 is a timing chart showing a third signal waveform for operating the first embodiment.

[0062] 1 frame period T _0, the first sub-frame as in the first and second signal waveform, Periods T _1, T ₂
The second sub-frame period, but is divided into a third sub-frame period of T _3, unlike the first and second signal waveform is _{T 1 = T 2 = T 3} = T 0/3. The amplitude of the VCP is set to ± V ₁ in the first sub-frame, ± V ₂ in the _second sub-frame, and ± V ₃ in the third sub-frame. In FIG. 6, V ₂ = 2V ₁ and V ₃ = 4V ₁ . In addition, the VCP is set to a waveform having one cycle of two frames in the same manner as the second signal waveform. However, similarly to the first signal waveform, a waveform having one cycle of one frame in which the polarity is inverted during the sub-frame period is set. The same effect can be obtained by using.
By making the VCP have such a waveform, the average value VAV of the absolute values of the voltages applied to the liquid crystal in one frame is calculated as follows.
By the combination of n = 3 pieces of display data held in the memory capacities 14, 15, and 16, VAV = 0 when “000” and VAV = (0 × V ₃ when “001”).
_{+ 0 × V 2 + 1 ×} V 1) / 3 = V 1/3 (= β), "01
VAV = (0 × V ₃ + 1 × V ₂ + 1 × V ₀ ) at the time of “0”
/ 3 = a _{2V 1/3 = 2 × β} = 2β. Similarly,
VAV = 3 × β = 3β when “011”, VAV = 4 × β = 4β when “100”, VA when “101”
V = 5 × β = 5β, VAV = 6 × β when “110”
= 6β, ²ⁿ = VAV = 7 × β = 7β when “111”
It is possible to apply 2 ³ = 8 different average voltages VAV to the liquid crystal, thereby displaying gradation. In the first and second signal waveforms, as the number n of display data increases, the minimum value of the subframe period sharply increases. However, in the third signal waveform, the subframe periods are all the same.
The minimum value of the sub-frame period can be made longer than that of the second signal waveform. That is, the highest frequency component of the VCP is lower than the first and second signal waveforms, and thus the power consumption can be reduced.

FIG. 7 is a timing chart showing a fourth signal waveform for operating the first embodiment.

VF ₁ , VF ₂ , VF ₃ , VM ₁ , V
M ₂ , VM ₃ , and VS are the same as the third signal waveform shown in FIG. 6, but have a different VCP. In the third signal waveform, VCP
Was changed in each sub-frame, thereby changing the absolute value of the voltage in the sub-frame period.
In the signal waveform of (1), the pulse width is changed instead of the amplitude of the VCP to change the absolute value of the voltage in the sub-frame period. In FIG. 7, the pulse width of the VCP in the first, second, and third sub-frame periods is t ₁ , t ₂ = 2 × t ₁ = 2t.
₁ , t ₃ = 4 × t ₁ = 4t ₁ . By making the VCP have such a waveform, the average value VAV of the absolute value of the voltage applied to the liquid crystal in one frame can be calculated by combining n = 3 pieces of display data held in the memory capacities 14, 15, and 16. VAV when "000"
= 0, “001”, VAV = (0 × t ₃ + 0 × t ₂₎
+ V ₀ × t ₁ ) / T ₀ = V ₀ × t ₁ / T ₀ (= γ), “01
VAV = (0 × t ₃ + V ₀ × t ₂ + 0 ×
t ₁ ) / 3 = V ₀ × 2 × t ₁ / T ₀ = 2γ Similarly, VAV = 3γ when “011”, VAV = 4γ when “100”, VAV = 5γ when “101”,
The average voltage VAV of 2 ⁿ = 2 ³ = 8 with VAV = 6γ when “110” and VAV = 7γ when “111”
Can be applied to the liquid crystal, whereby a gray scale can be displayed. In the fourth signal waveform, VCP consists of a number of voltage levels, but in the fifth signal waveform, even if the number n of display data increases, VCP is VCNT + V ₀ , VNCT, V
Since it has three levels of NCT-V ₀ , the liquid crystal driving AC voltage source that outputs the VCP can have a simple configuration.

In this embodiment, the configuration for displaying eight gradations is particularly shown. However, when it is desired to display 2 ⁿ -level gradations, the number of data lines and the memory capacity (the number of memory TFTs and the memory capacity) are reduced. Sample hold circuit (Sampling T
FT number, hold capacity) and the number of timing lines are n
Change to double. Also, the driving method is such that the subfield is equally divided into n, and an n-level voltage is set, or the voltage is divided by a time proportional to the square of the minimum subfield period, and the voltages having the same amplitude are divided. The processing performed in the above 3 such as application may be changed to n.

<Embodiment 2> FIG. 8 is a block diagram showing a liquid crystal display device according to a second embodiment of the present invention. The present liquid crystal display device drives one substrate in which pixel circuits 50 are arranged in a matrix in a matrix, and the other substrate having a transparent counter electrode 70, a liquid crystal layer inserted between both substrates, and scan lines 100. Scanning circuit 1 and data signal line group 20
0, a liquid crystal driving AC voltage source 5 for supplying an AC voltage for driving the liquid crystal to the counter electrode 70, and a timing circuit 3 for generating timing signals VF ₀ , VF ₁ , VF ₂ , and VF _3. And a center voltage circuit 4 for supplying a center voltage VCNT of an AC voltage to the pixel circuit 50.
The scanning line 100 and the data signal line group 200 are perpendicular to each other,
A pixel circuit 50 is provided at the intersection. Further, a common line 400 for supplying a center voltage and a timing line group 300 for supplying a timing signal are arranged in parallel with the scanning lines, and are connected to the pixel circuit 50.

FIG. 9 is a block diagram showing a configuration of a pixel circuit 50 of a liquid crystal display device according to a second embodiment of the present invention. The pixel circuit 50 includes a memory 10 storing voltages VM ₁ , VM ₂ , and VM ₃ corresponding to n = 3 display data;
Any one of VM ₁ , VM ₂ , and VM ₃ is selected and changed to the sample and hold circuit of the first embodiment that outputs as VS. The sample and hold circuit is controlled by the selection circuit 80, VS and VF ₀ , And a switch 90 for switching a connection relationship with a common line or a ground, which is a first switching means 30 for determining the connection state of the switch.
Selection circuit 80, when the VF ₁ = _"1", selects the VM _1, and outputs a VS = VM _1, when VF ₂ = "1", V
Select the M _2, and output the _{VS = VM 2, VF 3 =} "1"
At this time, VM ₃ is selected, and VS = VM ₃ is output. First switching means 30 is output VS is VS = "1" or a timing signal VF ₀ of the selection circuit 80 VF ₀ =
"1" connects the pixel electrode 40 and the common line 400 when, VS = "0", and releasing the connection of the pixel electrode 40 and the common line 400 when the VF ₀ = "0".

FIG. 10 is a circuit diagram for realizing the pixel circuit 50 shown in the block diagram of FIG. The memory 10 has n = 3 sets of memory TFTs 11, 12, 13 and memory capacities 14, 1
Consists of 5 and 16. The selection circuit 80 includes n = 3 sets × 2 = 6 switch TFTs as second switching means.
81, 82, 83, 84, 85, 86.

[0069] In this embodiment, the switch function according to the VF of the second switching means of the sample-and-hold circuit 20 shown in Example 1 is performed by the selecting circuit 80, the first switch of the switching means 30 according to the VF ₀ The function is constituted by the switch TFT91.

The memory TFT 11 determines that the voltage VG of the scanning line 100 is equal to VG ₁ = V in the first subfield T _1.
When “1”, the voltage VD ₁ of the data signal line group 200 is sampled and held in the memory capacity 14 as VM ₁ = VD ₁ .

The memory TFT 12 determines that the voltage VG of the scanning line 100 is equal to VG ₂ = ₂ in the _second subfield T _2.
When the value is “1”, the voltage VD ₂ of the data signal line group 200 is sampled, and VM ₂ = VD ₂ is held in the memory capacity 15.

The memory TFT 13 determines that the voltage VG of the scanning line 100 is equal to VG ₃ = ₃ in the _third subfield T _3.
When “1”, the voltage VD ₃ of the data signal line group 200 is sampled, and is held in the memory capacity 16 as VM ₃ = VD ₃ .

[0073] Switch TFT81, the voltage VM ₁ held in the memory 14 becomes ON state when the VM ₁ = _"1", the switch TFT84 timing line group 300
Is turned on when the voltage VF ₁ of VF _{1 is} “1”. Therefore, when VM ₁ = “1” and VF ₁ = “1”, the pixel electrode 40 is connected to the common line 400. The switch TFT 82 is turned on when the voltage VM ₂ held in the memory capacitor 15 is VM ₂ = “1”, and the switch TFT 85 is turned on when the voltage VF ₂ of the timing line group 300 is V
It turns ON when F ₂ = “1”. Therefore, VM ₂
= “1” and VF ₂ = “1”, the pixel electrode 40
Are connected to a common line 400. Switch TFT83
Means that the voltage VM ₃ held in the memory capacity 16 is VM ₃ =
It becomes ON state when the "1", the switch TFT86 the voltage VF ₃ timing line group 300 become ON state when the VF ₃ = "1". Therefore, VM ₃ = “1”, and
When VF ₃ = “1”, the pixel electrode 40 is connected to the common line 400
Connected to.

The switch TFT 91 is connected to the timing line group 3
When the voltage VF _{0 of} 00 is VF ₀ = “1”, the pixel electrode 40 and the common line 400 are connected.

The operation of the second embodiment of the present invention configured as described above will be described in detail with reference to a timing chart of signal waveforms shown in FIG. The signals shown in FIG. 11 are the output of the timing circuit VF ₀ , VF ₁ , VF ₂ , VF ₃ , memory capacity 1
Voltages VM ₁ , VM ₂ , VM held at 4, 15, 16
₃ , the voltage VCP of the counter electrode 70 supplied from the AC voltage circuit 5, the voltage VPX of the pixel electrode, and the liquid crystal applied voltage VLC =
VCP-VPX. The output VCP of the AC voltage circuit is
The AC voltage is based on the voltage VCNT of the center voltage circuit.

The period T _{0 of} one frame is the first sub-frame of the period T ₁ , the second sub-frame of the period T ₂ , T ₃
Are divided into a third subframe in the period of. Where T ₂
= 2T ₁ , T ₃ = 4T ₁ .

The outputs VF ₀ , VF ₁ , V of the timing circuit
The periods of F ₂ and VF ₃ are T ₀ , where VF ₀ is the first period t ₀ of the first sub-frame, the first period t ₀ of the second sub-frame, and the first period t ₀ of the third frame. ₀ becomes “1”, VF ₁ becomes “1” during the first sub-frame period, VF ₂ becomes “1” during the second sub-frame period, and VF ₃ becomes “1” during the third sub-frame period. Is set to be Here, t ₀ is T ₁ ,
The time is sufficiently shorter than T ₂ and T ₃ .

The voltage VCP applied to the counter electrode 70 is
The amplitude value with respect to the center voltage VCNT is ± V ₀ and the cycle is 2
It is set to be equal to the center voltage value VCNT when the frame is an AC voltage and VF ₀ is “1”.

In FIG. 11, the outputs VM ₃ , V
The case where M ₂ and VM ₁ change from “110” to “000” is taken as an example. The outputs VM ₁ , VM ₂ ,
Since the timing at which VM ₃ changes depends on the write operation of the memory 10, VF ₁ , VF ₂ , VF ₃ or VCP
VF ₀ = “1” in the period t ₀ of the first sub-frame
Therefore, the switch TFT 91 is in the ON state, and the pixel electrode 40 is connected to the common line 400. At this time, VCP =
VCNT, and the voltage applied to the liquid crystal is VLC = 0. During the period (T ₁ −t ₀ ) in the subsequent first subframe, the switch TFTs 81, 85, 86, and 91 are in the O state.
In the FF state, the connection between the pixel electrode 40 and the common line 400 is released, and VLC = 0 is maintained. In the first period t ₀ of the subsequent second frame, since VF ₀ = “1”, the switch TFT 91 is in the ON state, and the pixel electrode 40 is connected to the common line 400. At this time, VCP = VCN
T, and the voltage applied to the liquid crystal is VLC = 0.
During the period (T ₂ −t ₀ ) in the subsequent second sub-frame, VF ₂ = “1” and VM ₂ = “1”, and the pixel electrode 40 is connected to the common line 400. Therefore, the difference voltage VPX between the VCP and the pixel electrode voltage VPX = VCNT is applied to the liquid crystal.
LC = VCP−VPX = −V ₀ is applied. The third that follows
In the first period t ₀ of the subframe, VF ₀ =
Because of “1”, the switch TFT 91 is in the ON state, and the pixel electrode 40 is connected to the common line 400. At this time, V
CP = VCNT, and the voltage applied to the liquid crystal is VLC = 0.
It is. In the period of (T ₃ −t ₀ ) in the subsequent third subframe, VF ₃ = “1” and VM ₃ = “1”
And the pixel electrode 40 is connected to the common line 400.
Therefore, the liquid crystal has VCP and the voltage VPX = VC of the pixel electrode.
The difference voltage VLC of NT = VCP−VPX = V ₀ is applied. Therefore, the average of the absolute values of the voltages applied to the liquid crystal in the first one frame is VAV = (0 × T ₁ + V ₀ × T ₂ +
V ₀ × T ₃ ) / T ₀ = 6V ₀ × T ₁ / T ₀ (= 6α).
According to this method, 2 ⁿ = 2 ³ = 8 as in the first embodiment.
It is possible to apply the same average voltage to the liquid crystal,
Thereby, gradation can be displayed.

In FIG. 11, VM ₂ and VM ₃ are switched from “1” to “0” during the period of the third frame in the _second frame. At this time, since the state of the switch TFT 83 switches from ON to OFF, the pixel electrode 40 changes from the state connected to the common line 400 to the state opened. At this time, the voltage VLC applied to the liquid crystal =
−V ₀ is maintained. For example, if there is no period t ₀ during which VF ₀ = “1” in the first sub-frame of the third frame that follows, the connection between the pixel electrode 40 and the common line 400 is left open in this first sub-frame. And VLC = −V ₀ is maintained, and the desired VLC = 0 is not applied. However, in this embodiment, the provided first becomes necessarily VF ₀ = "1" period t ₀ of the subframe, and, VLC = 0 in the period t ₀
Since VCP = VCNT is set so as to satisfy the above condition, such a problem does not occur, and a desired voltage can be applied to the liquid crystal.

After the third frame in which the state of the memory becomes "000", the switch TFTs 81, 82 and 83 are always in the OFF state, and VLC = 0.

As described above, by using the present embodiment, the memory holding n pieces of display data can store 2n display data.
A low-power-consumption liquid crystal display device capable of displaying a gradation of a level can be provided.

Further, similarly to the first signal waveform in the first embodiment, the same effect can be obtained by using VCP as a signal voltage waveform having a cycle of one frame.

Further, similarly to the third signal waveform in the first embodiment, the period of the subframe is the same (T ₁ = T ₂ =
T ₃ ), the same effect can be obtained even if the VCP amplitude is changed for each subframe. Further, in this case, similar to the fourth signal waveform in the first embodiment, the same effect can be obtained even if the pulse width is changed instead of the amplitude of the VCP. Similarly, if the processing performed at n = 3 is changed to n, 2 ⁿ level gray scales can be displayed.

[0085]

According to the present invention, when realizing multi-gradation display in an active matrix liquid crystal display device having a built-in memory, the circuit configuration can be simplified, the yield is improved, and the manufacturing cost is reduced. Can be done.

Further, a counter electrode is formed in the structure of the present invention, the amplitude of the liquid crystal drive voltage applied to the counter electrode is substantially equal to each other, the frame period is divided into a plurality of sub-frames, and the divided sub-frames are divided. When the frame periods are formed to have different lengths, lower power consumption can be achieved. Further, when the amplitude of the liquid crystal drive voltage applied to the counter electrode is different from each other, and the frame period is divided into a plurality of sub-frames and the divided sub-frames are formed to have substantially the same period, 2 ⁿ When trying to produce a level gradation, it can be obtained only by the amplitude.

Further, if the liquid crystal driving voltage is made equal to the center voltage at the beginning of each subframe, the voltage of the pixel electrode becomes constant, and the malfunction of the first switching means can be prevented. Can be.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an entire configuration of an embodiment of a liquid crystal display device according to the present invention.

FIG. 2 is a block diagram showing a configuration of a pixel circuit 50 when three display data are applied to a data signal line group in one embodiment of the liquid crystal display device according to the present invention.

FIG. 3 is a circuit diagram for realizing a pixel circuit of the liquid crystal display device of FIG. 2;

4 is a timing chart showing a first signal waveform of a voltage applied to the liquid crystal display device of FIG.

FIG. 5 is a timing chart showing a second signal waveform of a voltage applied to the liquid crystal display device of FIG. 1;

FIG. 6 is a timing chart showing a third signal waveform of a voltage applied to the liquid crystal display device of FIG. 1;

FIG. 7 is a timing chart showing a fourth signal waveform of a voltage applied to the liquid crystal display device of FIG. 1;

FIG. 8 is a block diagram illustrating an overall configuration of a liquid crystal display device according to an embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of a pixel circuit 50 when three display data are applied to a data signal line group in one embodiment of the liquid crystal display device according to the present invention.

10 is a circuit diagram for realizing a pixel circuit of the liquid crystal display device of FIG.

FIG. 11 is a timing chart showing signal waveforms of voltages applied to the liquid crystal display device of FIG.

[Explanation of symbols]

1. Scanning circuit, 2. Data circuit, 3. Timing circuit,
4 ... Central voltage circuit, 5 ... Liquid crystal drive AC voltage source, 10 ... Memory, 11, 12, 13 ... Memory TFT, 14, 15,
16: memory capacity, 20: sample and hold circuit, 2
1, 22, 23 ... sampling TFT, 24 ... hold capacity, 30 ... first switching means, 31, 81, 8
2, 83, 84, 85, 86, 91 ... switch TFT,
40 ... pixel electrode, 50 ... pixel circuit, 60 ... liquid crystal, 70 ...
Counter electrode, 80 ... selection circuit, 90 ... switch, 100 ...
Scanning line, 200: data signal line group, 300: timing line group, 400: common line.

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Makoto Tsumura 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Within Hitachi Research Laboratory, Hitachi, Ltd. (56) References JP-A-7-64051 (JP, A) JP-A-7-253764 (JP, A) JP-A-9-212140 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G02F 1/1368 G02F 1/133 550 G09F 9/30 338 G09G 3/36

Claims (6)

(57) [Claims] 1. A liquid crystal display device comprising a pair of substrates, at least one of which is transparent, and a liquid crystal layer sandwiched between the pair of substrates, wherein one of the pair of substrates has a plurality of scanning lines and a plurality of the plurality of scanning lines. Surrounded by a plurality of data signal line groups intersecting the scanning lines in a matrix, a plurality of timing line groups formed between the plurality of scanning lines, and the plurality of scanning lines and the plurality of data signal line groups. And a memory connected to the corresponding scanning line and the data signal line group in the designated area, for taking in and holding display data from the data signal line group in response to the scanning signal, and connected to the memory, and connected to the memory. A sample-and-hold circuit that fetches the held data and whose output is controlled by a timing signal of a timing line group corresponding to the region, and a sample-and-hold circuit that is controlled by an output of the sample and hold circuit That a first switching means, a liquid crystal display device characterized by having its first pixel electrode connected to the switching means. 2. A liquid crystal display device comprising a pair of substrates at least one of which is transparent and a liquid crystal layer sandwiched between the pair of substrates, wherein one of the pair of substrates has a plurality of scanning lines and a plurality of the plurality of scanning lines. Surrounded by a plurality of data signal line groups intersecting the scanning lines in a matrix, a plurality of timing line groups formed between the plurality of scanning lines, and the plurality of scanning lines and the plurality of data signal line groups. And a memory connected to the corresponding scanning line and the data signal line group in the designated area, for taking in and holding display data from the data signal line group in response to the scanning signal, and connected to the memory, and connected to the memory. A selection circuit that fetches the held data and whose output is controlled by timing signals of the plurality of timing lines, a first switching unit that is controlled by an output of the selection circuit, The liquid crystal display device characterized by having a pixel electrode connected to the first switching means. 3. The liquid crystal display device according to claim 1, wherein the sample and hold circuit includes a plurality of second switching means connected to the memory. 4. The liquid crystal display according to claim 1, wherein the amplitudes of the liquid crystal driving voltages applied to the counter electrodes are substantially equal to each other, the frame period is divided into a plurality of subframes, and the length of the divided subframe period is increased. A liquid crystal display device characterized by different sizes. 5. The liquid crystal display device according to claim 1, wherein the amplitude of the liquid crystal driving voltage applied to the counter electrode is different from each other, a frame period is divided into a plurality of subframes, and a length of the divided subframe period is set. Are substantially equal to each other. 6. The liquid crystal display according to claim 1, wherein the waveforms of the liquid crystal driving voltages applied to the common electrodes are equal to each other, the frame period is divided into a plurality of subframes, and the length of the divided subframe period is Wherein the effective value of the voltage in the period of the sub-frame changes in proportion to the period of the sub-frame.