JP2013206512A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device capable of stably operating without reference to design sizes of respective transistors constituting a circuit and without margin design.SOLUTION: A semiconductor storage device includes: a D latch circuit 2 which has a D terminal (D), a clock terminal (φ), and a Q terminal (Q), passes the voltage of a data signal of the D terminal (D) through from a bit line when a write selection signal of the clock terminal (φ) is asserted or holds the voltage of the data signal when the write selection signal is negated, and outputs an inverted value of the passed-through/held voltage from the Q terminal (Q); and a memory cell 1 including a tristate buffer 3 connected between the Q terminal (Q) of the D latch circuit 2 and a data line (D), which outputs the inverted value of the voltage of the Q terminal (Q) to the bit line (D) when a read selection signal is asserted and generates an output in a high-impedance state when the read selection signal is negated.

Description

  The present invention relates to a semiconductor memory device used for an SRAM, and more particularly to a semiconductor memory device that can be easily designed for margin or can be margin-free designed even in a low power / ultrafine process.

  Conventionally, a 6-transistor SRAM memory cell (hereinafter referred to as “6T-SRAM”) has been widely used as a semiconductor memory device used in an SRAM (Static Random Access Memory). FIG. 9 is a diagram showing a basic circuit configuration of 6T-SRAM. For each 6T-SRAM, six MISFETs (Metal-Insulator-Semiconductor Field-Effect Transistors) (M1 to M6), two bit lines BL and BLB, and one word line WL are used. The MISFET (M1, M2) and the MISFET (M3, M4) constitute a CMIS (Complementary Metal-Insulator-Semiconductor) inverter (INV1, INV2), respectively, and the MISFET (M5, M6) is a word line ( WL) constitutes a transmission gate that is disconnected. The CMIS inverters (INV1, INV2) are cross-coupled with each other to form an inverter / latch circuit (flip-flop). The inputs of both CMIS inverters (INV1, INV2) are connected to the bit lines (BL, BLB) via transmission gates (M5, M6), respectively.

  At the time of read operation, the word line (WL) is set to the H level and the transmission gates (M5, M6) are turned on, so that the state values latched in the inverter latch circuit are set in the bit lines (BL, BLB). Is output. On the other hand, during the write operation, according to the write value, one of the bit lines (BL, BLB) is set to the H level and the other is set to the L level, and the write value is set. In this state, the word line (WL) is set to the H level. -Make the gates (M5, M6) conductive. As a result, a write value is set in the inverter / latch circuit.

  However, in recent years, with the miniaturization of integrated circuits and the reduction in voltage, problems of manufacturing variations of transistors (M1 to M6) used for CMIS inverters and transmission gates have become apparent. FIG. 10 is a diagram showing the transition of variations in power supply voltage and gate length with the progress of miniaturization of CMOS elements. As shown in FIG. 10, the lowering of the voltage of the CMOS element has progressed year by year, and the variation has increased accordingly. In 2010, the gate length variation has reached about 50% at 3σ / mean (a ratio of three times the standard deviation (σ) to the mean), and it can be easily estimated that the variation will increase further in the future. . As the variation increases, the operation margin of the SRAM decreases.

FIG. 11 shows (a) the relationship of the terminal voltage (CH, CL) of the inverter / latch circuit of FIG. 9 to the gate width of the transistors (M5, M6) of the transmission gate, and (b) at the time of reading the 6T-SRAM. It is a figure showing the noise margin. 11 (a), the horizontal axis represents the gate width _{W TN} transmission gates of the transistors (M5, M6), the terminal voltage CH of ordinate inverter latch circuit during a read / write (INV1, INV2) , CL (see FIG. 9). A dotted line (RD) is a terminal voltage at the time of reading, and a solid line (WT) is a terminal voltage at the time of writing. At the time of reading, sufficient reading is possible even when the gate width _WTN is small (the transmission gate resistance is large). However, as the gate width _WTN increases, the resistance of the transmission gate decreases, Since current leaks from each terminal of the latch circuit to the bit line (BL), the terminal voltage decreases. When the gate width W _TN exceeds a certain threshold value W _TNR , the data held in the inverter / latch circuit is destroyed at the moment of reading, so that the memory cell cannot be established. On the other hand, at the time of writing, if the gate width _WTN is too small, writing becomes impossible because the resistance of the transmission gate is large. Therefore, if the gate width W _TN is smaller than a certain threshold value W _TNW , writing cannot be performed and the memory cell cannot be established. Therefore, the allowable range of the gate width W _TN of the transmission gate transistors (M5, M6) is W _TNW <W _TN <W _TNR .

  FIG. 11B is a diagram showing a static noise margin (SNM) used as an index of the operation margin of the SRAM, and is a characteristic diagram generally called a butterfly curve (glasses characteristics). The horizontal and vertical axes in FIG. 11B represent the terminal voltages CL and CH of the inverter / latch circuit, respectively. Vs is the threshold voltage of the CMIS inverter (INV1, INV2). Also, the two curves shown in FIG. 11B represent voltage transfer curves (VTC) when the CMIS inverters (INV1, INV2) are read. The SNM at the time of reading is expressed by the length of the diagonal line of the square shown in FIG.

As described above, in the actual LSI manufacturing process, the performance variation of each transistor constituting the memory cell is large due to variations in gate length, fluctuations in impurities, and the like. Therefore, in designing the transistors (M5 and M6) described above. Therefore, it is necessary to design a margin in consideration of variations with respect to the optimum value of the gate width _WTN . At present, in this margin design, in many cases, the design is performed with the variation width of each transistor being about 20 to 50%. However, since there are millions of such memory cells mounted in the entire SRAM, a margin of variation of individual memory cells is overlapped. Therefore, in the near future, a design that expects a margin in the range of 1/10 to 10 times as a whole will be required.

  Therefore, it is clear that the current margin design will fail if the memory cell is further miniaturized and the voltage is lowered and the variation in transistor performance further increases. Therefore, there is a need for an SRAM memory cell (semiconductor memory device) capable of a margin-free design that is not affected by variations in transistor performance.

  As the semiconductor memory device, those described in Patent Documents 1 and 2 are known. FIG. 12 is a circuit diagram of the SRAM memory cell described in Patent Document 1. In FIG. In this memory cell, a write-only bit line (WBL, WBLB) and a read-only bit line (RBL, RBLB) are provided as bit lines, and a write-only bit is provided to each CMIS inverter (INV1, INV2). Transmission gates (WT1, WT2) for lines (WBL, WBLB) and transmission gates (RT1, RT2) for read-only bit lines (RBL, RBLB) are provided. In FIG. 12, a column selection line (CSL) is a line for selecting a column of a cell to which data is written. The column selection transistors (CT1, CT2) are column selection transmission gates that are disconnected by the voltage value of the column selection line (CSL).

Thus, by providing the read-only transmission gate (RT1, RT2) and the write-only transmission gate (WT1, WT2) independently, the gate width of the transmission gate at the time of writing, and at the time of reading It becomes possible to design the gate width of the transmission gate independently. Therefore, in FIG. 11, the gate width of the write transmission gates (WT1, WT2) may be equal to or greater than W _TNW , and the gate width of the read transmission gates (RT1, RT2) may be equal to or less than _WTNR. Therefore, the restriction on the allowable gate width becomes loose, and if the gate width is designed with a sufficient margin with respect to the allowable threshold _values W _TNW and W _TNR , it is possible to increase the design margin for the performance variation of each transmission gate. .

  In FIG. 12, the column of the memory cell to which writing is performed is selected by the column selection transistors (CT1, CT2). This is because the memory of the column other than the column to which writing is performed at the time of writing. This is to prevent the cell from being rewritten.

  FIG. 13 is a circuit diagram of the SRAM memory cell described in Patent Document 2. In the circuit of FIG. 13 as well, write-only bit lines (BLW, BLWB) and read-only bit lines (BLR) are provided, and write-only bit lines (BLW, BLV) are provided to the CMIS inverters (INV1, INV2). The transmission gate (WT1, WT2) for BLWB) and the transmission gate (RT1) and read transistor (RT2) for the read-only bit line (BLR) are provided. In this circuit, the write side is the same as the circuit of FIG. 12, but the read side does not directly connect the output of the inverter / latch circuit to the read-only bit line (BLR), but a high-impedance read transistor ( RT2) is connected to a read-only bit line (BLR) via a transmission gate (RT1). Thus, like the circuit of FIG. 12, the read-only transmission gate (RT1) and read transistor (RT2) and the write-only transmission gates (WT1, WT2) are provided independently, so that The gate width of the transmission gate and the gate width of the transmission gate at the time of reading can be designed independently. Further, since the latched value is output through the gate of the high impedance read transistor (RT2) at the time of reading, there is no possibility that the state value held by the inverter / latch circuit at the time of reading is destroyed.

JP 2010-277634 A WO2008 / 32549

Yoshiyuki Takeishi, supervised by Hiroshi Hara, “Introduction to VLSI Series 5 Basics of MOS Integrated Circuits”, First Edition, Modern Science, May 1992, p. 65. Takakuni Doseki, Shinichiro Muto, “Static noise margin analysis of fine CMOS memory cells”, IEICE Transactions, Institute of Electronics, Information and Communication Engineers, July 1992, C-II, Vol. J75-C-II, No. 7, pp. 350-361.

  However, in the conventional semiconductor memory device described above, the memory cell is used in both cases or one of the cases of inverting the data in the memory holding unit constituted by the latch / inverter and reading the data held in the latch / inverter. In all the transistors to be configured, or a part of the transistors, design restrictions, so-called ratio design, are necessary in the selection range of the gate size (gate width / gate length), and the performance variation of each transistor is considered. On the other hand, in order to operate stably, it is necessary to secure a design margin, and there has been a problem that there is a risk of failure in the future in the increase in performance variation of transistors.

  Therefore, an object of the present invention is a semiconductor capable of stable operation without depending on the design size (gate width / gate length) of each transistor constituting the circuit and without performing a composite margin design between the transistors. To provide a storage device.

A semiconductor memory device according to the present invention includes a word line pair consisting of a pair of a read word line and a write word line,
A bit line crossing the word line pair;
A memory cell provided corresponding to an intersection of the word line pair and the bit line,
The memory cell is
A write selection signal having a D terminal, a clock terminal, and a Q terminal, wherein the D terminal and the clock terminal are connected to the bit line and the write word line, respectively, and input from the write word line to the clock terminal Is asserted, the logic level voltage of the data signal input from the bit line to the D terminal is passed through. When the write selection signal is negated, the logic level voltage of the data signal is held, and is passed through or held. A D latch circuit that outputs a logic level voltage or an inverted voltage thereof from the Q terminal;
An input terminal, a control terminal, and an output terminal; the input terminal is connected to the Q terminal of the D latch circuit; the control terminal is connected to the read word line; and the output terminal is connected to the bit line When the logic level voltage of the read selection signal input from the read word line to the control terminal is asserted, the logic level of the input terminal or its inverted value is output from the output terminal to the bit line. And a three-state buffer whose output state becomes a high impedance state when the logic level voltage of the read selection signal is negated.

  According to this configuration, each memory cell that holds data input from the bit line is configured using the D latch circuit and the three-state buffer, thereby writing data into the memory cell and data from the memory cell. In both read operations, the operation of the memory cell is a digital operation. Basically, whether or not the operation is possible does not depend on the design value (gate width / gate length) of each transistor constituting the memory cell. Therefore, it is only necessary to design a margin independently for each transistor, and there is no need for a complex margin design between the transistors.

  Here, “assert” means that a signal and logic become effective (that is, when an H active signal is asserted, the signal becomes a digital H level. When an L active signal is asserted, the digital L level is asserted. become). “Negate” means that the signal and logic are invalidated (ie, negating an H active signal goes to a digital L level; negating an L active signal goes to a digital H level) . “Through the logic level voltage” means that the logic level voltage input to the data input terminal passes through the data output terminal as it is.

In the present invention, the D latch circuit is provided between the D terminal and the Q terminal, and the first inverter and the second inverter in which the input terminal and the output terminal are connected in a loop. An inverter loop including: a loop gate circuit that is a transfer gate inserted into the inverter loop; and an input gate circuit that is a transfer gate inserted between the D terminal and the inverter loop; With
The loop gate circuit has its control terminal connected to the write word line, and becomes conductive when the write selection signal is negated, and non-conductive when asserted.
The input gate circuit may be configured such that its control terminal is connected to the write word line and is rendered conductive when the write selection signal is asserted and non-conductive when negated.

In the present invention, the three-state buffer is
A high impedance input circuit receiving the output voltage of the D latch circuit input from the input terminal with high impedance;
Connected between the output terminal of the high-impedance input circuit and the bit line, and disconnected so as to be conductive when the read selection signal input from the control terminal is asserted and non-conductive when negated. And an output gate circuit for performing the above.

  In the present invention, the high impedance input circuit may be a CMIS inverter or a single-channel MISFET whose source is grounded.

Further, in the present invention, a plurality of the word line pairs and a plurality of the bit lines are arranged in a lattice shape, and the memory cells are provided corresponding to the respective intersections of the two,
An external data output terminal for outputting the logic level voltage of the read data to the outside;
An external data input terminal for inputting the logic level voltage of the write data from the outside;
A column address input terminal for externally inputting a column address signal for selecting a column of the bit line connected to a memory cell for writing or reading data;
A latch terminal for inputting a latch control signal from the outside;
The external data input terminal is connected to each bit line, the external data output terminal, the external data input terminal, the column address input terminal, and the latch terminal, and according to the column address signal input to the column address input terminal. And a column selection circuit for connecting the external data output terminal to any one of the bit lines,
The column selection circuit includes an output selector, a plurality of data hold circuits and a plurality of write selectors provided for each of the bit lines,
The output selector has a plurality of input terminals, one output terminal, and a selection control terminal, each input terminal is connected to each bit line, and the output terminal is connected to the external data output terminal, A multiplexer that connects the selection control terminal to the column address input terminal and connects any one of the bit lines to the external data output terminal in accordance with the column address signal input from the column address input terminal And
Each data hold circuit has a D terminal, a clock terminal, and a Q terminal, the D terminal is connected to the corresponding bit line, the clock terminal is connected to the latch terminal, A D latch circuit that latches a logic level voltage of the corresponding bit line in accordance with the input latch control signal and outputs the latched voltage to the Q terminal;
Each of the write selectors has two input terminals, one output terminal, and a selection control terminal, and each of the input terminals is connected to the external data input terminal and the corresponding Q terminal of the data hold circuit. When the output terminal is connected to the corresponding bit line, the selection control terminal is connected to the column address input terminal, and the corresponding bit line is selected by the column address signal, The external data input terminal is connected, and in other cases, the multiplexer can be connected to the Q terminal of the data hold circuit corresponding to the bit line.

  According to this configuration, it is possible to perform a read / write operation on each memory cell as follows.

  (1) During a read operation, first, a bit line connected to a memory cell from which data is read (hereinafter referred to as “read target memory cell”) is connected to a column address input terminal (hereinafter referred to as “bit line of read column”). A column address signal for selecting a column is input. As a result, the output selector connects the bit line of the read column to the external data output terminal. Next, a read selection signal of a read word line connected to the read target memory cell (hereinafter referred to as “read word line of read row”) is asserted. As a result, the three-state buffers of all the memory cells connected to the read word line of the read row (hereinafter referred to as “memory cells of the read row”) become conductive, and are held in the D latch circuit of the memory cells of each read row ( The held logic level voltage is output to the bit line connected to the memory cell. At this time, since the bit line of the read column is connected to the external data output terminal, the logic level voltage held in the D latch circuit of the memory cell to be read is output to the external data output terminal. . As a result, data can be read from the read target memory cell.

  (2) On the other hand, during a write operation, first, a read selection signal of a read word line (hereinafter referred to as a “write word read word line”) connected to a memory cell to be written (hereinafter referred to as a “write target memory cell”). Is asserted. As a result, the three-state buffers of all the memory cells connected to the read word line of the write row (hereinafter referred to as “write row memory cells”) are turned on and held in the D latch circuit of the memory cell of each write row ( The held logic level voltage is output to the bit line connected to the memory cell. Next, the latch control signal of the latch terminal is asserted for a predetermined time. As a result, the data hold circuit connected to each bit line latches the logic level voltage of the bit line and outputs it to one input terminal of the corresponding write selector. Next, the read selection signal of the read word line of the write row is negated, and the logic level voltage of the write data is input to the external data input terminal. Then, a column address signal for selecting a bit line (hereinafter referred to as a “write column bit line”) connected to the write target memory cell is input to the column address input terminal. Thereby, the write selector connects the bit line of the write column to the external data input terminal, and the bit line of the write column becomes the logic level voltage of the write data. The other bit lines are maintained while being constrained by the logic level voltage held in the data hold circuit (that is, the logic level voltage currently held in each memory cell in the write row). Next, a write selection signal of a write word line (hereinafter referred to as “write word line of write row”) connected to the write target memory cell is asserted for a predetermined time. Thereby, the D latch circuits of all the memory cells connected to the write word line of the write row hold the logic level voltage of the corresponding bit line. At this time, the logic level voltage of the write data is held in the write target memory cell, and the currently held logic level voltage is held again in the other memory cells. As a result, data can be written in the write target memory cell.

  As described above, during the write operation, for the memory cells in the write row other than the write target memory cell, the logic level voltage of the bit line is restricted to the currently held logic level voltage by the data hold circuit. During operation, an error such that a memory cell in a write row other than the write target memory cell is rewritten by mistake is prevented.

  As described above, according to the present invention, each memory cell that holds data is configured using the D latch circuit and the three-state buffer, so that the design value (gate width / gate length) of each transistor that configures the circuit is achieved. It is possible to provide a semiconductor memory device capable of performing a margin-free design regardless of ().

1 is a circuit block diagram illustrating a configuration of a memory cell and its periphery in a semiconductor memory device according to Example 1 of the invention. FIG. 2 is a circuit diagram showing an internal configuration of a memory cell 1 in FIG. 1 at a transistor level. 1 is a circuit block diagram illustrating an overall configuration of a semiconductor memory device according to Example 1 of the invention. 4 is a time chart of each signal during a read operation of the circuit of the semiconductor memory device of FIG. 3. 4 is a time chart of each signal of a selected memory cell during a write operation of the circuit of the semiconductor memory device of FIG. 4 is a time chart of each signal of a non-selected memory cell (a non-selected memory cell in the same row as a selected memory cell) during a write operation of the circuit of the semiconductor memory device of FIG. FIG. 6 is a circuit diagram illustrating a configuration of a memory cell of a semiconductor memory device according to Example 2 of the invention. It is a circuit block diagram showing the whole structure of the semiconductor memory device based on Example 3 of this invention. It is a figure showing the basic circuit structure of the conventional 6T-SRAM. It is a figure showing the transition of the dispersion | variation in the power supply voltage and gate length accompanying progress of miniaturization of a CMOS element. (A) The relationship of the terminal voltage (CH, CL) of the inverter / latch circuit of FIG. 14 to the gate width of the transfer gate transistors (M5, M6), and (b) the noise margin at the time of 6T-SRAM read. FIG. 2 is a circuit diagram of an SRAM memory cell described in Patent Document 1. FIG. 6 is a circuit diagram of an SRAM memory cell described in Patent Document 2. FIG.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

  FIG. 1 is a circuit block diagram showing a configuration of a memory cell and its peripherals in a semiconductor memory device according to Embodiment 1 of the present invention.

  In FIG. 1, a semiconductor memory device includes a word line pair which is a pair of a read word line (RWn) and a write word line (WWn) (n = 1, 2,...), And a bit line (Dm) (m = 1, 2,... Are arranged in a grid pattern (see FIG. 3), and the memory cells 1 are arranged at the intersections of the word line pairs and the bit lines (Dm). A read selection signal is input to the read word line (RWn). A write selection signal is input to the write word line (WWn). A data signal is input to the bit line (Dm), and a read data signal is output from the bit line (Dm).

  Each memory cell 1 includes an inverted output D latch circuit 2 and an inverted output three-state buffer 3.

The D latch circuit 2 includes a D terminal (D) connected to the bit line (Dm), a clock terminal (φ) connected to the write word line (WWn), and a Q terminal (Q ₋ ).

When the write selection signal input to the clock terminal (φ) is asserted, the D latch circuit 2 passes the logic level voltage of the data signal input from the D terminal (D), and when the write selection signal is negated. Holds the logic level voltage of the data signal. The D latch circuit 2 outputs the latched logic level voltage from the Q terminal (Q ₋ ). In this embodiment, the inverted value of the latched logic level voltage is output from the Q terminal (Q ₋ ). However, in the present invention, a non-inverted value is output. It may be configured.

The three-state buffer 3 has an input terminal connected to the Q terminal (Q ₋ ) of the D latch circuit 2, an output terminal connected to the bit line (Dm), and a control terminal connected to the read word line (RWn). Connected inverting output three-state buffer. When the read selection signal input from the control terminal is asserted, the three-state buffer 3 outputs the inverted value of the logic level voltage of the Q terminal (Q ₋ ) of the D latch circuit 2 to the bit line (Dm), and reads it. When the selection signal is negated, the output is in a high impedance state. Note that when the non-inverted value of the logic level voltage latched from the Q terminal (Q ₋ ) is output, a non-inverted output three-state buffer is used as the three-state buffer 3.

In the block diagram of FIG. 1, the write word line (WWn) and the clock terminal (φ) of the D latch circuit 2 are shown as one line and one terminal for the sake of convenience. Like a circuit, a write word line (WWn) is a pair of a write word line (WWn ₊ ) to which a non-inverted value of a write selection signal is input and a write word line (WWn ₋ ) to which an inverted value of the write selection signal is input. Are mounted as two terminals (φ ₊ , φ ₋ ) corresponding to each write word line (WWn ₊ , WWn ₋ ). Similarly, in the block diagram of FIG. 1, the read word line (RWn) and the control terminal of the three-state buffer 3 are also shown as one line and one terminal for the sake of convenience. As described above, the read word line (RWn) is used as a pair of a read word line (RWn ₊ ) to which the non-inverted value of the read selection signal is input and a read word line (RWn ₋ ) to which the inverted value of the read selection signal is input. When mounting, the control terminal (ENB) is mounted as two terminals (ENB ₊ , ENB ₋ ) corresponding to each read word line (RWn ₊ , RWn ₋ ).

  FIG. 2 is a circuit diagram showing the internal configuration of the memory cell 1 of FIG. 1 at the transistor level. 2A shows the internal configuration of the memory cell 1, and FIGS. 2B and 2C show other configuration examples of the three-state buffer 3. FIG. The D latch circuit 2 includes CMIS inverters 4 and 5, a loop gate circuit 6, and an input gate circuit 7. In the circuit of the memory cell 1 in FIG. 2, the case where both the read selection signal and the write selection signal are H active signals is illustrated, but in the present invention, the read selection signal and the write selection signal are L active. Of course, it is also possible to construct a circuit as the signal.

In FIG. 2, the write word line (WWn) of FIG. 1 is divided into a write word line (WWn ₊ ) to which a non-inverted value of a write selection signal is input and a write word line to which a non-inverted value of a write selection signal is input Although a pair of (WWn ₋ ) is used, it is of course possible to configure one write word line (WWn) (only WWn ₊ ) (in this case, each memory cell 1 has a write word line (WWn ₊ )). An inverter that generates an inverted signal (WWn ₋ ) of the signal is required). In FIG. 2, the read word line (RWn) of FIG. 1 is divided into a read word line (RWn ₊ ) to which a non-inverted value of a read selection signal is input and a read word line to which a non-inverted value of a read selection signal is input. Although a pair of (RWn ₋ ) is used, it is of course possible to configure one read word line (RWn) (only RWn ₊ ) (in this case, each memory cell 1 has a read word line (RWn ₊ )). An inverter that generates an inverted signal (RWn ₋ ) of the signal is required).

An output terminal 4 b of the CMIS inverter 4 is connected to the input terminal 5 a of the CMIS inverter 5. The loop gate circuit 6 is a transmission gate in which the channels of the nMISFET (M1) and the pMISFET (M2) are connected in parallel. The output terminal 5 b of the CMIS inverter 5 is connected to the input terminal 4 a of the CMIS inverter 4 through the channel of the loop gate circuit 6. The gate of the pMISFET (M2) of the loop gate circuit 6 corresponds to the clock terminal (φ ₊ ) of the D latch circuit 2 and is connected to the write word line (WWn ₊ ). The gate of the nMISFET (M1) of the loop gate circuit 6 is , Corresponding to the clock terminal (φ ₋ ) of the D latch circuit 2 and connected to the write word line (WWn ₋ ). As a result, the loop gate circuit 6 is turned on (the channel is turned on) and asserted when the write selection signal input from the write word line (WWn ₊ , WWn ₋ ) is negated (at the L level). Turns off (when channel is H) (channel is non-conductive). The CMIS inverters 4 and 5 form an inverter loop by interposing the loop gate circuit 6 and cross-coupling (connecting in a loop) the output and the input to each other.

The output terminal 4 b of the CMIS inverter 4 corresponds to the Q terminal (Q ₋ ) and is connected to the input terminal of the three-state buffer 3. Therefore, the inverted value of the logic level voltage latched by the inverter loop including the CMIS inverters 4 and 5 is output from the Q terminal (Q ₋ ) to the input terminal of the three-state buffer 3.

The input gate circuit 7 is a transmission gate in which the channels of the nMISFET (M3) and the pMISFET (M4) are connected in parallel, and both terminals of the channel are connected between the bit line (Dm) and the input terminal 4a of the CMIS inverter 4. Has been. Therefore, the node of the input gate circuit 7 on the side connected to the bit line (Dm) corresponds to the D terminal (D) of the D latch circuit 2. The gate of the nMISFET (M3) of the input gate circuit 7 corresponds to the clock terminal (φ ₊ ) and is connected to the write word line (WWn ₊ ), and the gate of the pMISFET (M4) of the input gate circuit 7 is the clock terminal (φ ₋ ). Is connected to a write word line (WWn ₋ ). As a result, the input gate circuit 7 is turned off (the channel is non-conductive) and asserted when the write selection signal input from the write word line (WWn ₊ , WWn ₋ ) is negated (at the L level). (On the H level), the channel is turned on.

The three-state buffer 3 includes an output gate circuit 9 and a high impedance input circuit 11. The high impedance input circuit 11 is an input circuit that receives the output voltage of the D latch circuit input from the input terminal with high impedance. In the present embodiment, the high impedance input circuit 11 is constituted by a CMIS inverter. The output gate circuit 9 is a transmission gate configured by connecting the channels of the nMISFET (M5) and the pMISFET (M6) in parallel. The gate of the nMISFET (M5) corresponds to the control terminal (ENB ₊ ) and is a read word. is connected to line (RWn _+), the gate of pMISFET (M6) is a control terminal is connected to (ENB _{- -)} the corresponding read word line (RWn).

The input terminal of the output gate circuit 9 is connected to the input terminal (in) of the three-state buffer 3 via the high impedance input circuit 11, and the output terminal of the output gate circuit 9 is the output of the three-state buffer 3. It is connected to a terminal (out). The input terminal (in) of the three-state buffer 3 is connected to the Q terminal (Q ₋ ) of the D latch circuit 2, and the output terminal (out) of the three-state buffer 3 is connected to the bit line (Dm). Has been.

2A shows an example in which the three-state buffer 3 is composed of a combination of an inverter and a transfer gate. However, when actually mounted, the three-state buffer 3 is not shown in FIG. As shown, the pMISFET (M6), pMISFET (M7), nMISFET (M8), and nMISFET (M5) are connected in series between the power source (VDD) and the ground (GND), and the power source (VDD) is connected. And a configuration in which the gates of the pMISFET (M6) and nMISFET (M5) on the side closer to the ground (GND) are used as control terminals (ENB ₋ , ENB ₊ ), and the power supply (VDD) and the ground as shown in FIG. PMISFET (M7), pMISFET (M6), nMISFET (M5), nMISFET (M8) The scan-drain connected in series, the power supply (VDD) and the ground far from (GND) pMISFET (M6), a gate control terminal of _{nMISFET (M5) (ENB -,} ENB +) and the such equivalent as It can also be replaced with a configuration.

  Also, the CMIS inverter 5 and the loop gate circuit 6 shown in FIG. 2A can have equivalent configurations similar to those shown in FIGS.

  FIG. 3 is a circuit block diagram showing the overall configuration of the semiconductor memory device according to the first embodiment of the invention. 3, the semiconductor memory device according to the first embodiment includes a word line pair (Wn) that is a pair of a read word line (RWn) (n = 1, 2,...) And a write word line (WWn), and a bit line ( Dm) (m = 1, 2,...) Are arranged in a grid pattern with each word line pair (Wn) as a row and each bit line (Dm) as a column. A memory cell 1 of FIG. 1 is disposed at each intersection of each word line pair (Wn) and each bit line (Dm). A column selection circuit 12 is connected to one end of each bit line (Dm).

  The column selection circuit 12 includes an external data input terminal (Din), an external data output terminal (Dout), a latch terminal (LAT), and a column address input terminal (Y0). From an external data input terminal (Din), a logic level voltage of data to be written in any one of the memory cells 1 is input. From the external data output terminal (Dout), a logic level voltage of data read from any one of the memory cells 1 is output. A column address signal for selecting a bit line (Dm) (m = 1, 2,...) Connected to a memory cell to which data is written or read is input to the column address input terminal (Y0). . A latch control signal for instructing the column selection circuit 12 to latch the logic level voltage of the data signal input to each bit line (Dm) is input to the latch terminal (LAT).

The column selection circuit 12 has a data selector 15-1, 15 comprising a write selector 13-1, 13-2,... And a D latch circuit for each bit line (D1, D2,...). -2, ... are provided. These write selectors 13-m (m = 1, 2,...) Have two input terminals (in ₁ , in _1m ) at one end of the bit line (Dm) corresponding to the output terminal (out _m ). Each is a multiplexer in which a selection control terminal (sel _m ) is connected to a column address input terminal (Y0) to an external data input terminal (Din) and a Q terminal (Q) of the data hold circuit 15-m. Each of these write selectors 13-m (m = 1, 2,...) Connects the connected bit line (Dm) to the external data input terminal (Din) or the Q terminal (Q of the data hold circuit 15-m. ) Selectively connect to any of the above. Each of the write selectors 13-m (m = 1, 2,...) Is switched in connection direction by a column address signal input from the column address input terminal (Y0). The write selector 13-m connects the bit line (Dm) to the external data input terminal (Din) when the column m of the bit line (Dm) to be connected is the column selected by the column address signal. In other cases, the bit line (Dm) is connected to the Q terminal (Q) of the data hold circuit 15-m. That is, the column selection circuit 12 connects the selected bit line (Di) to the external data input terminal (Din) according to the column address signal, and other bit lines (Dj) (j ≠ i) correspond to the corresponding data. It operates to connect to the Q terminal (Q) of the hold circuit 15-j.

Each data hold circuit 15-m (m = 1, 2,...) Is a D latch circuit having a D terminal (D _h ), a clock terminal (φ _h ), and a Q terminal (Q _h ). Each data hold circuit 15-m has a D terminal (D _h ) connected to a corresponding bit line (Dm), a clock terminal (φ _h ) connected to a latch terminal (LAT), and a Q terminal (Q _h ) It is connected to one input terminal (in _1m ) of the corresponding write selector 13-m. These data hold circuits 15-m latch the logic level voltage of the corresponding bit line (Dm) according to the latch control signal input from the latch terminal (LAT) and output it to the Q terminal (Q _h ).

The column selection circuit 12 includes an output selector 14 that selectively connects a bit line (Di) selected by a column address signal input from a column address input terminal (Y0) to an external data output terminal (Dout). ing. The output selector 14 has a plurality of input terminals (in _o1 , in _o2 ,...) On each bit line (D1, D2,...), An output terminal (out _o ) on an external data output terminal (Dout), and a selection control terminal. (Sel _o ) is a multiplexer connected to the column address input terminal (Y0). The output selector 14 selectively connects the bit line (Dm) of the column indicated by the column address signal to the external data output terminal (Dout) according to the column address signal input from the column address input terminal (Y0).

  The operation of the semiconductor memory device according to this embodiment configured as described above will be described below.

(1) Read Operation FIG. 4 is a time chart of each signal during the read operation of the circuit of the semiconductor memory device of FIG. FIG. 4 shows, as an example, a case where data is read from the memory cell 1 in the first row and the second column (the memory cell labeled B in FIG. 3). Note that the node potential (N_11) in FIG. 4 represents the potential of the node (N_11) in the memory cell 1 in the first row and the first column shown in FIG. 3 (the memory cell denoted by reference symbol A in FIG. 3). .

  (1.1) When reading data, first, a column address signal for selecting a column of a cell to be read is input to a column address input terminal (Y0). Thus, the output selector 14 connects the bit line (D2) of the selected column to the external data output terminal (Dout).

(1.2) Next, the read selection signal of the read word line (RW1) of the row of the cell to be read is asserted (set to H level). As a result, the three-state buffers 3 of all the memory cells 1 (the memory cells 1 in the first row) connected to the read word line (RW1) become conductive, and each bit line (Dm) (m = 1, 2). ,..., The logic level voltages D _old11 , D _old12 ,... _Latched in each memory cell 1 in the first row are output. At this time, since only the selected bit line (D2) is connected to the external data output terminal (Dout), the external data output terminal (Dout) is latched by the memory cell 1 in the first row and the second column. The logic level voltage D _old12 is output.

  Through the operation as described above, the data latched in the selected memory cell 1 is read.

(2) Write Operation FIG. 5 is a time chart of each signal of the selected memory cell during the write operation of the circuit of the semiconductor memory device of FIG. 3, and FIG. 6 is the write operation of the circuit of the semiconductor memory device of FIG. 10 is a time chart of signals of unselected memory cells (unselected memory cells in the same row as a selected memory cell) in FIG. 5 and 6, as an example, a case where data is written to the memory cell 1 in the first row and the second column (the memory cell labeled B in FIG. 3) is shown.

(initial state)
5, in the initial state, the latch terminal (LAT), each read word line (RWn) (n = 1, 2,...), And each write word line (WWn) (n = 1, 2,...) Are negated ( L level). Further, no column address signal is input to the column address input terminal Y0.

(Write preparation stage: times t1 to t6)
When data is written, in order to prevent the data latched in each cell of the row to which the cell to be written belongs from being lost, first, as a write preparation stage, each cell in the row is subjected to the following operation. The latched data is latched in the data hold circuits 15-1, 15-2,.

(2.1) The read selection signal of the read word line (RW1) of the row to which the memory cell 1 to be written belongs is asserted (set to H level) (time t1). As a result, the bit lines (D1, D2,...) Of each column are latched in the memory cells 1 (the memory cells 1 in the first row) connected to the selected read word line (RW1). The logic level voltages D _old11 , D _old12 ,... _Are output (time t2).

  At this time, since the column address signal has not yet been input to the column address input terminal (Y0), the write selectors 13-m (m = 1, 2,...) Of all the columns have corresponding data hold circuits. 15-1, 15-2,... Are connected to Q terminals (Q).

(2.2) Next, the latch control signal of the latch terminal (LAT) is asserted (set to H level) (time t3). As a result, the clock terminals (φ _h ) of the data hold circuits 15-1, 15-2,... Corresponding to the bit lines (D1, D2,...) Are asserted, and the data hold circuits 15-1, 15-2 are asserted. ,... _Pass the voltage level of the D terminal (D _h ) through the Q terminal (Q _h ). Therefore, the logic level voltages D _old11 , D _old12 ,... _Are output to the nodes (in ₁₁ , in ₁₂ ,...) In FIG. 3 (time t4).

(2.3) After a predetermined time has elapsed, the latch control signal of the latch terminal (LAT) is negated (set to L level) (time t5). Thus, the data hold circuits 15-1, 15-2, ... of the clock terminal (phi _h) is negated, the voltage level of the data hold circuits 15-1, 15-2, ... is D terminal _{(D h)} Latch. Therefore, the logic level voltages D _old11 , D _old12 ,... _{Are held at} the nodes (in ₁₁ , in ₁₂ ,...). Since each of the write selectors 13-m (m = 1, 2,...) Is connected to the nodes (in ₁₁ , in ₁₂ ,...), The voltage of each bit line (D1, D2,...) The levels are constrained to the logic level voltages D _old11 , D _old12 ,... By the corresponding data hold circuits 15-1, 15-2 _,.

(Writing stage: from time t6)
(2.4) Next, with negates read word line rows of write (RW1), and inputs the logical level voltage _{D new new} write data to be written to the external data input terminal (Din) (time t6) . At this time, since the column address signal is not yet inputted to the column address input terminal (Y0), the write data of the external data input terminal (Din) is inputted to the bit lines (D1, D2,...). Absent.

(2.5) Next, a column address signal for selecting a column of cells to be written is input to the column address input terminal (Y0) (time t7). Thereby, the write selector 13-2 of the selected column connects the bit line (D2) to the external data input terminal (Din) (time t8). In the other write selector 13-j (j ≠ 2), the bit line (Dj) is connected to the Q terminal (Q _h ) of the corresponding data hold circuit 15-j. Thus, the selected column of bit lines (D2) is a logic level voltage _{D new new} write data (time t8). On the other hand, the bit line (Dj) (j ≠ 2) of the column not selected becomes a _trap that is constrained to the _original logic level voltage _Dold1j by the data hold circuit 15-j.

(2.6) Next, the write selection signal of the write word line (WW1) of the row to be written is asserted (set to H level) (time t9). Thus, the D latch circuits 2 of all the memory cells 1 in the selected row (first row) are set to the bit line (Dm) of the column m (m = 1, 2,...) To which the memory cell 1 belongs. output voltage terminal Q _- to be through. At this time, the bit line (D2) of the selected column, since the logic level voltage D _{new new} write data has been set, first row second column of the memory cell 1 (the sign B in FIG. 3 is subjected and the D latch circuit 2 of the memory cell) is set the logic level voltage _{D new new} (time t10), accordingly, the voltage of the node N_12 of the memory cell 1 is the inverted value of the logical level voltage _{D new new.} On the other hand, the logic level voltage _Dold1j latched in the memory cell 1 and the data hold circuit 15-j in the selected row (first row) is applied to the bit line (Dj) (j ≠ 2) of the column not selected. Since it is set, the set voltage of the D latch circuit 2 of the memory cell 1 in the first row and j column is maintained as it is.

  (2.7) Next, the write selection signal of the write word line (WW1) is negated (set to L level). Thereby, the D latch circuit 2 of each memory cell 1 in the first row latches the voltage of the bit line (Dj) at that time (time t11).

  (2.8) Finally, the input of the column address signal is stopped (time t12). As a result, the write selector 13-m (m = 1, 2,...) Is not selected (time t12).

  Through the above operation, new data is written in the memory cell 1 in the first row and the second column, and the memory cell 1 in the first row and the first column holds the previous data.

  As described above, in the semiconductor memory device of this embodiment, each memory cell 1 uses the D latch circuit 2 and the three-state buffer 3, and the three-state buffer 3 receives the output of the D latch circuit 2 with high impedance. By separating the output of the D latch circuit 2 from the bit line (Dm), the design value (gate width / gate length) of each transistor (M3, M4) used in the input gate circuit 7 of the D latch circuit 2 The design value (gate width / gate length) of each transistor (M5, M6) used in the output gate circuit 9 can be determined completely independently. Therefore, the design can be performed without being restricted by the design value (gate width / gate length) of each transistor (M3, M4, M5, M6). Further, since the design is possible regardless of the design value (gate width / gate length) of each transistor (M3, M4, M5, M6), each transistor (M3, M4, M5, M6) and each inverter circuit are connected. It is also possible to design the constituent transistors as the minimum size of the process. Therefore, as a result, the circuit can be downsized as a whole.

FIG. 7 is a circuit diagram showing the configuration of the memory cell of the semiconductor memory device according to the second embodiment of the present invention. In FIG. 7, a read word line (RWn), a write word line (WWn, WWn ₊ , WWn ₋ ), a bit line (Dm), a D latch circuit 2, CMIS inverters 4, 5, a loop gate circuit 6, and an input gate circuit 7 is the same as that of FIG. 1, FIG. Moreover, each transistor M1-M4 of FIG. 8 respond | corresponds to the thing of the same sign of FIG.

  In the semiconductor memory device of this embodiment, the configuration of the three-state buffer 3 of the memory cell 1 is different from that of the first embodiment. That is, in the three-state buffer 3 of this embodiment, the high-impedance input circuit 11 is composed of a single channel MISFET (M7), and the output gate circuit 9 is also composed of a single channel MISFET (M8). . Here, the single channel MISFET means only an N channel MISFET or only a P channel MISFET. Since the output gate circuit 9 is a single channel, only one read word line (RWn) is required.

  Even with this configuration, the same effects as those of the first embodiment can be obtained. In the circuit configuration of this embodiment, compared to the first embodiment (FIG. 2), at least two transistors can be reduced per memory cell 1, and the read word line can be reduced by one for each row. it can.

  FIG. 8 is a circuit block diagram showing the overall configuration of the semiconductor memory device according to the third embodiment of the present invention. In FIG. 8, the same components as those in FIG. In the semiconductor memory device of this embodiment, the column selection circuit 12 includes a precharge control terminal PC to which a precharge signal is input, and the precharge transistors 16-1 and 16-2 correspond to the bit lines D1, D2,. The point provided with 16-2,... Is different from FIG. Each of the precharging transistors 16-1, 16-2,... Is a single-channel PMOSFET, whose source and drain are connected to the power supply VDD and each of the bit lines D1, D2,. Connected to PC. When the precharge signal is asserted (L level), each bit line D1, D2,... Is connected to the power supply VDD, and each bit line D1, D2,. As a result, each memory cell 1 and each data hold circuit 15-1, 15-2,... In the column selection circuit 12 can be initialized.

DESCRIPTION OF SYMBOLS 1 Memory cell 2 D latch circuit 3 Three-state buffer 4, 5 CMIS inverter 6 Loop gate circuit 7 Input gate circuit 8 Inverter 9 Output gate circuit 11 High impedance input circuit 12 Column selection circuit 13-1, 13-2, ... Selector 14 output selectors 15-1, 15-2,... Data hold circuits 16-1, 16-2,... Precharge transistors RWn, RWn ₊ , RWn _- read word lines WWn, WWn ₊ , WWn _- write words Line D1, D2, ... Bit line D Data input terminal φ Clock terminal Q _- Output terminal Din External data input terminal Dout External data output terminal Y0 Column address input terminal

LAT Latch terminal PC Precharge control terminal

Claims (5)

A word line pair consisting of a pair of a read word line and a write word line;
A bit line crossing the word line pair;
A memory cell provided corresponding to an intersection of the word line pair and the bit line,
The memory cell is
A write selection signal having a D terminal, a clock terminal, and a Q terminal, wherein the D terminal and the clock terminal are connected to the bit line and the write word line, respectively, and input from the write word line to the clock terminal Is asserted, the logic level voltage of the data signal input from the bit line to the D terminal is passed through. When the write selection signal is negated, the logic level voltage of the data signal is held, and is passed through or held. A D latch circuit that outputs a logic level voltage or an inverted voltage thereof from the Q terminal;
An input terminal, a control terminal, and an output terminal; the input terminal is connected to the Q terminal of the D latch circuit; the control terminal is connected to the read word line; and the output terminal is connected to the bit line When the logic level voltage of the read selection signal input from the read word line to the control terminal is asserted, the logic level of the input terminal or its inverted value is output from the output terminal to the bit line. A semiconductor memory device comprising: a three-state buffer whose output state becomes a high impedance state when the logic level voltage of the read selection signal is negated. The D latch circuit is
An inverter loop including a first inverter and a second inverter provided between the D terminal and the Q terminal and having an input terminal and an output terminal connected to each other in a loop;
A loop gate circuit which is a transfer gate inserted in the inverter loop;
An input gate circuit that is a transfer gate inserted between the D terminal and the inverter loop;
The loop gate circuit has a control terminal connected to the write word line, and is turned on when the write selection signal is negated and turned off when asserted.
The input gate circuit has a control terminal connected to the write word line, and is turned on when the write selection signal is asserted and turned off when negated. 1. The semiconductor memory device according to 1. The three-state buffer is
A high impedance input circuit receiving the output voltage of the D latch circuit input from the input terminal with high impedance;
Connected between the output terminal of the high-impedance input circuit and the bit line, and disconnected so as to be conductive when the read selection signal input from the control terminal is asserted and non-conductive when negated. The semiconductor memory device according to claim 1, further comprising: an output gate circuit that performs the operation.   4. The semiconductor memory device according to claim 3, wherein the high impedance input circuit is a CMIS inverter or a single-channel MISFET whose source is grounded. A plurality of the word line pairs and a plurality of the bit lines are arranged in a lattice shape, and the memory cells are provided corresponding to the intersections of the two,
An external data output terminal for outputting the logic level voltage of the read data to the outside;
An external data input terminal for inputting the logic level voltage of the write data from the outside;
A column address input terminal for externally inputting a column address signal for selecting a column of the bit line connected to a memory cell for writing or reading data;
A latch terminal for inputting a latch control signal from the outside;
The external data input terminal is connected to each bit line, the external data output terminal, the external data input terminal, the column address input terminal, and the latch terminal, and according to the column address signal input to the column address input terminal. And a column selection circuit for connecting the external data output terminal to any one of the bit lines,
The column selection circuit includes an output selector, a plurality of data hold circuits and a plurality of write selectors provided for each of the bit lines,
The output selector has a plurality of input terminals, one output terminal, and a selection control terminal, each input terminal is connected to each bit line, and the output terminal is connected to the external data output terminal, A multiplexer that connects the selection control terminal to the column address input terminal and connects any one of the bit lines to the external data output terminal in accordance with the column address signal input from the column address input terminal And
Each data hold circuit has a D terminal, a clock terminal, and a Q terminal, the D terminal is connected to the corresponding bit line, the clock terminal is connected to the latch terminal, A D latch circuit that latches a logic level voltage of the corresponding bit line in accordance with the input latch control signal and outputs the latched voltage to the Q terminal;
Each of the write selectors has two input terminals, one output terminal, and a selection control terminal, and each of the input terminals is connected to the external data input terminal and the corresponding Q terminal of the data hold circuit. When the output terminal is connected to the corresponding bit line, the selection control terminal is connected to the column address input terminal, and the corresponding bit line is selected by the column address signal, 5. The multiplexer according to claim 1, wherein the multiplexer is connected to the external data input terminal, and is connected to the Q terminal of the data hold circuit corresponding to the bit line in the other cases. Semiconductor memory device.

Images