JP5617679B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device used for an SRAM, and more particularly to a semiconductor memory device that can be easily designed for margin or can be margin-free designed even in a low power / ultrafine process.

  Conventionally, a 6-transistor SRAM memory cell (hereinafter referred to as “6T-SRAM”) has been widely used as a semiconductor memory device used in an SRAM (Static Random Access Memory). FIG. 14 is a diagram showing a basic circuit configuration of 6T-SRAM. For each 6T-SRAM, six MISFETs (Metal-Insulator-Semiconductor Field-Effect Transistors) M1 to M6, two bit lines BL, BLB, and one word line WL are used. The MISFETs M1 and M2 and the MISFETs M3 and M4 constitute CMIS (Complementary Metal-Insulator-Semiconductor) inverters INV1 and INV2, respectively. The MISFETs M5 and M6 have transmission gates cut off by the word line WL. Configure. The CMIS inverters INV1 and INV2 are cross-coupled with each other to form an inverter / latch circuit (flip-flop). The inputs of both CMIS inverters INV1 and INV2 are connected to bit lines BL and BLB via transmission gates M5 and M6, respectively.

  During the read operation, the word line WL is set to the H level and the transmission gates M5 and M6 are turned on, so that the state value latched by the inverter / latch circuit is output to both bit lines BL and BLB. On the other hand, during the write operation, according to the write value, one of the bit lines BL and BLB is set at the H level and the other is set at the L level. In this state, the word line WL is set at the H level and the transmission gate M5 is set. M6 is turned on. As a result, a write value is set in the inverter / latch circuit.

  However, in recent years, with the miniaturization of integrated circuits and the reduction in voltage, problems of manufacturing variations of transistors M1 to M6 used for CMIS inverters and transmission gates have become apparent. FIG. 15 is a diagram showing the transition of variations in power supply voltage and gate length with the progress of miniaturization of CMOS elements. As shown in FIG. 15, the lowering of the voltage of the CMOS element has progressed year by year, and the variation has increased accordingly. In 2010, the gate length variation reached about 50% at 3σ / meanm (a ratio of the standard deviation (σ) to the mean (three times)), and it can be easily estimated that the variation will increase further in the future. . As the variation increases, the operation margin of the SRAM decreases.

FIG. 16 shows (a) the relationship of the terminal voltage (CH, CL) of the inverter / latch circuit of FIG. 14 to the gate width of the transistors (M5, M6) of the transmission gate, and (b) at the time of reading the 6T-SRAM. It is a figure showing the noise margin. In FIG. 16A, the horizontal axis represents the gate width W _TN of the transmission gate transistors (M5, M6), and the vertical axis represents the terminal voltage CH of the inverter latch circuit (INV1, INV2) at the time of reading / writing. , CL (see FIG. 14). A dotted line (RD) is a terminal voltage at the time of reading, and a solid line (WT) is a terminal voltage at the time of writing. At the time of reading, sufficient reading is possible even when the gate width _WTN is small (the transmission gate resistance is large). However, as the gate width _WTN increases, the resistance of the transmission gate decreases, Since current leaks from each terminal of the latch circuit to the bit line BL, the terminal voltage decreases. When the gate width W _TN exceeds a certain threshold value W _TNR , the data held in the inverter / latch circuit is destroyed at the moment of reading, so that the memory cell cannot be established. On the other hand, at the time of writing, if the gate width _WTN is too small, writing becomes impossible because the resistance of the transmission gate is large. Therefore, if the gate width W _TN is smaller than a certain threshold value W _TNW , writing cannot be performed and the memory cell cannot be established. Therefore, the allowable range of the gate width W _TN of the transmission gate transistors (M5, M6) is W _TNW <W _TN <W _TNR .

  FIG. 16B is a diagram showing a static noise margin (SNM) used as an index of the operation margin of the SRAM, and is a characteristic diagram generally called a butterfly curve (glasses characteristic). The horizontal and vertical axes in FIG. 16B represent the terminal voltages CL and CH of the inverter / latch circuit, respectively. Vs is the threshold voltage of the CMIS inverters INV1 and INV2. Also, the two curves shown in FIG. 16B represent voltage transfer curves (VTC) when the CMIS inverters INV1 and INV2 are read. The SNM at the time of reading is represented by the length of the diagonal line of the square shown in FIG.

As described above, in the actual LSI manufacturing process, the performance variation of each transistor constituting the memory cell is large due to variations in gate length, fluctuations in impurities, and the like. Therefore, in designing the transistors (M5 and M6) described above. Therefore, it is necessary to design a margin in consideration of variations with respect to the optimum value of the gate width _WTN . At present, in this margin design, in many cases, the design is performed with the variation width of each transistor being about 20 to 50%. However, since there are millions of such memory cells mounted in the entire SRAM, a margin of variation of individual memory cells is overlapped. Therefore, in the near future, a design that expects a margin in the range of 1/10 to 10 times as a whole will be required.

  Therefore, it is clear that the current margin design will fail if the memory cell is further miniaturized and the voltage is lowered and the variation in transistor performance further increases. Therefore, there is a need for an SRAM memory cell (semiconductor memory device) capable of a margin-free design that is not affected by variations in transistor performance.

  As the semiconductor memory device, those described in Patent Documents 1 and 2 are known. FIG. 17 is a circuit diagram of the SRAM memory cell described in Patent Document 1. In FIG. In this memory cell, write-only bit lines WBL, WBLB and read-only bit lines RBL, RBLB are provided as bit lines, and transmissions for the write-only bit lines WBL, WBLB are provided to the CMIS inverters INV1, INV2. The gates WT1 and WT2 and transmission gates RT1 and RT2 for the read-only bit lines RBL and RBLB are provided. In FIG. 17, a column selection line CSL is a line for selecting a column of a cell to which data is written. The column selection transistors CT1 and CT2 are column selection transmission gates that are disconnected by the voltage value of the column selection line CSL.

Thus, by providing the read-only transmission gates RT1 and RT2 and the write-only transmission gates WT1 and WT2 independently, the gate width of the transmission gate at the time of writing and the transmission gate at the time of reading are set. The gate width can be designed independently. Accordingly, since 16, as long gate width of each of the write transmission gate WT1, WT2 is _{W TNW} long or more, the gate width of the readout transmission gates RT1, RT2 is _{W TNR} less, allowed gate If the gate width is designed to have a sufficient margin with respect to the permissible thresholds W _TNW and W _TNR , the design margin for the performance variation of each transmission gate can be increased.

  In FIG. 17, the column of memory cells to be written is selected by the column selection transistors CT1 and CT2. This is because the memory cells in columns other than the column to which writing is performed are written. This is to prevent rewriting.

  FIG. 18 is a circuit diagram of the SRAM memory cell described in Patent Document 2. In the circuit of FIG. 18 as well, write-only bit lines BLW and BLWB and read-only bit lines BLR are provided, and transmission gates WT 1 and WT 1 for write-only bit lines BLW and BLWB are provided to CMIS inverters INV 1 and INV 2. The WT2, the transmission gate RT1 for the read-only bit line BLR, and the read transistor RT2 are provided. In this circuit, the write side is the same as the circuit of FIG. 17, but the read side does not directly connect the output of the inverter / latch circuit to the read-only bit line BLR, but the gate of the high impedance read transistor RT2. And then connected to the read-only bit line BLR via the transmission gate RT1. Thus, like the circuit of FIG. 17, the gate width of the transmission gate at the time of writing is provided by providing the read-only transmission gate RT1 and read transistor RT2 and the write-only transmission gates WT1 and WT2 independently. Thus, the gate width of the transmission gate at the time of reading can be designed independently. Further, since the latched value is output through the gate of the high impedance read transistor RT2 at the time of reading, there is no possibility that the state value held by the inverter / latch circuit at the time of reading is destroyed.

JP 2010-277634 A WO2008 / 32549

Yoshiyuki Takeishi, supervised by Hiroshi Hara, “Introduction to VLSI Series 5 Basics of MOS Integrated Circuits”, First Edition, Modern Science, May 1992, p. 65.

  However, in the conventional semiconductor memory device described above, the memory cell is used in both cases or one of the cases of inverting the data in the memory holding unit constituted by the latch / inverter and reading the data held in the latch / inverter. In all the transistors to be configured, or a part of the transistors, design restrictions, so-called ratio design, are necessary in the selection range of the gate size (gate width / gate length), and the performance variation of each transistor is considered. On the other hand, in order to operate stably, it is necessary to secure a design margin, and there has been a problem that there is a risk of failure in the future in the increase in performance variation of transistors.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device capable of stable operation regardless of the design size (gate width / gate length) of each transistor constituting a circuit and without performing margin design. is there.

A first configuration of a semiconductor memory device according to the present invention includes a read word line to which a read selection signal is input;
A write word line to which a write selection signal is input;
A write data line to which a write data signal is input;
A read data line from which a read data signal is output;
A data input terminal connected to the write data line, a write enable input terminal connected to the write word line, and a data output terminal, and the write selection signal input to the write enable input terminal is asserted The logic level voltage of the write data signal input to the data input terminal is passed, and when the write selection signal is negated, the logic level voltage of the write data signal input to the data input terminal is held, A D latch circuit for outputting a through- or held logic level voltage or its inverted value from the data output terminal;
The D latch circuit is connected between the data output terminal and the read data line, and when the read selection signal is asserted, the logic level voltage of the data output terminal or its inverted value is output to the read data line. And a memory cell having a tristate buffer whose output is in a high impedance state when the read selection signal is negated.

  According to this configuration, each memory cell that holds data is configured by using a D latch circuit and a tristate buffer, so that in both cases of data writing to the memory cell and data reading from the memory cell, the memory cell These operations are all digital operations, and basically, whether or not the operations are possible does not depend on the design value (gate width / gate length) of each transistor that constitutes.

A second configuration of the semiconductor memory device according to the present invention is the first configuration, wherein the D latch circuit is
A first CMIS inverter;
A second CMIS inverter having an input terminal connected to the output terminal of the first CMIS inverter;
Which is connected between the output terminal of the second CMIS inverter and the input terminal of said first CMIS inverter, connected to both terminals when the write selection signal inputted from the write enable input terminal is negated A loop gate circuit that disconnects both terminals when asserted, and
Connected between the data input terminal and the input terminal of the first CMIS inverter. When a write selection signal input from the write enable input terminal is asserted, both terminals are connected and negated. And an input gate circuit for cutting both terminals.

  According to this configuration, the D latch circuit portion constituting the memory cell can be configured only by a simple CMIS inverter and a transfer gate circuit, and the size and voltage can be reduced.

According to a third configuration of the semiconductor memory device of the present invention, in the second configuration, the tristate buffer is connected to a CMIS inverter and an output terminal of the CMIS inverter, and the read selection signal is asserted. And an output gate circuit for connecting both terminals to each other and disconnecting both terminals when negated.

  According to this configuration, the tristate buffer configuring the memory cell can be configured with only a simple CMIS inverter and a transfer gate circuit, and the size and voltage can be reduced.

According to a fourth configuration of the semiconductor memory device of the present invention, in the third configuration, a word line pair that is a pair of the read word line and the write word line, and a pair of the write data line and the read data line. A plurality of data line pairs are arranged in a grid pattern with each word line pair as a row and each data line pair as a column, and at each intersection of each word line pair and each data line pair, Memory cells are arranged,
A data input terminal to which the logic level voltage of the write data is input;
A column address input terminal to which a column address signal for selecting a column of the data line pair connected to a memory cell to which data is written is input;
A write selector for selectively connecting the write data line of the data line pair to either the read data line or the data input terminal of the data line pair for each of the data line pairs; With
Each of the write selectors connects the write data line to the data input terminal when the column of the write selector is a column selected by the column address signal; otherwise, the write data line Is connected to the read data line.

  According to this configuration, when the memory cell array is configured with the memory cell of the present invention, in the memory cell of the present invention that is selected by the row address signal but not specified by the column address signal during the write operation, The held data is looped back via the read data line and the write data line, so that the data in the memory cell can be held correctly without being lost.

A fifth configuration of the semiconductor memory device according to the present invention is characterized in that, in the third configuration, the input gate circuit and the output gate circuit are each composed of a single-channel MISFET having a reverse polarity.

  According to this configuration, the number of transistors constituting the memory cell can be reduced while maintaining the retention characteristics of the information storage unit, and the number of NMISFETs and PMISFETs is the same, facilitating layout and miniaturization.

  A fifth configuration of the semiconductor memory device according to the present invention is characterized in that, in the fifth configuration, the input gate circuit is configured by PMISFET and the output gate circuit is configured by NMISFET.

  According to this configuration, the retention characteristic of the information storage unit can be maintained while maintaining the high-speed reading speed which is the greatest feature of the SRAM, the number of transistors constituting the memory cell can be reduced, and the number of NMISFETs and PMISFETs As a result, the layout can be simplified and miniaturized.

According to a seventh configuration of the semiconductor memory device of the present invention, in the third configuration, at least one of the input gate circuit, the loop gate circuit, and the output gate circuit is configured by a single channel MISFET. It is characterized by that.

  According to this configuration, the number of transistors constituting the memory cell can be reduced, the layout becomes easy, and the size can be reduced.

  According to an eighth configuration of the semiconductor memory device of the present invention, in the seventh configuration, in the adjacent memory cell, the input gate circuit, the loop gate circuit, a part of the single channel MISFET configuring the output gate, Or, in all, the polarity is reversed.

  According to this configuration, the number of NMISFETs and PMISFETs that constitute a plurality of adjacent memory cells is the same, which facilitates the layout and reduces the size.

  As described above, according to the present invention, each memory cell that holds data is configured using the D latch circuit and the tristate buffer, so that the design value (gate width / gate length) of each transistor that configures the circuit. Therefore, it is possible to provide a semiconductor memory device capable of performing a margin-free design.

1 is a circuit block diagram illustrating a configuration of a memory cell of a semiconductor memory device according to Example 1 of the invention. FIG. 2 is a circuit diagram illustrating an internal configuration of a D latch circuit in FIG. 1. FIG. 2 is a circuit diagram illustrating an internal configuration of a tristate buffer circuit (inverted output type) in FIG. 1. 1 is a circuit block diagram illustrating an overall configuration of a semiconductor memory device according to Example 1 of the invention. 6 is a time chart of each signal during a read operation of the circuit of FIG. 5 is a time chart of each signal of a selected memory cell during a write operation of the circuit of FIG. 6 is a time chart of each signal of a non-selected memory cell 1 during a write operation of the circuit of FIG. FIG. 6 is a circuit diagram illustrating a configuration of a memory cell 1 of a semiconductor memory device according to Example 2 of the invention. FIG. 6 is a circuit diagram illustrating a configuration of a memory cell 1 of a semiconductor memory device according to Example 3 of the invention. FIG. 6 is a circuit diagram illustrating a configuration of a memory cell 1 of a semiconductor memory device according to Example 4 of the invention. FIG. 9 is a circuit diagram illustrating a configuration of a memory cell 1 of a semiconductor memory device according to Example 5 of the invention. FIG. 10 is a circuit diagram illustrating a configuration of a memory cell 1 of a semiconductor memory device according to Example 6 of the invention. FIG. 10 is a circuit diagram illustrating a configuration of a plurality of memory cells 1 of a semiconductor memory device according to Example 7 of the invention. It is a figure showing the basic circuit structure of the conventional 6T-SRAM. It is a figure showing the transition of the dispersion | variation in the power supply voltage and gate length accompanying progress of miniaturization of a CMOS element. (A) The relationship of the terminal voltage (CH, CL) of the inverter / latch circuit of FIG. 14 to the gate width of the transfer gate transistors (M5, M6), and (b) the noise margin at the time of 6T-SRAM read. FIG. 2 is a circuit diagram of an SRAM memory cell described in Patent Document 1. FIG. 6 is a circuit diagram of an SRAM memory cell described in Patent Document 2. FIG.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

  FIG. 1 is a circuit block diagram showing a configuration of a memory cell of a semiconductor memory device according to Embodiment 1 of the present invention.

  In FIG. 1, in the semiconductor memory device, a word line pair that is a pair of a read word line RW and a write word line WW and a data line pair that is a pair of a write data line WD and a read data line RD are arranged in a lattice pattern. (See FIG. 4), the memory cells 1 are arranged at the intersections of the word line pairs and the data line pairs. A read selection signal is input to the read word line RW. A write selection signal is input to the write word line WW. A write data signal is input to the write data line WD. A read data signal is output to the read data line RD.

  The memory cell 1 includes a D latch circuit 2 and a tristate buffer 3.

D latch circuit 2, write data line WD connected to a data input terminal D, a write word line WW connected to the write enable input terminal phi, and a data output terminal Q _- and a. When the write selection signal input to the write permission input terminal φ is asserted, the D latch circuit 2 passes through the logic level voltage of the write data signal input to the data input terminal D, and the write selection signal is negated. And hold the logic level voltage of the write data signal. Further, D latch circuit 2, the latched logic level voltage data output terminal Q _- output from. In the present embodiment, the data output terminal Q _- from is inverted value of the latched logic level voltage is configured to be output, in the present invention configured as non-inverting value is output May be.

Tri-state buffer 3, an input terminal the D data output terminal of the latch circuit 2 Q _- is connected to the output terminal is connected between the read data line RD, the inverted output control terminal connected to the read word line RW Tri-state buffer. The tristate buffer 3 outputs the inverted value of the logic level voltage of the data output terminal to the read data line when the read selection signal is asserted, and the output is in a high impedance state when the read selection signal is negated. The data output terminal Q _- in the case of the structure which outputs a non-inverted value of the logical level voltage latched from, the tri-state buffer 3 may be used a non-inverting output tri-state buffer.

  FIG. 2 is a circuit diagram showing the internal configuration of the D latch circuit 2 of FIG. The D latch circuit 2 includes CMIS inverters 4 and 5, a loop gate circuit 6, an input gate circuit 7, and an inverter 8.

  The output terminal of the CMIS inverter 4 is connected to the input terminal of the CMIS inverter 5. The loop gate circuit 6 is a transmission gate in which the channels of the nMISFET M1 and the pMISFET M2 are connected in parallel, and both channel terminals are connected between the output terminal of the CMIS inverter 5 and the input terminal of the CMIS inverter 4. Yes. The gate of the pMISFET M2 of the loop gate circuit 6 is connected to the write enable input terminal φ, and the gate of the nMISFET M1 of the loop gate circuit 6 is connected to the write enable input terminal φ via the inverter 8. As a result, the loop gate circuit 6 connects both terminals when the write selection signal input from the write enable input terminal φ is negated (at the L level) and asserts (when at the H level). Disconnect both terminals. The CMIS inverters 4 and 5 constitute a flip-flop by interpolating the loop gate circuit 6 and the output and the input being cross-coupled with each other.

The output terminal of the CMIS inverter 4, the data output terminal Q _- is connected to. Therefore, the data output terminal Q _- from the inverted value of the logical level voltage latched by flip-flop consisting of CMIS inverters 4, 5 are output.

  The input gate circuit 7 is a transmission gate in which the channels of the nMISFET M3 and the pMISFET M4 are connected in parallel, and both channel terminals are connected between the data input terminal D and the input terminal of the CMIS inverter 4. The gate of the nMISFET M3 of the input gate circuit 7 is connected to the write enable input terminal φ, and the gate of the pMISFET M4 of the input gate circuit 7 is connected to the write enable input terminal φ via the inverter 8. As a result, the input gate circuit 7 disconnects both terminals when the write selection signal input from the write enable input terminal φ is negated (at the L level) and asserts (when at the H level). Connect both terminals to.

  FIG. 3 is a circuit diagram showing the internal configuration of the tri-state buffer 3 of FIG. The tristate buffer 3 includes an output gate circuit 9 and inverters 10 and 11. The output gate circuit 9 is a transmission gate configured by connecting the channels of the nMISFET M5 and the pMISFET M6 in parallel. The gate of the nMISFET M5 is connected to the control terminal ENB, and the gate of the pMISFET M6 is connected via the inverter 10. It is connected to the control terminal ENB. The control terminal ENB is connected to the read word line RW.

The input terminal of the output gate circuit 9 is connected to the input terminal in of the tristate buffer 3 via the inverter 11, and the output terminal of the output gate circuit 9 is connected to the output terminal out of the tristate buffer 3. . The input terminals in the tri-state buffer 3, D data output terminal of the latch circuit 2 Q _- is connected to the output terminal out of the tri-state buffer 3 is connected to the read data line RD.

  FIG. 4 is a circuit block diagram showing the overall configuration of the semiconductor memory device according to the first embodiment of the invention. 4, the semiconductor memory device according to the first embodiment includes a word line pair Wn that is a pair of a read word line RWn (n = 1, 2,...) And a write word line WWn, and a write data line WDm (m = 1, 2,...) And a data line pair Dm, which is a pair of read data lines RDm, are arranged in a grid pattern with each word line pair Wn as a row and each data line pair Dm as a column. A memory cell 1 shown in FIG. 1 is disposed at each intersection of each word line pair Wn and each data line pair Dm. A column selection circuit 12 is connected to one end of each write data line WDm and read data line RDm.

  The column selection circuit 12 includes a data input terminal Din, a data output terminal Dout, and a column address input terminal Y0. From the data input terminal Din, a logic level voltage of data to be written in any one of the memory cells 1 is input. From the data output terminal Dout, the logic level voltage of the data read from any one of the memory cells 1 is output. A column address signal for selecting a data line pair Dm (m = 1, 2,...) Connected to a memory cell to which data is written is input to the column address input terminal Y0.

  The column selection circuit 12 includes write selectors 13-1, 13-2,... For each data line pair D1, D2,. These write selectors 13-m (m = 1, 2,...) Are connected to one end of the write data line WDm and the read data line RDm of the corresponding data line pair Dm and the data input terminal Din. . Each of the write selectors 13-m (m = 1, 2,...) Is a selector that selectively connects the connected write data line WDm to either the read data line RDm or the data input terminal Din. Each write selector 13-m (m = 1, 2,...) Connects the write data line WDm to the data input terminal Din when the column m of the data line pair Dm to be connected is the column selected by the column address signal. Otherwise, the write data line WDm is connected to the read data line WDm. Thereby, the column selection circuit 12 connects the write data line WDi of the selected data line pair Di to the data input terminal Din according to the column address signal, and the write data of the other data line pair Dj (j ≠ i). It operates to connect the line WDj and the read data line WDj.

  The column selection circuit 12 includes an output selector 14 that selectively connects the read data line RDi selected by the column address signal to the data output terminal Dout.

  The operation of the semiconductor memory device according to this embodiment configured as described above will be described below.

(1) Read Operation FIG. 5 is a time chart of each signal during the read operation of the circuit of FIG. FIG. 5 shows, as an example, a case where data is read from the memory cell 1 in the first row and the second column (the memory cell labeled B in FIG. 4).

  When reading data, first, a column address signal for selecting a column of cells to be read is input to the column address input terminal Y0. As a result, the read data line RD2 of the selected column is connected to the data output terminal Dout.

Next, the read selection signal of the read word line RW1 of the row of the cell to be read is asserted (set to H level). As a result, the tristate buffers 3 of all the memory cells 1 connected to the read word line RW1 are connected, and each memory cell in the first row is connected to each read data line RDm (m = 1, 2,...). The logic level voltages D _old11 , D _old12 ,... _Latched at 1 are output. At this time, since only the selected read data line RD2 is connected to the data output terminal Dout, the logic level voltage _Dold12 latched in the memory cell 1 in the first row and the second column is connected to the data output terminal Dout. Is output.

  Through the operation as described above, the data latched in the selected memory cell 1 is read.

(2) Write Operation FIG. 6 is a time chart of each signal of the selected memory cell during the write operation of the circuit of FIG. 4, and FIG. 7 is a diagram of each of the non-selected memory cells during the write operation of the circuit of FIG. It is a time chart of a signal. 6 and 7 show an example in which data is written to the memory cell 1 in the first row and the second column (the memory cell denoted by reference character B in FIG. 4).

When writing data, first, the read selection signal of the read word line RW1 of the row of the cell to be written is asserted (set to H level) (time t1). As a result, the logical data voltages D _old11 , D _old12 ,... _Latched in the memory cells 1 of each column connected to the selected read word line RW1 are output to the read data lines RD1, RD2 _,. (Time t ₂ ).

At this time, since the column address signal has not yet been input, the write selectors 13-2 of all the columns are in a connected state. Therefore, the logic level voltage _Dold1m output to the read data line RDm (m = 1, 2,...) Of each column is transmitted to the paired write data line WDm, and the voltage of the write data line WDm is the logic level voltage. D _old1m (time t3).

Then, enter the logic level voltage _{D new new} write data for writing to the data input terminal Din (time t4).

Next, a column address signal for selecting a column of cells to be written is input to the column address input terminal Y0. As a result, the write selector 13-2 of the selected column connects the write data line WD2 to the data input terminal Din. In the other write selector 13-j (j ≠ 2), the write data line WDj remains connected to the read data line RDj (t5). Thereby, the write data lines WD2 of the selected column, the logic level voltage D _{new new} write data. On the other hand, since the write data line WDj (j ≠ 2) in the unselected column remains connected to the read data line RDj, the memory cell 1 in the j-th column of the selected row is stored in the tristate buffer 3. The output terminal and the data input terminal D of the D latch circuit 2 are short-circuited.

Next, the write selection signal of the write word line WW1 of the row to be written is asserted (set to H level) (time t6). As a result, the write data line WDm of the column m (m = 1, 2,...) To which the memory cell 1 belongs is set in the D latch circuits 2 of all the memory cells 1 in the selected row (first row). Set voltage. At this time, the write data line WD2 of the selected column, since the logic level voltage D _{new new} write data has been set, first row second column of logic level voltage in the D latch circuit 2 of the memory cell 1 D _new is set (time t7), and accordingly, the voltage of the read data line RD2 in the second column also becomes the logic level voltage D _new (time t8). On the other hand, since the logic level voltage _Dold1j latched in the memory cell 1 of the selected row (first row) is set to the write data line WDj (j ≠ 2) in the unselected column, one row The set voltage of the D latch circuit 2 of the memory cell 1 in the first column is maintained as it is.

  Next, the write selection signal of the write word line WW1 is negated (set to L level). As a result, the D latch circuit 2 of each memory cell 1 in the first row latches the voltage of the data input terminal D at that time (time t9).

  Finally, the input of the column address signal is stopped and the read selection signal of the read word line RW1 in the write row is negated (set to L level) (time t10). As a result, the output of data from the D latch circuit 2 of the memory cell 1 in each column of the first row to the read data lines RD1, RD2,... Is stopped (time t11, t12).

  Through the above operation, new data is written in the memory cell 1 in the first row and the second column, and the memory cell 1 in the first row and the first column holds the previous data.

  As described above, in the semiconductor memory device of this embodiment, the D latch circuit 2 and the tristate buffer 3 are used for each memory cell 1, and the output of the D latch circuit 2 is received by the tristate buffer 3 with high impedance. By separating from the data line RD, the design values (gate width / gate length) of the transistors M3 and M4 used for the input gate circuit 7 of the D latch circuit 2 and the transistors M5 and M6 used for the output gate circuit 9 are determined. Design values (gate width / gate length) can be determined completely independently. Therefore, the design can be performed without being limited by the design value (gate width / gate length) of each of the transistors M3, M4, M5, and M6. In addition, the transistors M3, M4, M5, and M6 can be designed regardless of the design value (gate width / gate length), so that the transistors M3, M4, M5, and M6 and the transistors constituting each inverter circuit are provided. It is also possible to design as the minimum level size of the process. Therefore, the circuit can be reduced in size as a whole.

  FIG. 8 is a circuit diagram showing a configuration of a memory cell of the semiconductor memory device according to the second embodiment of the present invention. In FIG. 8, read word line RW, write word line WW, write data line WD, read data line RD, memory cell 1, D latch circuit 2, tristate buffer 3, CMIS inverters 4 and 5, loop gate circuit 6, input The gate circuit 7, the output gate circuit 9, and the inverter 11 are the same as those having the same reference numerals in FIGS. Further, the transistors M1 to M6 in FIG. 8 correspond to the same reference numerals in FIGS.

In the semiconductor memory device of this embodiment, the inverter 8 of the D latch circuit 2 of FIG. 2 and the inverter 10 of the tristate buffer 3 of FIG. 3 are omitted, and the logically inverted value of the read word line RW is input instead. read word line RW which is _- a write word line WW that logically inverted value of the write word line WW is input _- and a. The write word line WW ₋ is connected to the gates of the transistors M1 and M4, and the read word line RW ₋ is connected to the gate of the transistor M6.

Even with this configuration, the same effects as those of the first embodiment can be obtained. In the circuit configuration of this embodiment, since the inverters 8 and 10 are omitted as compared with the first embodiment, at least four transistors can be reduced per memory cell 1 compared to the first embodiment. Instead, two new wirings (read word line RW ₋ , write word line WW ₋ ) are required per row.

FIG. 9 is a circuit diagram showing a configuration of a memory cell of a semiconductor memory device according to Embodiment 3 of the present invention. In FIG. 9, read word line RW, write word line WW, write data line WD, read data line RD, memory cell 1, D latch circuit 2, tristate buffer 3, CMIS inverters 4 and 5, loop gate circuit 6, input The gate circuit 7, the output gate circuit 9, the inverter 11, and the transistors M2, M3, and M5 correspond to the same reference numerals in FIG. Compared to FIG. 8, in the memory cell 1 of this embodiment, the loop gate circuit 6, the input gate circuit 7, and the output gate circuit 9 are replaced by a single-channel transfer gate instead of the two-channel transmission gate. The difference is in the configuration. Thus, the read word line RW 8 _- and the write word line WW _- is not required.

  When a single-channel transfer gate is used, for example, the pMISFET alone has a weak point that a low-side signal cannot be accurately transmitted. Even in such a configuration, the semiconductor memory device of the present invention can be configured.

  In this embodiment, each memory cell 1 in FIG. 4 has the same configuration as that shown in FIG. 9, but as another example, in the adjacent memory cell 1 in FIG. A part or all of the one-channel MISFETs M3, M2, and M5 constituting the loop gate circuit 6 and the output gate circuit 9 can be configured to have opposite polarities (see the seventh embodiment). Thereby, the layout area of the whole chip can be reduced.

  FIG. 10 is a circuit diagram showing a configuration of the memory cell 1 of the semiconductor memory device according to Embodiment 4 of the present invention. In FIG. 10, read word line RW, write word line WW, write data line WD, read data line RD, memory cell 1, D latch circuit 2, tristate buffer 3, CMIS inverters 4 and 5, loop gate circuit 6, input The gate circuit 7, the output gate circuit 9, the inverter 11, and the transistors M1, M2, M3, and M5 correspond to the same reference numerals in FIG. The memory cell 1 of FIG. 10 is an improvement of the memory cell 1 of FIG. Compared with FIG. 9, the only difference is that the transmission gates of both channels similar to the first embodiment are used for the loop gate circuit 6.

  The reason why only the loop gate circuit 6 interpolated in the flip-flop composed of the CMIS inverters 4 and 5 is the transmission gate of both channels is that if the loop gate circuit 6 is a single channel as shown in FIG. This is because the characteristic on the level side does not appear cleanly, the leakage current increases, and it is necessary to design the loop gate circuit 6 with a strict margin in order to compensate for the state retention in the flip-flop. If both channel transmission gates are used as shown in FIG. 10, such a problem is solved.

  In this embodiment, each memory cell 1 in FIG. 4 has the same configuration as that shown in FIG. 10, but as another example, in the adjacent memory cells 1 and 1 in FIG. 7 and part or all of the one-channel MISFETs M7 and M9 constituting the output gate circuit 9 can be configured so that their polarities are reversed (see the seventh embodiment). Thereby, the layout area of the whole chip can be reduced.

  FIG. 11 is a circuit diagram showing a configuration of the memory cell 1 of the semiconductor memory device according to the fifth embodiment of the present invention. The memory cell 1 of FIG. 11 is an improvement of the memory cell 1 of FIG. Compared with FIG. 10, a loop gate / inverter circuit 15 in which the loop gate circuit 6 and the inverter 5 are integrated is used, and the output gate circuit 9 is composed of the PMISFET M6.

  It is functionally equivalent to use the inverter and the transfer gate at the output of the inverter by changing the connection to a loop gate inverter circuit such as 15, and this is done conveniently for layout and the like. Further, by configuring the output gate circuit 9 with PMISFET, the number of NMISFETs and PMISFETs constituting the memory cell in the circuit of FIG. It becomes easy.

  FIG. 12 is a circuit diagram showing a configuration of the memory cell 1 of the semiconductor memory device according to Embodiment 6 of the present invention. The memory cell 1 in FIG. 12 is a modification of the memory cell 1 in FIG. Compared with FIG. 11, in the loop gate inverter circuit 15, the connection order of the PMISFET and NMISFET connected in series is changed. In addition, since the polarity of the transistors constituting the input gate circuit 7 and the output gate circuit 9 is reversed and the NMISFET is used for the output gate circuit 9, the data reading speed, which is the most important feature of the SRAM, is affected. Never give.

  It is functionally equivalent to use the inverter of FIG. 10 and the transfer gate at the output thereof by changing the connection to the loop gate inverter circuit 15 in FIG. 11 or FIG. What is necessary is just to select for convenience, such as a layout. Further, when the input gate circuit 7 and the output gate circuit 9 are made into one channel, either PMISFET or NMISFET may be used as shown in FIG. 10, FIG. 11, and FIG. 12, in consideration of layout ease and miniaturization. To select.

  FIG. 13 is a circuit diagram showing a configuration of a plurality of memory cells 1 of a semiconductor memory device according to Embodiment 7 of the present invention. The semiconductor memory device of FIG. 13 includes the polarity of the memory cell 1 of FIG. 9 and the single channel transistors M2, M3, and M5 that constitute the loop gate circuit 6, the input gate circuit 7, and the output gate circuit 9 of the memory cell 1. The memory cell 1 'includes a loop gate circuit 6', an input gate circuit 7 ', and an output gate circuit 9' composed of transistors M1, M4, and M6.

  The circuit of FIG. 9 has nine transistors in the memory cell 1 and the smallest number of elements in the circuits of FIGS. 9 to 12. However, since the total number of elements is an odd number, the PMISFET and NMISFET The number is not the same. For example, it is difficult to reduce the size when performing layout. Therefore, as shown in FIG. 13, in the adjacent memory cells, all or some of the transfer gates constituted by one-channel MISFETs are reversed in polarity, and the same number of PMISFET and NMISFET transistors are used in a plurality of memory cells. To do. In the example of FIG. 13, the number of PMISFETs and NMISFETs is the same as nine in the upper and lower two memory cells 1 and 1 ′, respectively. In the example of FIG. 13, this effect can be obtained by setting the polarity of at least the output gate circuit 9 of two adjacent memory cells to the opposite polarity.

1, 1 'memory cell 2 D latch circuit 3 tristate buffer 4, 5 CMIS inverter 6, 6' loop gate circuit 7, 7 'input gate circuit 8 inverter 9, 9' output gate circuit 10, 11 inverter 12 column selection circuit 13-1 and 13-2, ... of write selector 14 outputs the selector 15 loop gate inverter circuit RW read word line RW _- read word line WW write word line WW _- write word line WD write data line RD read data line D data Input terminal φ Write enable input terminal Q ₋ Data output terminal Din Data input terminal Dout Data output terminal Y0 Column address input terminal

Claims (7)

A read word line to which a read selection signal is input; and
A write word line to which a write selection signal is input;
A write data line to which a write data signal is input;
A read data line from which a read data signal is output;
A data input terminal connected to the write data line, a write enable input terminal connected to the write word line, and a data output terminal, and the write selection signal input to the write enable input terminal is asserted The logic level voltage of the write data signal input to the data input terminal is passed, and when the write selection signal is negated, the logic level voltage of the write data signal input to the data input terminal is held, A D latch circuit for outputting a through- or held logic level voltage or its inverted value from the data output terminal;
The D latch circuit is connected between the data output terminal and the read data line, and when the read selection signal is asserted, the logic level voltage of the data output terminal or its inverted value is output to the read data line. And a memory cell including a tristate buffer whose output is in a high impedance state when the read selection signal is negated ,
The word line pair, which is a pair of the read word line and the write word line, and the data line pair, which is a pair of the write data line and the read data line, use the word line pair as a row, and the data line pair. Are arranged in a grid pattern, and the memory cells are arranged at the intersections of the word line pairs and the data line pairs,
A data input terminal to which the logic level voltage of the write data is input;
A column address input terminal to which a column address signal for selecting a column of the data line pair connected to a memory cell to which data is written is input;
A write selector for selectively connecting the write data line of the data line pair to either the read data line or the data input terminal of the data line pair for each of the data line pairs; With
Each of the write selectors connects the write data line to the data input terminal when the column of the write selector is a column selected by the column address signal; otherwise, the write data line Is connected to the read data line . The D latch circuit is
A first CMIS inverter;
A second CMIS inverter having an input terminal connected to the output terminal of the first CMIS inverter;
Which is connected between the output terminal of the second CMIS inverter and the input terminal of said first CMIS inverter, connected to both terminals when the write selection signal inputted from the write enable input terminal is negated A loop gate circuit that disconnects both terminals when asserted, and
Connected between the data input terminal and the input terminal of the first CMIS inverter. When a write selection signal input from the write enable input terminal is asserted, both terminals are connected and negated. 2. A semiconductor memory device according to claim 1, further comprising an input gate circuit for cutting both terminals. The tri-state buffer is
A CMIS inverter; and an output gate circuit connected to the output terminal of the CMIS inverter, connecting both terminals when the read selection signal is asserted, and disconnecting both terminals when negated. The semiconductor memory device according to claim 2 , wherein: 4. The semiconductor memory device according to claim 3 , wherein each of the input gate circuit and the output gate circuit is configured by a single-channel MISFET having a reverse polarity. 4. The semiconductor memory device according to claim 3 , wherein the input gate circuit is a PMISFET and the output gate circuit is an NMISFET. 4. The semiconductor memory device according to claim 3 , wherein at least one of the input gate circuit, the loop gate circuit, and the output gate circuit is configured by a single channel MISFET. The adjacent memory cells, the input gate circuit, said loop gate circuit, a portion of one channel MISFET constituting said output gate, or all, to claim 6, characterized in that the polarity becomes opposite The semiconductor memory device described.

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