CN117476072A - SRAM (static random Access memory) storage unit - Google Patents

Abstract

The invention discloses an SRAM (static random Access memory) storage unit, which relates to the technical field of chip design and is used for solving the problem that the conventional storage structure cannot ensure the writing capability and the stability of a half-selected unit at the same time. Comprising the following steps: a cross-coupled inverter, a read path, and an access transistor; the cross-coupled inverter comprises a first PMOS tube, a second PMOS tube, a first NMOS tube and a second NMOS tube; the access transistor comprises a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube; the third NMOS tube and the fifth NMOS tube are used for eliminating row half-select interference so that the memory array supports a bit interleaving structure; the read channel comprises a first read channel formed by a sixth NMOS tube and an eighth NMOS tube, and a second read channel formed by a fourth NMOS tube and a seventh NMOS tube; the third PMOS tube and the fourth PMOS tube are used for cutting off the feedback of the back-to-back inverter; the fifth PMOS tube is used for providing a pull-up path for the floating storage nodes of the column half-selected units; the writing capability is improved, and meanwhile, the stability of the half-selected unit is ensured.

Description

SRAM (static random Access memory) storage unit

Technical Field

The invention relates to the technical field of chip design, in particular to an SRAM (static random Access memory) storage unit.

Background

Low voltage technology is the most straightforward method to reduce SRAM power consumption, but has a negative impact on SRAM stability. As the voltage decreases, threshold value mismatch caused by process deviation has a great influence on the read-write stability of SRAM. Read stability is measured primarily by read noise margin (RSNM), which decreases the voltage of the cell RSNM, and too low RSNM causes the data to be overwritten during a read operation. Meanwhile, in the aspect of SRAM array organization, a bit interleaving structure is generally adopted to realize sharing of peripheral structures so as to optimize the area, namely a plurality of words are placed on the same row, and different bits of each word are arranged in an interleaving manner, but a bit interleaving storage unit in the prior art adopts stacked NMOS (N-channel metal oxide semiconductor) tubes for writing, so that the writing operation speed is very slow, and when a power gating writing auxiliary unit is used for writing, the problem that storage nodes in a column half-selected unit are easy to float is solved, and data stored in the column half-selected unit are turned over in error. Therefore, the existing memory structure cannot guarantee both the writing capability and the stability of the half select unit.

Accordingly, there is a need to provide a more reliable SRAM memory cell structure.

Disclosure of Invention

The invention aims to provide an SRAM memory cell which is used for solving the problem that the existing memory structure cannot simultaneously ensure the writing capability and the stability of a half-selected cell.

In order to achieve the above object, the present invention provides the following technical solutions:

in a first aspect, the present invention provides an SRAM memory cell, comprising:

a cross-coupled inverter, a read path, and an access transistor;

the cross-coupled inverter comprises a first PMOS tube, a second PMOS tube, a first NMOS tube and a second NMOS tube;

the access transistor comprises a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube; the third NMOS tube and the fifth NMOS tube are used for eliminating row half-select interference so that the memory array supports a bit interleaving structure;

the read channel comprises a first read channel formed by a sixth NMOS tube and an eighth NMOS tube, and a second read channel formed by a fourth NMOS tube and a seventh NMOS tube;

the third PMOS tube and the fourth PMOS tube are used for cutting off the feedback of the back-to-back inverter; the fifth PMOS tube is used for providing a pull-up path for the floating storage nodes of the column half-selected units.

Optionally, the SRAM memory cell is a 13-pipe memory cell; the SRAM memory cell further comprises:

a storage node, a read word line, a first write word line, a second write word line, and a bit line; the storage nodes comprise a first storage node and a second storage node;

the read word lines are row-based, the first write word lines, the second write word lines, bit lines, and bit lines are not column-based; the storage nodes are decoupled from the bit lines and bit lines by using a read buffer.

Optionally, under a hold operation, the read word line, the first write word line, and the second write word line are controlled to be low; control bit line and bit line not to be high level; the storage node is not coupled with an external signal, and the SRAM storage unit stably holds data.

Optionally, before the SRAM memory cell performs a read operation, the bit line and the bit line are not high;

when the SRAM memory cell executes a read operation, a selected read word line is enabled, the first write word line and the second write word line are disabled, and the third NMOS tube and the fifth NMOS tube remain turned off.

Optionally, when performing the read 0 operation, the first storage node stores 0, and the second storage node stores 1;

and a low-resistance passage is formed between the bit line and the ground through the fourth NMOS tube and the seventh NMOS tube, so that a read current is generated, the eighth NMOS tube is turned off, and no read current exists on the non-side of the bit line.

Optionally, during a read operation, when the first write word line and the second write word line are disabled, the third PMOS transistor and the fourth PMOS transistor are turned on, and the third PMOS transistor and the fifth PMOS transistor are turned off, so that the first storage node and the second storage node are separated from the bit line and the bit line, and the storage node is decoupled from the bit line.

Optionally, when the SRAM memory cell performs a write 0 operation, the read word line and the first write word line are activated simultaneously; the third PMOS tube and the fifth PMOS tube are in a closed state, the pull-up path of the first storage node is cut off, the first storage node is rapidly pulled down to 0 by the third NMOS tube and the fourth NMOS tube, and the second storage node is precharged to 1 by positive feedback, so that the 0 writing operation is completed.

Optionally, the second write word line is disabled, the fifth NMOS transistor is turned off, and the bit line does not affect the second storage node;

when the SRAM memory cell executes the write 1 operation, the bit line is not at a low level, the read word line and the second write word line are at a high level, the fourth PMOS tube and the fifth PMOS tube are turned off, the pull-up path of the second memory node is cut off, the second memory node is pulled down to 0 by the fifth NMOS tube and the sixth NMOS tube, and the first memory node is precharged to 1 by positive feedback, so that the write 1 operation is completed.

Optionally, for the half-select units on the same row, the third NMOS transistor and the fifth NMOS transistor are turned off by two column word lines, there is no coupling effect between the storage node and the bit line, and half-select damage is not generated;

for half-select cells on the same column, the read word line is set low.

Optionally, when performing a write 0 operation on the selected unit, the first write word line of the half selected unit is enabled, the third NMOS transistor is turned on, the third PMOS transistor is turned off, and if the first storage node is set to 1, the first storage node is kept to 1 through the fourth PMOS transistor, the fifth PMOS transistor, and the first PMOS transistor;

when the write 1 operation is executed on the selected unit, the second write word line is enabled, the fifth NMOS tube is opened, the fourth PMOS tube is turned off, and the third PMOS tube, the fifth PMOS tube and the second PMOS tube maintain the high level of the second storage node, so that the second storage node is ensured not to float; at this time, when the second storage node of the data stored in the half-selected cell is 0 or 1, none of the data stored in the cell is changed.

Compared with the prior art, the SRAM memory cell provided by the invention comprises the following components: a cross-coupled inverter, a read path, and an access transistor; the cross-coupled inverter comprises a first PMOS tube, a second PMOS tube, a first NMOS tube and a second NMOS tube; the access transistor comprises a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube; the third NMOS tube and the fifth NMOS tube are used for eliminating row half-select interference so that the memory array supports a bit interleaving structure; the read channel comprises a first read channel formed by a sixth NMOS tube and an eighth NMOS tube and a second read channel formed by a fourth NMOS tube and a seventh NMOS tube, so that the read damage problem of the unit is solved; the third PMOS tube and the fourth PMOS tube are used for cutting off the feedback of the back-to-back inverter and improving the writing capacity; the fifth PMOS tube is used for providing a pull-up path for the floating storage node of the column half-selected unit and ensuring the stability of the column half-selected unit; the memory cell structure with both writing capability and half-selected cell stability is provided, so that the read damage is eliminated, the writing capability is improved, and the stability of the half-selected cell is ensured.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and do not constitute a limitation on the invention. In the drawings:

FIG. 1 is a schematic diagram of a bit interleaving structure of an SRAM cell in the prior art;

FIG. 2 is a schematic diagram of a memory cell structure of a 13TSRAM according to the present invention;

FIG. 3 is a schematic diagram of a hold operation provided by the present invention;

FIG. 4 is a schematic diagram of a read operation provided by the present invention;

FIG. 5 is a schematic diagram of performing a write 0 operation according to the present invention;

FIG. 6 is a schematic diagram of performing a write 1 operation provided by the present invention;

FIG. 7 is a schematic diagram of a half-select cell write operation on the same row provided by the present invention;

FIG. 8 is a schematic diagram of a half-selected cell write operation on the same column provided by the present invention.

Detailed Description

In order to clearly describe the technical solution of the embodiments of the present invention, in the embodiments of the present invention, the words "first", "second", etc. are used to distinguish the same item or similar items having substantially the same function and effect. For example, the first threshold and the second threshold are merely for distinguishing between different thresholds, and are not limited in order. It will be appreciated by those of skill in the art that the words "first," "second," and the like do not limit the amount and order of execution, and that the words "first," "second," and the like do not necessarily differ.

In the present invention, the words "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.

In the present invention, "at least one" means one or more, and "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a alone, a and B together, and B alone, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b or c may represent: a, b, c, a and b, a and c, b and c, or a, b and c, wherein a, b, c can be single or multiple.

Term interpretation:

a static random access memory StaticRandomAccessMemory (SRAM).

The static noise margin ReadStaticNoiseMargin (RSNM) is read.

In the prior art, as shown in fig. 1. In the prior art bit interleaving structure, the same row shares one word line. When a write operation is performed on the selected cell, cell WL [0] is turned on. WL [1] =0 corresponding to the column half-selected cell, the data on the bit line will not affect the data of the cell storage node. But for row half-select cells, the word line is open and there is a coupling between the storage node and the bit line, i.e., equivalent to a read operation. The half select unit also faces stability problems at low voltages.

The conventional 6T-SRAM cell structure is very simple, but its operation margin is affected by read disturb, half select disturb, and read-write requirement conflicts. The read-write stability of 6T-SRAM decreases rapidly with decreasing supply voltage due to increased threshold voltage fluctuations caused by global and local process variations in advanced CMOS processes. For robust low voltage operation, the 7T-SRAM memory cell in the prior art utilizes a feedback cut-off NMOS transistor to enhance the write margin and a dynamic decoupling scheme to eliminate read interference, but the feedback cut-off NMOS transistor leads to a floating memory node and is easily affected by leakage current and coupling noise. An 8T cell with single-ended read decouples the cell storage node from the bit line during operation to eliminate read disturb and improve read noise margin (RSNM). The bit interleaved memory cells supported by 9T and 10T solve the stability problem of the row half select cell by adding access NMOS transistors controlled by the column select word line signal, but the write operation speed is very slow by using stacked NMOS transistors, so that additional write assist circuits are required to improve the write capability of the cell. The power-gated write assist unit proposed in the prior art improves the write capability of the unit by switching off the feedback path in the back-to-back inverter. However, during the write operation, the floating problem of the storage nodes in the column half-selected cells easily occurs, which results in the erroneous inversion of the data stored in the column half-selected cells.

It can be seen that the prior art SRAM memory cell, the bit-interleaved memory cell, uses stacked NMOS transistors for writing, makes the writing operation very slow. When the power gating write auxiliary unit is used for writing, the problem that the storage nodes in the column half-selected units are easy to float easily causes error overturning of data stored in the column half-selected units. Therefore, the existing memory structure cannot guarantee both the writing capability and the stability of the half select unit.

Based on the defects in the prior art, the invention provides a memory cell structure which has both writing capability and half-selected cell stability, can eliminate read damage, improve writing capability and simultaneously can ensure the stability of the half-selected cell.

Next, the scheme provided by the embodiments of the present specification will be described with reference to the accompanying drawings:

as shown in fig. 2, the SRAM memory cell may include the following structure:

a cross-coupled inverter, a read path, and an access transistor;

the cross-coupled inverter comprises a first PMOS tube MP1, a second PMOS tube MP2, a first NMOS tube MN1 and a second NMOS tube MN2;

the access transistor comprises a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5 and a sixth NMOS transistor MN6; the third NMOS transistor MN3 and the fifth NMOS transistor MN5 are configured to eliminate row half-select interference, so that the memory array supports a bit interleaving structure;

the read channel comprises a first read channel formed by a sixth NMOS tube MN6 and an eighth NMOS tube MN8, and a second read channel formed by a fourth NMOS tube MN4 and a seventh NMOS tube MN 7;

the third PMOS tube MP3 and the fourth PMOS tube MP4 are used for cutting off the feedback of the back-to-back inverter; the fifth PMOS transistor MP5 is configured to provide a pull-up path for the storage node floating in the column half-select unit.

The SRAM memory cell structure in fig. 2, MP1, MP2, MN1 and MN2 constitute cross-coupled inverters, Q and QB being storage nodes. MN3, MN4, MN5, and MN6 are access transistors, and MN3 and MN5 are used to eliminate row half select interference so that the memory array supports a bit interleaving structure. The MN6, MN8, MN4 and MN7 transistors form a read path, and are used for solving the read damage problem of the unit. MP3 and MP4 are used to cut off the feedback from the back-to-back inverters, improving the write capability. The MP5 transistor is used for providing a pull-up path for the floating storage node of the column half-selected unit and ensuring the stability of the column half-selected unit. The memory cell structure with both writing capability and half-selected cell stability is provided, so that the read damage is eliminated, the writing capability is improved, and the stability of the half-selected cell is ensured.

Based on the structure of fig. 2, some specific structures of the structure and the corresponding read-write operation process of the structure are further provided in the embodiments of the present disclosure, and are described below.

As shown in fig. 2, the SRAM memory cell is a 13-pipe memory cell; the SRAM memory cell further comprises: storage nodes (Q and QB), read Word Line (RWL), first Write Word Line (WWL), second Write Word Line (WWL), and Bit Line (BL); the storage nodes comprise a first storage node Q and a second storage node QB; the Read Word Line (RWL) is row-based, and the first Write Word Line (WWLA), the second Write Word Line (WWLB), the Bit Line (BL), and the bit line non-BLB are column-based. Since the proposed 13T bit cell uses a read buffer to decouple the storage nodes (Q and QB) from the bit lines (BL and BLB) to eliminate read disturb and enhance write capability, there is no size conflict between read and write operations, so a minimum size design is used for all cell transistors.

Table 1 lists the truth tables for the proposed 13T bit cell under different operating conditions.

As can be seen from table 1, the SRAM memory cells are under different operating states, read word line, write word line, bit line not control signal conditions.

Control signal table of table 113T unit

Next, each operation is described in conjunction with the SRAM memory cell of fig. 2 in conjunction with fig. 3-8:

1) Hold operation

The SRAM memory cell in fig. 2 is shown in fig. 3 at the time of the hold operation. The control signals RWL, WWLA, WWLB are all low in hold operation. The control signals BL and BLB are high. The cell storage node is not coupled with an external signal, and the cell can stably hold data.

2) Read operation

BL and BLB are precharged to a high level prior to a read operation. During a read operation, the selected RWL is enabled, while WWL and WWL are still disabled, so that transistors MN3 and MN5 remain off, ensuring that read corruption does not occur during the read operation. When reading 0, Q is 0, QB is 1, as shown in FIG. 4, a low-resistance path is formed between the bit line BL and the ground through MN4 and MN7, so that read current is generated, MN8 is turned off, no read current exists on the BLB side, and then the bit line voltage is amplified and output to the full swing through a sense amplifier, so that robust read operation is realized. The same applies to reading "1".

Since WWLA and WWLB are disabled during a read operation, transistors MP3 and MP4 are turned on, MN3 and MN5 are turned off, thereby separating Q and QB from BL and BLB, decoupling the storage node from the bit line, thereby eliminating read corruption, and achieving read stability.

Through the SRAM memory cell structure in FIG. 2, a read decoupling structure is adopted to isolate the memory nodes from the bit lines, thereby ensuring read stability.

3) Write operation

The 13-pipe memory cell is shown in fig. 5 at the time of the write operation. When the memory cell performs a write "0" operation, RWL and WWL are activated at the same time. MP3 and MP5 are in the off state, the pull-up path of node Q is cut off, so node Q is pulled down to "0" by MN3 and MN4 rapidly, and node QB is precharged to "1" by positive feedback, completing the write "0" operation. While WWLB is disabled, MN5 is off, BLB has no effect on QB point.

As shown in fig. 6, when writing "1", BLB is low, RWL and WWLB are high, MP4 and MP5 are turned off, and the pull-up path of the node QB is cut off, so that the node QB is rapidly pulled down to "0" by MN5 and MN6, and the node Q is precharged to "1" by positive feedback, completing the writing "1" operation. The 13T memory cell effectively improves the write margin and write speed of the memory cell by cutting off the pull-up path.

With the SRAM memory cell structure of fig. 2, the pull-up network is weakened by cutting back-to-back feedback, thereby improving the write capability.

4) Stability of half-select cell

The half select cell case for the 13-pipe cell at the time of the write operation is shown in fig. 7-8. For half-select cells on the same row, although word line RWL is on, half-select corruption does not occur because MN3 and MN5 are turned off by two columns of word lines, there is no coupling between the storage node and the bit line. For half select cells on the same column, RWL is set low. When writing "0" to the selected cell, half-select cell WWLA is enabled, MN3 is turned on, MP3 is turned off, if Q is "1", and turning off MP3 results in floating of node Q, but Q is kept "1" by MP4, MP5 and MP1 due to MP 5. When writing "1" to the selected cell, WWLB is enabled, MN5 is on, MP4 is off, MP3, MP5 and MP2 maintain QB point high level, ensuring no floating. At this time, when the data QB stored in the half-selected cell is "0" or "1", the data stored in the cell is not changed. The proposed novel 13T cell has stability of row half select cells and column half select cells.

The SRAM memory cell provided by the invention eliminates the stability problem of the column half-selected cell. Meanwhile, the read-write contradiction of the unit is eliminated by isolating the storage node from the bit line, the read stability of the unit is ensured, the write capability is enhanced by the aid of the data-dependent power gating write assistance, the floating node in the column half-selected unit is eliminated, and the stability of low-voltage operation is ensured. Specifically, the technical effects of the 13TSRAM memory unit provided by the invention include:

1) The memory nodes and the bit lines are isolated through read decoupling to eliminate read damage, so that the read stability of the cell is ensured.

2) By cutting off the back-to-back feedback, the power supply voltage of the left half cell or the right half cell is cut off depending on input data in the writing operation process, so that the pull-up network of the bit cell is weakened, the discharging of the storage node is assisted, the writing margin and the writing speed of the storage cell are effectively improved, and the writing capability is improved without using an additional peripheral writing auxiliary circuit and a related time sequence control circuit.

3) Meanwhile, write half-select interference is eliminated by adopting a write word line based on a column, and the problem that a floating node appears at a storage node in a column half-select unit is solved by adding a balance PMOS transistor, so that the stability of low-voltage operation is ensured.

4) The 13TSRAM memory cell structure provided by the invention greatly improves the read stability, effectively improves the write noise margin and the write speed, and further ensures the stability of the half-selected cell.

Although the invention is described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Although the invention has been described in connection with specific features and embodiments thereof, it will be apparent that various modifications and combinations can be made without departing from the spirit and scope of the invention. Accordingly, the specification and drawings are merely exemplary illustrations of the present invention as defined in the appended claims and are considered to cover any and all modifications, variations, combinations, or equivalents that fall within the scope of the invention. It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims (10)

1. An SRAM memory cell, comprising:

a cross-coupled inverter, a read path, and an access transistor;

the cross-coupled inverter comprises a first PMOS tube, a second PMOS tube, a first NMOS tube and a second NMOS tube;

the access transistor comprises a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube; the third NMOS tube and the fifth NMOS tube are used for eliminating row half-select interference so that the memory array supports a bit interleaving structure;

the read channel comprises a first read channel formed by a sixth NMOS tube and an eighth NMOS tube, and a second read channel formed by a fourth NMOS tube and a seventh NMOS tube;

the third PMOS tube and the fourth PMOS tube are used for cutting off the feedback of the back-to-back inverter; the fifth PMOS tube is used for providing a pull-up path for the floating storage nodes of the column half-selected units.

2. The SRAM memory cell of claim 1, wherein said SRAM memory cell is a 13-pipe memory cell; the SRAM memory cell further comprises:

a storage node, a read word line, a first write word line, a second write word line, and a bit line; the storage nodes comprise a first storage node and a second storage node;

the read word lines are row-based; the first write word line, the second write word line, bit line, and bit line are not column-based; the storage nodes are decoupled from the bit lines and bit lines by using a read buffer.

3. The SRAM memory cell of claim 2, wherein said read word line, said first write word line, and said second write word line are controlled to be low under a hold operation; control bit line and bit line not to be high level; the storage node is not coupled with an external signal, and the SRAM storage unit stably holds data.

4. The SRAM memory cell of claim 3, wherein bit lines and bit lines are not high before said SRAM memory cell performs a read operation;

when the SRAM memory cell executes a read operation, a selected read word line is enabled, the first write word line and the second write word line are disabled, and the third NMOS tube and the fifth NMOS tube remain turned off.

5. The SRAM memory cell of claim 4, wherein said first storage node stores 0 and said second storage node stores 1 when performing a read 0 operation;

and a low-resistance passage is formed between the bit line and the ground through the fourth NMOS tube and the seventh NMOS tube, so that a read current is generated, the eighth NMOS tube is turned off, and no read current exists on the non-side of the bit line.

6. The SRAM memory cell of claim 5, wherein during a read operation, when the first write word line and the second write word line are disabled, the third PMOS transistor and the fourth PMOS transistor are turned on, the third PMOS transistor and the fifth PMOS transistor are turned off, separating the first storage node and the second storage node from the bit line and the bit line non-so as to decouple the storage node from the bit line.

7. The SRAM memory cell of claim 2, wherein said read word line and said first write word line are activated simultaneously when said SRAM memory cell performs a write 0 operation; the third PMOS tube and the fifth PMOS tube are in a closed state, the pull-up path of the first storage node is cut off, the first storage node is rapidly pulled down to 0 by the third NMOS tube and the fourth NMOS tube, and the second storage node is precharged to 1 by positive feedback, so that the 0 writing operation is completed.

8. The SRAM memory cell of claim 7, wherein said second write word line is disabled, a fifth NMOS transistor is turned off, and a bit line does not affect said second storage node;

when the SRAM memory cell executes the write 1 operation, the bit line is not at a low level, the read word line and the second write word line are at a high level, the fourth PMOS tube and the fifth PMOS tube are turned off, the pull-up path of the second memory node is cut off, the second memory node is pulled down to 0 by the fifth NMOS tube and the sixth NMOS tube, and the first memory node is precharged to 1 by positive feedback, so that the write 1 operation is completed.

9. The SRAM cell of claim 2, wherein for half-select cells on a same row, said third NMOS transistor and said fifth NMOS transistor are turned off by two column word lines, there is no coupling between a storage node and a bit line, and half-select destruction is not generated;

for half-select cells on the same column, the read word line is set low.

10. The SRAM memory cell of claim 9, wherein when performing a write 0 operation on a selected cell, a first write word line of a half-selected cell is enabled, said third NMOS transistor is turned on, said third PMOS transistor is turned off, and if a first storage node is set to 1, said first storage node is held to 1 by a fourth PMOS transistor, a fifth PMOS transistor, and a first PMOS transistor;

when the write 1 operation is executed on the selected unit, the second write word line is enabled, the fifth NMOS tube is opened, the fourth PMOS tube is turned off, and the third PMOS tube, the fifth PMOS tube and the second PMOS tube maintain the high level of the second storage node, so that the second storage node is ensured not to float; when the second storage node of the data stored in the half-selected cell is 0 or 1, none of the data stored in the cell changes.