JP2005321526A - Semiconductor integrated circuit system, display apparatus and system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit system, a display apparatus and a system in which desirable transient characteristics hardly influenced by load capacitance change is realized. <P>SOLUTION: A plurality of output circuits for outputting signals to a plurality of signal transmission lines extended in parallel, which consist of capacitive loads comprises; a first conductive type first output MOSFET whose source is connected to a first voltage terminal to which a first power voltage is supplied and whose drain is connected to the signal transmission line; a second conductive type second output MOSFET whose source is connected to a second voltage terminal to which a second power voltage is supplied and whose drain is connected to the signal transmission line; a first driving circuit which flows a constant current to a gate when turning the first MOSFET from OFF to ON according to the signal output; and a second driving circuit which switches the second MOSFET in a complementary style with the first MOSFET according to the signal output. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit device, a display device, and a system, and includes a driver that forms a plurality of output signals transmitted to a plurality of capacitive loads such as address electrodes of a plasma display panel (PDP), for example. The present invention relates to a semiconductor integrated circuit device and a technology effective for use in a display device and system using the same.

Japanese Patent Laid-Open No. 10-123998 discloses an example of an address driver that applies an address pulse signal in accordance with display data to an address electrode of a PDP. As shown in the general address driver circuit diagram shown in FIG. 17 of the publication, it is shown that the capacitance Cg of the address electrode and the parasitic capacitance Ca between adjacent addresses exist. In the address driver of the publication, it is described that power consumption is reduced by providing a time difference between the rise of the first address electrode and the fall of the second address electrode adjacent thereto.
JP-A-10-123998

  FIG. 17 shows an equivalent circuit diagram for explaining the load of the address driver of the PDP. The load of the address driver is composed of a pair sustain and pair scan capacity and an adjacent pin capacity. The adjacent pin capacitance corresponds to the parasitic capacitance Ca between the address electrodes as shown in FIG. When the drive output signal applied to the adjacent pins changes in the same direction, the pin capacitance cannot be seen as a capacitive load when viewed from the driver side. This adjacent pin capacity accounts for more than half of the capacitive load of the address driver. Therefore, in each address driver, the load varies depending on the change state of the drive output signal of the adjacent pin. That is, it becomes light when changing in phase as described above, and becomes heavy when changing in reverse phase. In a semiconductor integrated circuit device having a plurality of drivers, in the display mode for evaluating PDP, the lightest load is when all bits change in the same phase, and the load is heaviest when the adjacent address electrodes are respectively The staggered operation mode moves in the opposite direction.

  FIG. 18 shows a circuit diagram of an address driver studied prior to the present invention. Complementary display signals IN1 and / IN1 formed by a logic circuit having a low voltage V1 of 5V as an operating voltage are transmitted to the gates of N-channel MOSFETs M21 and M22 having the circuit supplied with the ground potential GND (VSS) of the circuit. . The drains of these N-channel MOSFETs M21 and M22 are supplied with a high voltage V2 of about 20V to 80V necessary for the PDP display operation, and the gates and drains are cross-connected to form a latch configuration of the P-channel MOSFETs M23 and M24. Connected to the drain. As a result, the display signal corresponding to the low voltage V1 is level-converted to a high voltage corresponding to the high voltage V2, and transmitted to the gate of the P-channel output MOSFET M27. In addition, the display formed by the above logic circuit is connected to the gate of the N-channel output MOSFET M28 connected in series with the P-channel output MOSFET M27 through a CMOS inverter circuit composed of the P-channel MOSFET M25 and the N-channel MOSFET M26 operating at the low voltage V1. A signal IN2 is supplied.

  FIG. 19 shows a load characteristic diagram of the simulation result of the transient time (for example, rise time, change time from 10% to 90% output) due to the load capacity of the address driver of FIG. In the circuit of FIG. 19, the load capacity and the transient time (time for changing 80% of the driver output) change almost linearly, and when the load capacity is small, the transient time becomes extremely short. When the load capacity is large, the transient time becomes longer. Therefore, as shown in the waveform diagram of FIG. 20, when all the bits operate simultaneously, the transient time is shortened as shown by the dotted line, and in the staggered operation mode in which the adjacent bits move in the opposite directions, the solid line shows. As shown, the transient time is increased.

  The driver output transient time is too long or too short. If it is too long, it may cause erroneous lighting (malfunction) such as lighting where it is not lit or lighting where it should be lit. However, there is a problem that radiation occurs when the transient time is too short. In the current PDP, it is necessary to preferentially take measures against lighting malfunction, so that the drivability of the address driver is sufficiently large, and the necessary transient is required even when the load capacity is large as in the worst case of the staggered operation. It needs to be designed to be time. As a result, when the load capacity is small as in the simultaneous operation of all bits, the change speed of the output signal becomes too fast and radiation is generated from the PDP. Such radiation from the PDP has a great effect on the cost and display efficiency of the PDP because a countermeasure is taken by putting a filter on the panel surface.

  An object of the present invention is to provide a semiconductor integrated circuit device that realizes desired transient characteristics that are less affected by changes in load capacitance, and a display device and system using the semiconductor integrated circuit device. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. In a plurality of output circuits that perform signal output to a plurality of signal transmission paths that are extended side by side and include capacitive loads, a source is connected to a first voltage terminal to which a first power supply voltage is supplied, and a drain is the signal transmission path. A first output MOSFET of the first conductivity type connected to the second voltage terminal and a second voltage terminal to which the first power supply voltage is supplied, a source connected to the first conductivity type, and a drain connected to the signal transmission path. A two-output MOSFET, a first drive circuit for causing a constant current to flow through the gate when the first output MOSFET is switched from an off state to an on state corresponding to the signal output, and the second output corresponding to the signal output A second drive circuit for switching the MOSFET in a complementary manner with the first output MOSFET;

  It is possible to achieve desired transient characteristics that are less affected by changes in load capacitance.

  FIG. 1 is a circuit diagram showing one embodiment of an address driver of a semiconductor integrated circuit device for driving an address electrode of a PDP according to the present invention. The address driver of this embodiment includes a level conversion (or level shift) circuit and an address driver or data driver (hereinafter simply referred to as an output circuit). The level conversion circuit converts a signal amplitude formed by an internal circuit such as a logic unit operating with a low voltage power source V1 such as 5V into a signal amplitude corresponding to a high voltage power source V2 such as 20 to 80V. It is provided to do. The output circuit is composed of a CMOS output circuit composed of a P-channel output MOSFET M7 and an N-channel output MOSFET M8 operated by the high-voltage power supply V2, and has a high level corresponding to the high voltage V2 from the output terminal OUT and a ground potential GND ( VSS) corresponding to VSS) is output.

  To the input terminals IN1 and IN2, a complementary input signal composed of a non-inverted signal and an inverted signal corresponding to the low power supply voltage V1 for controlling the operation of the P-channel output MOSFET M7 is supplied. The complementary input signal is level-converted from a low voltage V1 to a high voltage V2 by a level conversion circuit in order to perform on / off control of the P-channel output MOSFET Q7 operating with the high-voltage power supply V2. That is, the complementary input signal is supplied to the bases of differential NPN transistors Q1 and Q2. A series circuit of a switch SW1 and a current source I1 is provided between the common emitter of these differential transistors Q1 and Q2 and the ground potential GND (VSS) of the circuit. Between the collectors of the differential transistors Q1 and Q2 and the high voltage power supply V2, P-channel MOSFETs M1 and M2 in the form of current mirrors are provided. A level-converted output signal is obtained from the connection point between the output-side MOSFET M2 of the current mirror circuit and the collector of the transistor Q2, and is transmitted to the gate of the P-channel output MOSFET M7. Although not particularly limited, a Zener diode DZ having a Zener voltage equal to or lower than the gate breakdown voltage of the MOSFET M7 is provided between the gate and source (high power supply voltage V2) of the output MOSFET M7. The switch SW1 is supplied with an operation control signal supplied from the input terminal IN4, and the level conversion circuit is intermittently operated as described later in order to reduce power consumption.

  An input signal corresponding to the low power supply voltage V1 for controlling the operation of the N-channel output MOSFET M8 is supplied to the input terminal IN3. A constant current formed by the constant current source I2 is passed through the diode-connected P-channel MOSFET M3 via the switch SW2 controlled by the input signal supplied from the input terminal IN3. A constant current corresponding to the constant current I2 is supplied to the gate of the N-channel output MOSFET M8 through the MOSFET M3 and the P-channel MOSFET M4 in the form of a current mirror. In order to eliminate the waste of the constant flow of current by the constant current source I2 and the MOSFET M3, when the gate voltage of the MOSFET M8 reaches the low voltage V1, the switch SW2 is turned off. At this time, the gate of the output MOSFET M8 is connected to the output terminal of the CMOS inverter circuit composed of the P-channel MOSFET M5 and the N-channel MOSFET M6 in order to maintain the ON state, and after the switch SW2 is turned off, The low voltage V1 is supplied to the gate electrode of the MOSFET M8 through the P-channel MOSFET M5 which is turned on by the low level of the input signal supplied to the input terminal IN3. MOSFET M5 has a small size that allows a very small current to flow so that the gate voltage of MOSFET M8 does not decrease due to a leakage current.

  The address driver operation of this embodiment is as follows. When a high level output signal corresponding to the high voltage power supply V2 is formed from the output terminal OUT, a high level input signal is supplied to the input terminal IN3. In this case, the switch SW2 is turned off, the MOSFET M6 is turned on, and the output MOSFET M8 is turned off. When the switch SW1 is turned on by the input terminal IN4, a low-level input signal is supplied to the input terminal IN1, and a high-level input signal is supplied to the input terminal IN2, the differential transistor Q1 is turned off. The dynamic transistor Q2 is turned on.

  An equivalent circuit diagram for explaining the high-level output operation in the address driver of FIG. 1 is shown in FIG. 2, and its operating voltage waveform diagram is shown in FIG. FIG. 2 omits the Zener diode DZ for limiting the Vgs of the MOSFET M7 in FIG. 1 for ease of explanation. It is assumed that the maximum voltage Vgs of the MOSFET M7 is a difference voltage between V2 and GND. The on-state transistor Q2 and switch SW1 corresponding to the input signals of the input terminals IN4 and IN2 are shown as being replaced with one switch SW in FIG. Accordingly, the drive current I1 corresponding to the constant current of the constant current source I1 charges the gate-source parasitic capacitance Cgs of the P-channel output MOSFET M7. At this time, there is a parasitic capacitance Cgd between the gate and the drain, but the capacitance value seen from the gate side is increased by the Miller effect. For this reason, the current I1 acts as a current i1 for charging the gate-source parasitic capacitance Cgs having a relatively small capacitance value, and the gate-source voltage Cgd of the output MOSFET M7 as shown in FIG. Decrease linearly.

  When the gate-source voltage Vgs of the MOSFET M7 becomes larger than the threshold voltage, the MOSFET M7 is turned on, the output current io flows from the drain, and the address electrode connected to the output terminal OUT changes from the low level to the high level. To change. At this time, an address electrode of the PDP is connected to the output terminal OUT, and the parasitic capacitance existing between the ground potential of the circuit and the parasitic capacitance existing between the adjacent address electrodes is connected to the address electrode of the PDP. And a load capacity CL. The parasitic capacitance existing between the adjacent address electrodes can be regarded as not existing when viewed from the output terminal OUT when the adjacent address electrodes are also changed to a high level. Becomes smaller. On the other hand, when the adjacent address electrode remains at the low level, or conversely, when converting from the high level to the low level, the charging current is also supplied to the load address CL for the output circuit. . The load capacitance CL of the output circuit greatly changes due to such a change in the adjacent address electrode.

  In the output circuit of this embodiment, when the load capacitance CL is small, as shown in FIG. 3, a voltage Vgs1 in which the gate-source voltage Vgs of the P-channel MOSFET M7 linearly increased by the current I1 is relatively small is applied. Due to the drain current io of the MOSFET M7 flowing when the gate voltage VG1 is applied, the charging operation to the small load capacitor CL is started to raise the output terminal OUT. As the output terminal OUT rises, the current I1 is consumed in the discharge operation of the gate-drain parasitic capacitance Cgd of the MOSFET M7. As a result, the gate voltage VG1 (gate-source voltage Vgs1) becomes substantially constant, and the gate The address electrode rises linearly from the low level (L) to the high level (H) by a relatively small constant output current io corresponding to the voltage VG1.

  On the other hand, when the load capacitance CL is large, as shown in FIG. 3, the large load capacitance is obtained when the gate-source voltage Vgs of the P-channel MOSFET M7 formed by the current I1 is relatively small as described above. The potential change of CL is small, and the gate-source parasitic capacitance Cgs is charged so that the gate-source voltage Vgs is increased by the current I1. As the charging period becomes longer in this manner, the output MOSFET M7 causes a relatively large drain current io to flow by the gate voltage VG2 to which the increased gate-source voltage Vgs2 is applied, thereby charging the large load capacitance CL. Start and raise the output terminal OUT. As the output terminal OUT rises, the current I1 is consumed in the discharge operation of the gate-drain parasitic capacitance Cgd of the MOSFET M7. As a result, the gate voltage VG2 (gate-source voltage Vgs2) is substantially constant. The address electrode rises linearly from the low level (L) to the high level (H) by a relatively large constant output current io corresponding to the gate voltage VG2.

  In this embodiment, as described above, when the N-channel output MOSFET M8 is in the OFF state and the output from the P-channel output MOSFET M7 transitions from the low level to the high level, the P-channel MOSFET M7 turns on the constant current source I1 by turning on the switch SW1. The charge / discharge operation of the parasitic capacitances Cgs and Cgd is performed by the current I1. The output rise speed tr at this time is mainly determined by the discharge speed (slew rate) of the parasitic capacitance Cgd by the current source I1 as described above. As a result, the gate voltage VG of the P-channel MOSFET M7 is balanced by the gate-source Vgs which becomes the driver current io corresponding to the load capacitance CL and its rising speed tr. This is a section in which the gate voltage VG becomes constant in the rising process in FIG. The driver current io required at this time is io = V2 (high level) × CL / tr. Therefore, the larger the capacitance value of the load capacitor CL and the faster (smaller) the rising speed tr, the larger the driver current io of the P-channel MOSFET driver, and the larger the gate-source voltage Vgs of the P-channel MOSFET M7.

  In the circuit of this embodiment, when the gate of the P-channel output MOSFET M7 is grounded to GND, the gate-source voltage Vgs of the P-channel MOSFET driver is maximized, and the driver current io of the P-channel output MOSFET M7 is also maximized. Become. Thereafter, since the driver current io of the P-channel output MOSFET M7 is constant at the maximum value, the rising speed tr changes when the load capacitance changes in the above equation (1). That is, in the circuit as shown in FIG. 18, since the gate-source voltage Vgs is determined by the maximum voltage, the driver current io is always used at a maximum current and a constant current. It changes linearly with changes in CL. On the other hand, if the rising speed tr is determined by the slew rate and the load is used within the maximum driver current in the formula io = V2 (high level) × CL / tr, the rising speed tr changes even if the load capacitance CL changes. It can be controlled not to.

  In this way, the rise of the output terminal OUT can be made substantially the same regardless of the magnitude (variation) of the load capacitance. In other words, when the load capacitance CL is small, a small output current io corresponding thereto is formed, and when the load capacitance CL is large, a large output current io corresponding thereto is formed. As described above, the output terminal OUT The rise is almost the same. However, in order to realize the operation as described above, it is necessary that the P-channel MOSFET M7 has sufficient drivability to realize the rising characteristics. That is, the output MOSFET M7 requires drivability that can obtain the output current io that can realize the required rise characteristic even with the voltage Vgs1 or the voltage Vgs2 smaller than the power supply voltage V2.

  The maximum value of the gate-source voltage Vgs of the MOSFET M7 is limited by the Zener diode DZ, and the gate voltage of the MOSFET M7 is limited by the Zener voltage, thereby preventing gate breakdown. In order to form the MOSFET M7 so as not to cause gate dielectric breakdown under the high voltage power source V2 such as 20 to 80V as described above, the gate insulation is not performed at the worst case of 80V. Although the device manufacturing process becomes complicated by forming a thick insulating film, in this embodiment, by providing the Zener diode DZ, a special withstand voltage process is applied to the high operating voltage V2 in a wide range of 20 to 80V. It can be operated stably without implementation. In this case, the gate-source voltage Vgs of the P-channel output MOSFET M7 limited by the Zener diode DZ is maximized, and the driver current io is also maximized. Similarly, even if the load capacitance CL changes within a range not exceeding the maximum drivability, the rising speed tr can be controlled so as not to change.

  As described above, since the address electrode is a capacitive load, the MOSFET M7 needs to supply only a current sufficient to compensate for the leakage current when the address electrode becomes a high level corresponding to the high voltage power supply V2. Further, the MOSFET M7 can be kept on by the gate-source voltage Vgs held in the gate-source parasitic capacitance Cgs. Therefore, a drive pulse is supplied from the input terminal IN4, and the switch SW1 is turned on in response to a signal transition period in which the output terminal OUT is changed from a low level to a high level, thereby obtaining a high level output signal. If so, the switch SW1 is turned off to prevent the current I1 of the current source I1 from continuing to flow through the Zener diode DZ, thereby reducing the current consumption in the level conversion circuit.

  An equivalent circuit diagram for explaining the low-level output operation in the address driver of FIG. 1 is shown in FIG. 4, and its operating voltage waveform diagram is shown in FIG. Although omitted in FIG. 4, the differential transistor Q1 of the level conversion circuit is turned on, current is supplied from the current mirror MOSFET M2 to the gate electrode of the output MOSFET M7, and the gate voltage is changed from low level to high level for output. The MOSFET M7 is turned off. Then, the switch SW2 is turned on by an input signal of the input terminal IN3, and a constant current is supplied to the gate of the N-channel output MOSFET M8 through the current mirror circuit of the MOSFET M3-M4. Thus, as in the case of the P-channel output MOSFET M7, when the N-channel output MOSFET M8 is turned on and the output terminal OUT is changed from the high level to the low level, the gate of the output MOSFET M8, the parasitic capacitance Cgs between the source and the gate, Charging and discharging of the drain-to-drain parasitic capacitance Cgd is started corresponding to the magnitude of the load capacitance CL, and as shown in FIG. 5, a constant output current corresponding to the original gate voltage VG of the constant voltage Vgs is applied to the output terminal OUT. The connected load capacitance CL can be discharged from the high level to the low level.

  FIG. 5 shows an example of one load capacitor CL. However, when the load capacitance is larger than the example of FIG. 5, the gate and source of the output MOSFET M8 with constant current are applied as in the case of the P-channel output MOSFET M7. The time required for switching from the charging operation of the inter-parasitic capacitance Cgs to the discharging operation of the parasitic capacitance Cgd between the gate and drain becomes longer, and the gate voltage under the gate-source voltage Vgs larger than the constant voltage Vgs shown in FIG. The load capacitance CL connected to the output terminal OUT is discharged by a large constant output current corresponding to VG. On the other hand, when the load capacitance is smaller than the example in the figure, the time required for switching from the charging operation of the gate / source parasitic capacitance Cgs of the output MOSFET M8 by the constant current to the discharging operation of the gate / drain parasitic capacitance Cgd. The load capacitance CL connected to the output terminal OUT is discharged by a small constant output current corresponding to the original gate voltage VG of the gate-source voltage Vgs smaller than the constant voltage Vgs of FIG.

  In this embodiment, the switch SW2 is turned off when the gate voltage of the MOSFET M8 reaches the low voltage V1 in order to eliminate the waste of the constant flow of current by the constant current source I2 and the MOSFET M3. Although not particularly limited, the switch SW2 is configured by an N-channel MOSFET and is turned on by the high level of the input terminal IN3. The input signal IN3 supplied to the inputs of the MOSFETs M5 and M6 is different from the switch SW. Although an input signal is supplied and is not particularly limited, the P-channel MOSFET M5 is turned on when the switch SW2 is turned on and at a low level. However, since the current of the MOSFET M5 is made small enough to compensate for the leakage current, it is not substantially involved in the switching operation as described above. An inverted signal of the input terminal IN3 may be formed and supplied to the gates of the MOSFETs M5 and M6. In this case, the MOSFET M5 is turned on when the constant current of the MOSFET M4 is cut off.

  FIG. 6 is a characteristic diagram for explaining the address driver of FIG. This characteristic diagram is a simulation result showing the relationship of the transient time corresponding to the load capacity. For comparison, the characteristics of the address driver shown in FIG. 19 are also shown. In the load characteristics with constant current drive of this embodiment, when the transient time (rise speed tr) is almost constant at the slew rate, the capacitive load when driving all bits and the capacitive load during staggered operation If the P-channel and N-channel MOSFETs have the same configuration, the case of all bit operations (small CL) indicated by the dotted line as shown in the output waveform diagram of FIG. As in the case of CL large), the fluctuation of the transient time between the rising edge and the falling edge can be suppressed to a small time difference Δt1. That is, it can be greatly improved compared to the large transient time difference Δt2 of the address driver of FIG.

  FIG. 8 is a circuit diagram showing another embodiment of the address driver according to the present invention. In this embodiment, the following circuit is used as a level conversion circuit for performing the switching operation of the P-channel output MOSFET M19. Input terminals IN1 and IN2 to which complementary input signals are supplied are supplied to the gates of N-channel MOSFETs M10 and M11. The sources of these MOSFETs M10 and M11 are given a circuit ground potential GDN. Between the drains of the MOSFETs M10 and M11 and the high voltage power supply V2, latch-type P-channel MOSFETs M12 and M13 are provided in which the gate and the drain are cross-connected. An output signal obtained from the drain connection point of the MOSFETs M13 and M11, which has been level-converted to the high voltage V2 corresponding to the input signals supplied to the input terminals IN1 and IN2, is transmitted to the gate of the P-channel MOSFET M14. The drain of the MOSFET M14 is connected to the gate of the P-channel output MOSFET M19.

  A switch SW1 and a constant current source I1 are provided between the gate of the P-channel MOSFET M14 and the circuit ground potential. As a result, the input signal IN1 is set to the high level, the input signal IN2 is set to the low level, and the P-channel MOSFET M14 is turned off. As in the circuit shown in FIG. Charge and discharge the gate-source parasitic capacitance and the gate-drain parasitic capacitance. Thus, as described above, the output signal is raised from the low level to the high level with substantially the same slew rate without being affected by the magnitude of the load capacitance due to the drive signal supplied to the adjacent address electrode connected to the output terminal OUT. Can be.

  In this embodiment, since the output MOSFET M19 is formed to have a sufficiently high breakdown voltage, the Zener diode for protecting the gate breakdown voltage as shown in FIG. 1 is omitted. Accordingly, the pulse driving is also omitted. Even if the switch SW1 is kept on, no direct current as described above flows. The MOSFET M14 performs an operation of turning off the P-channel output MOSFET M19 by being turned on by the low level of the output signal of the level conversion circuit. The constant current drive circuit for driving the N-channel output MOSFET M20 includes MOSFETs M15 to M18, a switch SW2, and a constant current source I2 similar to those in FIG.

  In the embodiment of FIG. 8, the MOSFET 17 is changed to a size slightly larger than that which compensates for the leakage current, and the MOSFET M17 is turned on before the switch SW2 is turned on. By setting the level of the input signal supplied to the input terminal IN3 so as to be in the state, the harmonic component generated at the time of the fall of the address electrode drive signal output from the output terminal OUT can be reduced.

  FIG. 9 is a waveform diagram for explaining an example of the operation of the address driver of FIG. In the figure, as described above, in order to reduce the harmonic component generated when the drive signal falls, the input terminal IN3 is set to the low level to turn on the P-channel MOSFET M17. As a result, the gate voltage of the MOSFET M8 gradually rises, and the corner of the falling start portion can be cut correspondingly. Thereafter, the switch SW2 is turned on and a constant current corresponding to the slew rate is supplied to perform the above-described operation. Radiation can be further reduced by reducing such harmonic components.

  FIG. 10 is a circuit diagram showing still another embodiment of the address driver according to the present invention. This embodiment is a modification of FIG. 1 in which harmonic components generated at the fall of the drive signal are reduced in the same manner as described above. The address driver of FIG. 1 is to drive the output MOSFET M8 with a constant current to realize a desired slew rate. Therefore, the harmonic component is reduced by switching the drive current. . That is, a constant current source I3 and a switch SW3 having a relatively small current are added to the embodiment circuit of FIG. 1 so that the constant current I3 flows through the MOSFET M3 in parallel with the constant current source I2 and the switch SW2. It is to make. A circuit for driving the P-channel output MOSFET M7 at a constant current is constituted by the circuit shown in FIG.

  FIG. 11 is a waveform diagram for explaining an example of the operation of the address driver of FIG. In the figure, as described above, in order to reduce the harmonic component generated when the drive signal falls, the input terminal IN3 is set to the low level to turn on the P-channel MOSFET M5. At the same time, the switch SW3 is turned on to lower the drive signal at a low slew rate with a small constant current I3, thereby removing the harmonic component at the start of the fall. Then, the switch SW2 is turned on to allow a constant current I2 corresponding to the original slew rate to flow. At this time, since the slew rate is determined by the current I3 + I2, if the slew rate is the same as that of the circuit of FIG. 1, it is sufficient that I3 + I2 becomes the constant current I2 shown in FIG.

  After a certain period of time before the drive signal becomes low level (GND), the switch SW2 is turned off, and the drive signal is lowered at a low slew rate with a small constant current I3 at the same time as the start of the fall. Remove harmonic components at the end. When the drive signal becomes low level, the switch SW3 is also turned off to reduce current consumption. At this time, the output MOSFET M8 is kept on by the current from the MOSFET M5.

  FIG. 12 is a circuit diagram showing still another embodiment of the address driver according to the present invention. This embodiment is a modification of FIG. 1 in which the harmonic component generated at the rising edge of the driving signal is reduced as in the case of the falling edge of the driving signal. In the figure, it is shown in the form of an equivalent circuit diagram corresponding to FIG. When applied to the circuit of FIG. 1, a parallel circuit of a switch SW1, a constant current source I1, and a switch SW4, a constant current source I4 is provided between the common emitters of the differential transistors Q1 and Q2 and the ground potential of the circuit. . The principle of reducing harmonic components in this embodiment is the same as in the case of the N-channel output MOSFET M8. A constant current source I4 and a switch SW4 having a relatively small current are added to the constant current source I1 and the switch. In parallel with SW1, constant currents I4 and I1 are used when the drive signal rises.

  FIG. 13 is a waveform diagram for explaining an example of the operation of the address driver of FIG. In the figure, in order to reduce the harmonic component generated at the rise of the drive signal as described above, the switch SW4 is turned on, the drive signal is raised at a low slew rate with a small constant current I4, and the rise starts. Remove harmonic components of time. Then, the switch SW1 is turned on to allow a constant current I1 corresponding to the original slew rate to flow. At this time, since the slew rate is determined by the current I4 + I1, if the slew rate is the same as that of the circuit of FIG. 1, it is sufficient that I4 + I1 becomes the constant current I1 shown in FIG.

  After a certain period of time before the drive signal becomes high level (V2), the switch SW1 is turned off, and the drive signal is raised at a low slew rate with a small constant current I4 as at the start of the fall. Remove harmonic components at the end. When the drive signal becomes low level, the switch SW1 is also turned off in the embodiment circuit of FIG. 1 to reduce current consumption. The MOSFET M7 is kept on with the voltage held in the gate-source parasitic capacitance Cgs. When the level conversion circuit as in the embodiment of FIG. 8 is used, the current consumption does not increase even if the switch SW4 is kept on.

  FIG. 14 is an overall block diagram showing one embodiment of a semiconductor integrated circuit device LSI according to the present invention. Each block in the figure is shown according to the geometrical arrangement of each circuit block on a semiconductor substrate (LSI). In the semiconductor integrated circuit device, a driver part and a control part are divided into upper and lower parts. In the driver unit, the logic unit is arranged at the center of the semiconductor integrated circuit device, and a level shift (the level conversion circuit) and a driver are arranged on both sides thereof. As a result, the output terminals OUT for driving the address electrodes of the PDP are arranged side by side from both sides of the semiconductor integrated circuit device of FIG. The control unit and the logic unit are operated by the low voltage power supply V1, and the high power supply voltage V2 is supplied to the level shifter and the driver to perform the operation as described above. A latch is provided corresponding to the level shift as a circuit for forming the address driver (data driver) and its drive signal. This latch is provided in the logic unit. A display signal held in the latch is output through the shift register driver. The control unit also includes an input interface circuit that receives a clock and input data.

  FIG. 15 is a schematic block diagram showing one embodiment of a plasma display panel apparatus to which the present invention is applied. The PDP device shown in FIG. 1 includes a plasma display panel 1, an X electrode drive circuit 2, a Y electrode drive circuit 3, an address electrode drive circuit (semiconductor integrated circuit device) 4, and the like. The plasma display panel 1 is provided with an X electrode 5, a Y electrode 6, and an address electrode 7. The X electrode drive circuit 2 outputs an X pulse to be applied to the X electrode 5 based on the drive pulse. The Y electrode drive circuit 3 outputs a Y pulse applied to the Y electrode 6 based on the drive pulse. The address electrode drive circuit 4 is composed of a plurality of the semiconductor integrated circuit devices LSI shown in the embodiment of FIG. 3 corresponding to the address electrodes provided in the plasma display panel 1, and based on display data. An address pulse applied to the address electrode 7 is output. The display data includes, for example, image bit data and a latch signal.

  In the PDP apparatus of this embodiment, for example, in order to obtain 256 gradations (8 bits), one field of a certain time is divided into 8 subfields having different relative luminance ratios, and the least significant bit of the image bit information Subfields are configured in order from the most significant bit. One subfield is composed of three types of periods: a reset period, an address period, and a sustain discharge period. In the reset period, the three operations of all screen batch erase, all screen batch write, and all screen batch erase are sequentially performed. In the address period, an operation of sequentially writing image bit information, which is one of display data assigned to each subfield, for each line is performed. The address electrode 7 outputs image bit information for n rows corresponding to the number of display lines as serial data in order from the first row. At this time, in each address electrode, an address pulse is selectively applied only to the discharge cells to be displayed.

  In response to the serial data applied to the address electrode 7, the Y electrode 6 has a scan pulse for setting a voltage of 0 V in the same phase as the address pulse, one row at a time from the first electrode in the Y electrode 6. Applied. Thereby, image bit information is written only when an address pulse is applied to the address electrode 7 and a scan pulse is applied to the Y electrode 6. In the sustain discharge period, a sustain pulse for maintaining the discharge is alternately applied to the Y electrode 6 and the X electrode 5. At this time, the address electrode 7 is fixed at 0 V, but is re-discharged only by the wall charges and the sustain pulse remaining in the discharge cells in which the image bit information is written in the address period.

  FIG. 16 is a block diagram showing an embodiment of a microcomputer system to which the present invention is applied. In this embodiment, a memory circuit SDRAM and a signal processing circuit ASIC are connected via an address bus A and a data bus D with a central processing unit CPU as a center. In addition, a CLK line for supplying a clock from the central processing unit CPU to the memory circuit SDRAM and the signal processing circuit ASIC is provided. In the case of the CPU of this embodiment, the CPU and the SDRAM are closely coupled to ensure a large bandwidth with the memory circuit SDRAM which is the main memory. Further, a flash memory FLASH is connected through the signal processing circuit ASIC as a fixed storage for storing an IPL for bootstrap. Since the flash memory FLASH does not require a very large bandwidth, it is loosely coupled with the CPU.

  The problem to be solved by the present invention is to improve the slew rate accompanying the change in load capacity due to adjacent transmission signals in a plurality of signal transmission paths that are extended side by side and composed of capacitive loads. Similar to the address electrodes, the address bus A is arranged with 26 signal lines arranged side by side, and the data bus D is arranged with 32 signal lines arranged side by side. When the CPU has a 64-bit configuration or a 128-bit configuration, the data bus D has 64 or 128 signal lines arranged side by side. Therefore, when these bus drivers are configured with CMOS circuits as in the prior art, setting the slew rate corresponding to the maximum value of the load fluctuation described above causes the slew rate to be too high at the time of the minimum load, causing overshoot and undershoot. In addition to the generation, a large noise is generated in the power supply line. Further, in a signal composed of a plurality of bits, the transmission speed between the signals varies and a large skew is generated, which makes high-speed signal transmission difficult. Therefore, by driving the CMOS output circuit at a constant current as described above, the slew rate can be set almost constant without being affected by the magnitude of the load capacitance that changes in response to the signal change transmitted to the adjacent signal line. it can. As a result, in the bus driver that drives the data bus D and the address bus A, the skew between the transmission signals can be reduced while preventing the generation of the power supply noise, thereby enabling high-speed signal transmission.

  In such a semiconductor integrated circuit device such as a CPU or ASIC, an internal circuit is operated at a low voltage of about 1.2 V, and an input / output circuit that exchanges signals with the outside is 3.3 V. Some of them can be operated at such a high voltage. In this case, a level conversion circuit that converts the signal amplitude of 1.2V to a signal amplitude of 3.3V is required. Therefore, the level conversion circuit as shown in FIGS. 1 and 8 is used as it is. An output driver can be configured. In the case of FIG. 1, the differential transistors Q1 and Q2 can be replaced with MOSFETs.

  In the present invention described above, it is possible to prevent the problem of radiation from occurring due to the transient time being too short when the load is light. A rising / falling characteristic with less radiation can be realized by changing the falling waveform and the rising waveform. Therefore, when applied to an address driver, it is possible to take a radiation countermeasure filter from the PDP panel. In this application, the characteristics are determined by the current-driven slew rate, and the slew rate characteristic is not determined by the drivability of the external load and output as in the past. Is not too fast. Further, by changing the drive current when the output is changing, the rising / falling waveform can be made more difficult to emit radiation.

  Although the invention made by the inventor has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. For example, in the embodiment of FIG. 1, when the differential transistors Q1 and Q2 are formed by a CMOS process, a P-type well in which an N-channel MOSFET is formed is used as a base region, and source and drain diffusion layers are used as an emitter and a collector. Such a lateral type transistor or a vertical type transistor may be formed by bipolar-CMOS circuit technology. The present invention relates to a semiconductor integrated circuit device having a plurality of output circuits that perform signal output to a plurality of signal transmission paths that are extended side by side like a PDP address electrode driver and are composed of capacitive loads, and a configuration using the same Widely used in display devices and systems.

1 is a circuit diagram showing an embodiment of an address driver of a semiconductor integrated circuit device for driving an address electrode of a PDP according to the present invention. FIG. FIG. 2 is an equivalent circuit diagram for explaining a high level output operation in the address driver of FIG. 1. FIG. 3 is an operation voltage waveform diagram corresponding to FIG. 2. FIG. 2 is an equivalent circuit diagram for explaining a low-level output operation in the address driver of FIG. 1. FIG. 5 is an operation voltage waveform diagram corresponding to FIG. 4. FIG. 2 is a characteristic diagram for explaining the address driver of FIG. 1. FIG. 2 is an output waveform diagram of the address driver of FIG. 1. It is a circuit diagram showing another embodiment of the address driver according to the present invention. FIG. 9 is a waveform diagram for explaining an example of the operation of the address driver of FIG. 8. FIG. 7 is a circuit diagram showing still another embodiment of the address driver according to the present invention. FIG. 11 is a waveform diagram for explaining an example of the operation of the address driver of FIG. 10. FIG. 7 is a circuit diagram showing still another embodiment of the address driver according to the present invention. FIG. 13 is a waveform diagram for explaining an example of the operation of the address driver of FIG. 12. 1 is an overall block diagram showing an embodiment of a semiconductor integrated circuit device LSI according to the present invention. It is a schematic block diagram which shows one Example of the plasma display panel apparatus with which this invention is applied. It is a block diagram which shows one Example of the microcomputer system to which this invention is applied. FIG. 3 is an equivalent circuit diagram for explaining a load of an address driver of a PDP. It is a circuit diagram of an address driver examined prior to the present invention. FIG. 19 is a load characteristic diagram of a simulation result of transient time depending on the load capacity of the address driver of FIG. 18. It is a wave form diagram of the address driver of FIG.

Explanation of symbols

Q1, Q2 ... transistor, M1-M28 ... MOSFET, SW1-SW4 ... switch means, I1-I4 ... current source, DZ ... zener diode, Cgs, Cgd ... parasitic capacitance,
DESCRIPTION OF SYMBOLS 1 ... Plasma display panel, 2 ... X electrode drive circuit, 3 ... Y electrode drive circuit, 4, 4a-4c ... Address electrode drive circuit, 5 ... X electrode, 6 ... Y electrode, 7 ... Address electrode,

Claims (13)

A plurality of output circuits that are extended side by side and that should output signals to each of a plurality of signal transmission paths composed of capacitive loads;
A first voltage terminal to which a first power supply voltage is supplied;
A second voltage terminal to which a second power supply voltage is supplied,
The output circuit is
A first output MOSFET of a first conductivity type whose source is connected to the first voltage terminal and whose drain is to be connected to each of the plurality of signal transmission paths;
A second output MOSFET of a second conductivity type whose source is connected to the second voltage terminal and whose drain is to be connected to each of the plurality of signal transmission paths;
A first drive circuit for causing a constant current to flow through the gate when the first output MOSFET is turned from an off state to an on state in response to the signal output;
A semiconductor integrated circuit device comprising: a second drive circuit for switching the second output MOSFET in a complementary manner with the first output MOSFET in response to the signal output. In claim 1,
2. The semiconductor integrated circuit device according to claim 1, wherein the second drive circuit is configured to cause a constant current to flow through the gate when the second output MOSFET is turned from an off state to an on state in response to the signal output. In claim 2,
The first and second drive circuits are connected to a third voltage terminal to which a third power supply voltage smaller than the first power supply voltage is supplied and a fourth voltage terminal to which the second power supply voltage is supplied,
The semiconductor integrated circuit device, wherein the second power supply voltage is a ground potential of the circuit. In claim 3,
The first drive circuit includes:
A differential transistor for receiving a complementary signal corresponding to the third power supply voltage;
A current mirror type MOSFET provided between the collector of the differential transistor and the first voltage terminal;
A first switch provided between the common emitter of the differential transistor and the fourth voltage terminal; and a series circuit of a first constant current source,
The semiconductor integrated circuit device according to claim 1, wherein the first switch is turned on for a certain period of time to turn the first output MOSFET from an off state to an on state. In claim 4,
The first output MOSFET of the first conductivity type is a P-channel MOSFET, and a Zener diode having a gate breakdown voltage or lower is provided between the gate and the source. In claim 3,
The first drive circuit includes:
A complementary signal corresponding to the third power supply voltage is received at the gate, and a source is connected to the fourth voltage terminal between the pair of N channel MOSFETs, and between the drain of the pair of N channel MOSFETs and the first voltage terminal. A signal level corresponding to the third power supply voltage is converted into a signal level corresponding to the first power supply voltage. A level conversion circuit;
A drive P-channel MOSFET that receives the output signal of the level conversion circuit at the gate and short-circuits the gate and source of the first output MOSFET to turn them off;
A first switch provided between the drain of the drive P-channel MOSFET and the fourth voltage terminal and turned on in a complementary manner with the drive P-channel MOSFET; and a series circuit of a first constant current source. A semiconductor integrated circuit device. In claim 3,
The second drive circuit includes:
A second constant current source having one end connected to the fourth power supply terminal;
A second switch having one end connected to the second constant current source;
A first P-channel MOSFET in the form of a die auto provided between the second switch and the third voltage terminal;
Including a first P-channel MOSFET and a second P-channel MOSFET in the form of a current mirror;
A semiconductor integrated circuit device, wherein a drain output current of the second P-channel MOSFET is supplied to a gate of the second output MOSFET. In claim 7,
The second drive circuit further includes a CMOS inverter circuit that operates at the second power supply voltage,
In the CMOS inverter circuit, an input signal corresponding to the output signal is supplied to an input terminal, an output terminal is connected to a gate of the second output MOSFET,
The P-channel MOSFET constituting the CMOS inverter circuit has a small current supply capability for maintaining the gate voltage of the second output MOSFET at the voltage of the third voltage terminal, and has a smaller current supply capability than the second drive circuit. A semiconductor integrated circuit device characterized by being made. In claim 7,
The semiconductor integrated circuit device, wherein the P-channel MOSFET of the CMOS inverter circuit is turned on before the second switch is turned on. In claim 6,
The first constant current source is
A first circuit that forms a relatively small current and a second circuit that forms a relatively larger current than the first circuit;
The first switch includes a third switch corresponding to the first circuit and a fourth switch corresponding to the second circuit,
A semiconductor integrated circuit device, wherein the fourth switch is turned on after the third switch is turned on. In claim 7,
The second constant current source is
A third circuit that forms a relatively small current and a fourth circuit that forms a relatively larger current than the third circuit;
The second switch includes a fifth switch corresponding to the third circuit and a sixth switch corresponding to the fourth circuit,
A semiconductor integrated circuit device, wherein the sixth switch is turned on after the fifth switch is turned on. A plurality of output circuits that are extended side by side and that should output signals to each of a plurality of signal transmission paths composed of capacitive loads;
A first voltage terminal to which a first power supply voltage is supplied;
A second voltage terminal to which a second power supply voltage is supplied,
The output circuit is
A first output MOSFET of a first conductivity type whose source is connected to the first voltage terminal and whose drain is to be connected to each of the plurality of signal transmission paths;
A second output MOSFET of a second conductivity type whose source is connected to the second voltage terminal and whose drain is to be connected to each of the plurality of signal transmission paths;
A first drive circuit for causing a constant current to flow through the gate when the first output MOSFET is turned from an off state to an on state in response to the signal output;
A semiconductor integrated circuit device comprising: a second drive circuit that complementarily switches the second output MOSFET with the first output MOSFET in response to the signal output;
A display device comprising: a plasma display panel in which the plurality of signal transmission paths are address electrodes. A plurality of output circuits that are extended side by side and that should output signals to each of a plurality of signal transmission paths composed of capacitive loads;
A first voltage terminal to which a first power supply voltage is supplied;
A second voltage terminal to which a second power supply voltage is supplied,
The output circuit is
A first output MOSFET of a first conductivity type whose source is connected to the first voltage terminal and whose drain is to be connected to each of the plurality of signal transmission paths;
A second output MOSFET of a second conductivity type whose source is connected to the second voltage terminal and whose drain is to be connected to each of the plurality of signal transmission paths;
A first drive circuit for causing a constant current to flow through the gate when the first output MOSFET is turned from an off state to an on state in response to the signal output;
A semiconductor integrated circuit device comprising: a second drive circuit that switches the second output MOSFET in a complementary manner with the first output MOSFET in response to the signal output;
The signal transmission path is an address bus or a data bus,
The semiconductor integrated circuit device comprises a central processing unit or a memory circuit connected to the address bus or data bus.

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