JP3237644B2 - Level conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level conversion circuit, and more particularly to a level conversion circuit which receives an input signal of a first power supply system, latches the input signal, and provides a second power supply system having a higher potential than the first power supply potential. The present invention relates to a level conversion circuit that outputs a voltage signal.

[0002]

2. Description of the Related Art FIG. 8 is a diagram showing a configuration of a conventional level conversion circuit of this kind. As the circuit configuration shown in FIG. 8, for example, FIG. 3 of JP-A-4-192622 and its related description, or FIG. 6 of JP-A-9-2000020 and its related description are referred to. Referring to FIG. 8, this level conversion circuit has a first N-channel MO having a source grounded and a gate connected to an input terminal VIN to which a signal having a first power supply voltage (VCC) amplitude is input.
An S-transistor N1, an inverter INV having an input terminal connected to the input terminal VIN, a second N-channel MOS transistor N2 having a source grounded and a gate connected to the output terminal ("node A") of the inverter, A first P-channel MOS transistor having a source connected to a power supply terminal VPP to which a power supply voltage higher than the first power supply voltage VCC is applied, and a drain connected to a drain of the first N-channel MOS transistor N1 P1; a second P-channel MOS transistor P2 having a source connected to the power supply terminal VPP and a drain connected to the drain of the second N-channel MOS transistor N2;
The gate of the first P-channel MOS transistor P1 is
The gate of the second P-channel MOS transistor P2 is connected to the drain of the second N-channel MOS transistor N2 (referred to as “node C”), and the drain of the first N-channel MOS transistor N1 (referred to as “node B”). The connection point between the drain of the second N-channel MOS transistor N2 and the drain of the second P-channel MOS transistor P2 is connected to a third P-channel MOS transistor connected in series between the power supply terminal VPP and the ground. Transistor P3 and third N-channel MOS transistor N3
And a connection point between the drain of the third P-channel MOS transistor P3 and the drain of the third N-channel MOS transistor N3 is connected to the output terminal VOU.
Connected to T.

Here, the current driving capability of the first and second P-channel MOS transistors P1 and P2, which are active load elements, is proportional to the gain coefficient β and proportional to the W / L ratio.
Are the first and second N-channel MOS transistors N1,
N1 is set smaller than the current driving capability of N2, and first and second P-channel MOS transistors P1 and P2 forming active load elements and first and second gates forming differential switches.
And the drains of the second N-channel MOS transistors N1 and N2 are cross-connected to each other.
An input signal of the first power supply voltage amplitude input to the input terminal is latched, and the latch output is latched by a third P-channel MOS.
Drain of transistor P3 and third N-channel MOS
The CMOS inverter including the transistor N3 is configured to invert and output.

FIG. 9 is a diagram showing timing waveforms of respective nodes, ie, VIN, node A, node B, node C, and VOUT in the conventional level conversion circuit shown in FIG. The operation of the conventional level conversion circuit will be described with reference to FIGS.

When the input signal from the input terminal VIN switches from the high level of the first power supply voltage (VCC) amplitude to the low level, the first N-channel MOS transistor N1 is turned off, and the output of the inverter INV is input to the gate. A second N-channel MOS transistor N
2 is turned on from the off state, and the second N channel M
The node C, which is the drain of the OS transistor N2, is Lo.
The first P-channel MOS transistor P1 which is pulled down to the w level and has the potential of the node C as a gate input is turned on, and thereafter, the second P-channel MOS transistor P1 is turned on.
2 turns off.

When the node C goes low, the level of the output terminal VOUT goes high in response to the output of the CMOS inverter to which the potential of the node C is input.

After the output level at the output terminal VOUT is determined, the power supply voltage supplied to the power supply terminal VPP is changed from the first power supply voltage (VCC) to a potential higher than the first power supply voltage (VCC). Boosted potential level (second
(This operation sequence is shown in FIG. 9).
Is not shown in the timing chart of FIG. That is,
Instead of always supplying a high voltage to the power supply terminal VPP,
After the output level of the level shift circuit is determined (that is, when the latch output is determined), VP
By supplying a high voltage as P, power consumption of the device is reduced, and it is also preferable in terms of withstand voltage of the element,
Such power supply switching control is performed. Needless to say, in FIG. 8, a configuration in which a high voltage (second power supply voltage) is always applied to the power supply terminal VPP may be adopted. In this case, for example, a threshold value is set so that the transistors N1 and N2 are turned on / off by an input signal having a logic amplitude of the first power supply voltage (VCC), and the transistors P1 and N2 are
The threshold value of P2 is set so that on / off control is performed on the basis of the drain voltages of the transistors N2 and N1.

[0008]

By the way, in the above-mentioned conventional level conversion circuit, the second N-channel MO is used.
The S transistor N2 is turned on, and the second P-channel MOS
There is a time difference until the transistor P2 is turned off, during which time the second N series connected in series between the power supply terminal VPP and the ground.
Channel MOS transistor N2 and second P-channel M
Since both OS transistors P2 are turned on, problems such as an increase in signal propagation delay time and an increase in current consumption occur.

In order to solve this problem, it is necessary to turn off the second P-channel MOS transistor P2 quickly. That is, from the Low level of the node B to the Hi level
It is necessary to speed up the rise time to the gh level.

However, in the conventional level conversion circuit shown in FIG. 8, the node C is changed from high level to low level.
When changing to the low level, the node B is pushed down to the lower potential side, that is, the minus potential due to the coupling of the gate-drain capacitance of the second P-channel MOS transistor P2. Even if the pull-up is performed by the first P-channel MOS transistor P1 in the ON state, the node B changes from the low level to the high
The rise to the level is delayed, which is the limiting factor. .

More specifically, referring to FIGS. 8 and 9, the voltage of the input terminal VIN is changed from the high level to the low level.
In the process in which the second N-channel MOS transistor N2 is turned on and the node C falls to the low potential from the point in time when the level changes to the low level, the potential of the node B is changed by the gate-drain capacitance of the second P-channel MOS transistor P2. , Below the ground potential (OV) (see timing (b) in FIG. 9), and thereafter, the node B is pulled up by the first P-channel MOS transistor P1. Therefore, the node B is slower than the output VOUT,
It is rising to a high level.

As a result, there is a time difference before the second N-channel MOS transistor N2 is turned on and the second P-channel MOS transistor P2 is turned off (the node A is at Hi level).
(The time difference from the gh level to the node B being changed to the High level.) During that time, both the second N-channel MOS transistor N2 and the second P-channel MOS transistor P2 are turned on, resulting in a reduction in speed and an increase in current consumption. Problems will arise. That is, the second N-channel MOS transistor N2 and the second P-channel M
The time of the simultaneous ON state (simultaneous selection) of the OS transistor P2 becomes longer, so that the signal propagation delay time increases,
In addition, problems such as an increase in current consumption due to the through current occur.

Therefore, the present invention has been made in view of the above problems, and its main objects are to increase the speed,
An object of the present invention is to provide a level conversion circuit that achieves low power consumption. Other objects, features, and effects of the present invention will be further clarified in the following description.

[0014]

In order to achieve the above object, the present invention provides a first differential amplifier for differentially inputting an input signal having a first power supply voltage amplitude and a signal obtained by inverting the input signal to a pair of input terminals. A second pair connected between a moving pair, a pair of output terminals of the first differential pair, and a power supply terminal to which a second power supply voltage higher in potential than the first power supply voltage is applied; A pair of input terminals of the second differential pair are cross-connected to a pair of output terminals of the first differential pair, and an output terminal of the first differential pair. A level conversion circuit configured to extract an output signal obtained by latching the input signal from the input terminal, wherein one input terminal of the first differential pair and one output terminal of the pair of the first differential pair are provided. Between the output terminal on the other input terminal side of the first differential pair and the connection point of the input terminal of the second differential pair, Serial is on-off controlled by one input end side potential, and a first switching element for pulling up the connecting point from the one of the input end of the first differential pair. As will be apparent from the following description, the above object is achieved by any of the present inventions according to claims 2 to 25 of the claims.

[0015]

Embodiments of the present invention will be described. In a preferred embodiment of the level conversion circuit according to the present invention, an inverter (INV) that inverts and outputs an input signal having a first power supply voltage amplitude from an input terminal (VIN).
And a source, both of which are connected to a reference potential and which differentially inputs the input signal from the input terminal and the output signal of the inverter to the gate to form a first differential pair of first and second transistors (N
1, N2) and first and second transistors (N1, N2).
3rd and 4th terminals which are respectively connected between the output terminal of 2) and a power supply terminal to which a second power supply voltage higher in potential than the first power supply voltage is applied, forming a second differential pair And a transistor (P1, P2), the level of which the gates of the third and fourth transistors (P1, P2) are cross-connected to the output terminals of the first and second transistors (N1, N2). In the conversion circuit, the output terminal of the inverter (INV) is connected to the second terminal.
A diode-connected transistor (N4) between a connection point between the gate of the transistor (N2) and a connection point between the output terminal of the first transistor (N1) and the gate of the fourth transistor (P2). Is inserted.

Referring to FIG. 1, a level conversion circuit according to the present invention is different from a conventional level conversion circuit (see FIG. 7) in that a connection point between an inverter (INV) and a gate of a second N-channel MOS transistor (N2) is provided. The node A is connected to the gate and the drain, and the node B is connected to the drain of the first N-channel MOS transistor (N1) and the gate of the second P-channel MOS transistor (P2).
N-channel MOS transistor (N
4). By providing this N-channel MOS transistor (N4), the input terminal (V
When the input signal from IN) changes from High level to Low level, the first N-channel MOS transistor (N1) switches from the ON state to the OFF state, and the potential of the node A which is the output terminal of the inverter (INV). Is Hi
gh level, and the second N-channel MOS transistor (N2) switches from the off state to the on state, thereby discharging the electric charge of the node C and setting the potential of the node C to Lo.
At that time, the N-channel MOS transistor (N4) is turned on to charge the node B, and the gate of the second P-channel MOS transistor (P2) accompanying the transition of the node C to the Low level. Since the problem of lowering the potential of the node B to the negative potential due to the capacitance between the drains is avoided and the node B is further pulled up from the positive potential by the first P-channel MOS transistor (P1) turned on, The time required for the transition of the node B to the High level is shortened, so that the second P-channel MOS transistor (P2) and the second N-channel MOS transistor (N2) are simultaneously turned on, so that the through current flowing The volume and power consumption are reduced.

As will be described later, the level conversion circuit according to the present invention is used in a semiconductor memory device such as an EEPROM (electrically erasable and writable read-only memory), for example, in a high voltage for erasing or writing. Used for high voltage generation. In addition to this, the first
Of course, the present invention can be applied to a circuit that receives and latches a signal driven by the power supply system and converts the level into an output signal of a second power supply system having a power supply voltage higher than the first power supply. The present invention is applicable to a driver circuit for converting a first power supply level to a second power supply level. Hereinafter, the present invention will be described in more detail with reference to various examples.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described. FIG. 1 is a diagram showing a configuration of a level conversion circuit according to a first embodiment of the present invention. Referring to FIG. 1, a level conversion circuit according to a first embodiment of the present invention comprises a first N-channel MO having a source grounded and a gate connected to input terminal VIN.
S transistor N1, an inverter INV having an input terminal connected to input terminal VIN, a second N-channel MOS transistor N2 having a source grounded and a gate connected to the output terminal of inverter INV, and a source connected to power supply terminal VPP.
, And a first P-channel M whose drain is connected to the drain of the first N-channel MOS transistor N1
An OS transistor P1, a second P-channel MOS transistor having a source connected to the power supply terminal VPP and a drain connected to the drain of a second N-channel MOS transistor N2
A transistor P2, and a first P-channel MOS
The gate of the transistor P1 is connected to a second N-channel MOS
The drain of the transistor N2 (referred to as “node C”), the gate of the second P-channel MOS transistor P2 is connected to the drain of the first N-channel MOS transistor N1 (referred to as “node B”), Further, the gate and the drain are connected to the output terminal (referred to as “node A”) of the inverter INV, and the source is connected to the first terminal.
And a fourth N-channel MOS transistor N4 connected to the drain of the N-channel MOS transistor N1.

Second N-channel MOS transistor N2
And the second P-channel MOS transistor P1
Is connected to a third P-channel MOS transistor P3 connected between the power supply terminal VPP and the ground.
Is connected to the gate of the N-channel MOS transistor N3, and the connection point between the drain of the third P-channel MOS transistor P3 and the drain of the third N-channel MOS transistor N3 is connected to the output terminal VOUT. A logic signal having a power supply amplitude of the first power supply voltage (VCC) is input to the input terminal VIN.

The operation of the first embodiment of the present invention will be described. The input signal from the input terminal VIN changes from High to L
When the level changes to the low level, the first N-channel MOS transistor N1 is turned off, and the second N-channel MOS transistor N2 whose gate receives the output of the inverter INV that inverts and outputs an input signal is turned on.

Second N-channel MOS transistor N2
Is turned on, the potential of the node C is pulled down to the Low side, and the first P-channel MOS transistor P1 that inputs the potential of the node C as a gate voltage is turned on,
Thereafter, the second P-channel MOS transistor P2 turns off.

When the node C goes low, the third P-channel MOS transistor P3 is turned on, and when the third N-channel MOS transistor is turned off, the output terminal VOUT is pulled up to a high level. Become.

Here, in the conventional circuit, the second N
A considerable time difference occurs before the channel MOS transistor N2 turns on and the second P-channel MOS transistor P2 turns off, during which time the second N-channel MOS transistor N2 and the second P-channel MOS transistor P2
2 are both turned on, causing problems such as a reduction in speed and an increase in current consumption.

In the first embodiment of the present invention, an N-channel MOS transistor N4 for pull-up is provided between the nodes A and B, and when the potential of the node A is at a high level, the fourth transistor is turned on. The node B is charged via the N-channel MOS transistor N4, and its potential is pulled up, thereby increasing the speed (rise time) of the node B changing from Low to High.

Fourth N-channel MOS transistor N4
, The node B has a fourth N-channel M
A potential lower than the High level potential applied to the gate and the drain of the OS transistor N4 by the threshold voltage V _TH is supplied to charge the node B, thereby setting the node B to the ground potential or lower as in the conventional circuit. Then, the node B is pulled up by the first P-channel MOS transistor P1, and the second P-channel MOS transistor P2 that receives the potential of the node B as a gate voltage is turned off. As a result, the speed of the level conversion circuit can be increased, and power consumption can be reduced.

FIG. 2 is a diagram showing operation timing waveforms of the first embodiment of the present invention, and is a diagram showing signal waveforms of VIN, node A, node B, node C, and VOUT in FIG. FIG. 2 is a circuit simulator SPICE corresponding to the circuit configuration of the first embodiment of the present invention shown in FIG.
FIG. 9 is a diagram showing output results obtained by simulation in the same manner as above, in which simulation is performed under the same conditions as those shown in FIG.

Here, looking at the timing waveform of the conventional circuit shown in FIG. 9 for comparison, the second N-channel MOS transistor N2 is turned on from the time when VIN transitions from High to Low, and the node C In the process of falling to the Low potential, the potential of the node B falls below the ground potential (see FIG. 9B), and thereafter, the node B is pulled up by the first P-channel MOS transistor P1. Therefore, the node B rises later than the output VOUT.

On the other hand, in the first embodiment of the present invention, referring to FIG.
Changes from High to Low level, the node A rises and the first N-channel MOS transistor N1
Is turned off, the second N-channel MOS transistor N2 is turned on, the node C goes low, and the fourth N
The channel MOS transistor N4 turns on. 4th N
When the channel MOS transistor N4 is turned on, the potential of the node B is pulled up to the High potential side, and the first
P-channel MOS transistor P1 is turned on to pull up the potential of node B, and second P-channel MOS transistor P2 is turned off.

That is, in the first embodiment of the present invention, when the input terminal VIN transitions from High to Low, the second N-channel MOS transistor N2 is turned on and the node C falls to Low potential. ,
The node B is charged via the fourth N-channel MOS transistor N4 which is turned on. Therefore, for example, in the example shown in FIG. 2, for example, 61 nano (N) seconds on the time axis (horizontal axis). At this point, the potential of the node B is set to a positive potential (see FIG. 2A). After that, since the node B is pulled up by the first P-channel MOS transistor P1, the node B is supplied from the output VOUT. Rises quickly, and the period from the transition of the node A to the high level (after exceeding the logical threshold voltage) to the transition of the node B to the high level (exceeding the logical threshold voltage) is 1.3 nanoseconds. In the example shown in FIG. 9, it is set to about 2 nanoseconds. Therefore, compared with the conventional circuit, it is reduced by more than 30%, and the second N
Channel MOS transistor N2 and second P-channel M
Useless power consumption due to a through current of the OS transistor P2 is reduced.

FIG. 1 shows a configuration in which the potential at node C is output by a buffer circuit composed of a CMOS inverter including a third N-channel MOS transistor N3 and a third P-channel MOS transistor P3. However, it goes without saying that this buffer may be constituted by an inverter in which the load and the driving transistor are constituted by N-channel MOS transistors, or by an inverter constituted by a resistive load type N-channel MOS transistor.

The level conversion circuit of the first embodiment of the present invention shown in FIG. 1 is replaced with an EEPROM (Electrically Erasable).
and / or Programmable ROM; electrically erasable and writable read-only memory) memory cells or batch erase type EEPROM memory cells
Alternatively, in the case where the input signal VIN is used for the write voltage,
Are driven by the logic amplitude voltage of the first power supply voltage VCC, and when the output VOUT of the level conversion circuit is stabilized,
The power supply terminal VPP may be controlled to be pulled up from the first power supply potential VCC to a predetermined high voltage (for example, about 10 V). As described above, the control method in which the power supply terminal VPP is temporarily raised from the first power supply potential VCC to a predetermined high voltage is effective in extending the life by reducing the withstand voltage of the element, reducing power consumption, and the like.

Alternatively, in the level conversion circuit shown in FIG. 1, a power supply potential higher than VCC may be applied to the power supply terminal VPP from the beginning.

Next, a second embodiment of the present invention will be described. FIG. 3 is a diagram showing the configuration of the second embodiment of the present invention. Referring to FIG. 3, the second embodiment of the present invention is similar to the first embodiment, except that the connection point between the output terminal of the inverter INV and the gate of the second N-channel MOS transistor N2, Between the drain (node B) of the N-channel MOS transistor N1
In addition to the transistor N4, the inverter IN
V input terminal and second N-channel MOS transistor N2
Of the fifth N-channel MO between the drain (node C)
An S transistor N5 is provided. A fourth N-channel MOS transistor N4 having a gate and a drain connected to the output terminal of the inverter INV, and a source connected to the node B;
Is similar to the first embodiment, when the input signal VIN is High.
At the time when the voltage changes from h to Low, the transistor is turned on and functions to charge and pull up the node B. On the other hand, a fifth N-channel MOS transistor having its gate and drain connected to the input terminal VIN and its source connected to the node C N5 is turned on when the input signal VIN is High, and serves to pull up the node C.

In the second embodiment of the present invention, the high voltage HV (Hi
gh Voltage) and / or its complementary signal ＶHV.

Next, a third embodiment of the present invention will be described. FIG. 4 is a diagram showing the configuration of the third embodiment of the present invention. Referring to FIG. 4, in the fourth embodiment of the present invention, a gate is connected to power supply terminal VPP between first N-channel MOS transistor N1 and first P-channel MOS transistor P1. Third N channel M
An OS transistor N3 is inserted, and a second N-channel M
A fourth N-channel MOS transistor N4 having a gate connected to the power supply terminal VPP is inserted between the OS transistor N2 and the second P-channel MOS transistor P2.
A fifth N-channel MO having a gate and a drain connected to a connection point of the gate of the S transistor N2 and a source connected to a connection point of the drain of the third N-channel MOS transistor N3 and the gate of the second P-channel MOS transistor
An S transistor N5 is provided. In the fourth embodiment of the present invention, the third N-channel MOS transistor N
3 has a high voltage (for example, 1) from the power supply terminal VPP.
0V) is applied, but a voltage of, for example, about 6 V appears as a level-shifted voltage at the source of the third N-channel MOS transistor N3 or the fourth N-channel MOS transistor N4. N-channel MO
The electric field between the drain and the source of the S transistor N1 is reduced. In this embodiment, the fourth and fifth N-channel MOS transistors N4 and N5 and the first and second N-channel MOS transistors N4 and N5 are used.
An N-channel MOS transistor may be inserted between the P-channel MOS transistors P1 and P2, or a P-channel MOS transistor may be inserted.

Further, similarly to the configuration shown in FIG. 3, a configuration may be adopted in which a sixth N-channel MOS transistor N6 having a gate and a drain connected to the input terminal of the inverter INV and a source connected to the node C is provided. Of course.

Next, a fourth embodiment of the present invention will be described. FIG. 5 shows a level conversion circuit according to a first embodiment of the present invention shown in FIG.
FIG. 9 is a diagram illustrating an example of an operation timing waveform when applied to a high voltage generation circuit of a ROM.

Referring to FIGS. 1 and 5, the input terminal VI
When N transitions from the High level of the first power supply voltage (VCC) amplitude to the Low level, the node A changes to High and the node C changes to Low, and as described above, the first N-channel MOS transistor N1 At the connection point between the drain of the transistor P2 and the gate of the second P-channel MOS transistor P2 changes to High level, and VOU
As for T, the output of the High level is determined. At this point, V
Supply boost voltage from boost circuit to PP (FIG. 5)
Thus, a boosted voltage is output from VOUT.

FIG. 6A is a diagram showing an example of the configuration of a memory cell array when the level conversion circuit according to the present invention is applied to an EEPROM decoder or the like. Referring to FIG. 6A, a control (control) gate and a floating (floating) of the EEPROM memory cell 100 are formed.
The memory cell transistor having a gate has a drain terminal (D) connected to the bit line 103, a gate terminal (G) connected to the word line 106, and a source terminal (S).
Are connected to the source line 104. EEPROM X
The decoder 102 decodes the input address signal to select and control the word line 106, and the Y decoder 101 decodes the input address signal and controls on / off of a Y switch (column switch) 108 to turn on the bit line 103. Select and control. Further, the source decoder 105 selectively controls a source line connected to the source of the memory cell 100. The read / write circuit 107 includes a sense amplifier that reads data of the bit line 103 and a write circuit that outputs a write signal to the bit line 103.

FIG. 6B is a table showing an example of a voltage applied to a terminal of a memory cell transistor when writing and erasing a memory cell. When writing to a memory cell, the first boosted voltage is applied to the gate terminal, the second boosted voltage is applied to the drain terminal, and the source terminal is grounded. On the other hand, erasing is performed by grounding the gate terminal and connecting the drain to the drain terminal. Opening is performed by supplying a third boosted voltage to the source.

The level conversion circuit described in each of the above embodiments is used for the X decoder 102, the write circuit 107, and the source decoder 105, and the word line 106, the bit line 103, and the source line 104 are obtained from the output VOUT of the level conversion circuit.
Supply the necessary boost voltage to
And erasure are performed.

Referring again to FIG. 5, a boosted voltage is supplied from the output VOUT of the level conversion circuit, and after the writing or erasing operation on the memory cell, the power supply of VPP is returned to the normal power supply (VCC) level (FIG. 5). ), And VIN
Is changed from low to high, a non-selection state is established, and a low level is output to the output VOUT of the level conversion circuit.

Next, a fifth embodiment of the present invention will be described. FIG. 7 is a diagram showing an example of a circuit configuration for switching the VPP to the boosted voltage described with reference to FIGS. 5 and 6 as a fifth embodiment of the present invention.

Referring to FIG. 7, booster circuit 11 receives a control signal (Low active signal) from input terminal VIN to generate a boosted voltage. The level conversion circuit 10
For example, it is composed of the level conversion circuit of each of the embodiments described with reference to FIG. The output terminal of the booster circuit 11 is connected to the source of a P-channel MOS transistor P12 (first switch) whose gate receives a control signal, and the output terminal of the level conversion circuit 10 has its drain connected to the power supply VCC. P-channel MOS transistor P11
(Second switch) connected to the gate of the P-channel M
The source of the OS transistor P11 and the drain of the P-channel MOS transistor P12 are connected in common, and VPP
It is output as a voltage.

This VPP voltage is also supplied as a VPP power supply voltage of the level conversion circuit 10 (see FIG. 1).

The operation of the circuit shown in FIG. 7 will be described below. When the control signal transits from the High level to the Low level, the P-channel MOS transistor P12 forming the first switch is turned on (conducting), the booster circuit 11 is activated, and the boosted voltage is output from the output terminal. A high voltage such as 10 V is output. In response to the high voltage VPP, the level conversion circuit 10 also outputs a high voltage (VPP) from an output terminal. The output voltage VPP (eg, 10 V) is used as a gate input. The source is at a high potential of 10 V, and the gate-source potential is 0 V.
V is output (see FIG. 5).

On the other hand, when the control signal from the input terminal VIN is L
When the level is changed from the low level to the high level, the P-channel MOS transistor P12 forming the first switch is turned off, and the level conversion circuit 10 outputs the Low level, so that the P-channel MOS transistor P11 forming the second switch is turned off. And the power supply voltage VCC becomes V
It is supplied as a PP voltage (see FIG. 5).

In each of the embodiments described above, the level conversion circuit mainly used for erasing and writing the high voltage of the EEPROM has been described. However, the present invention is not limited only to such a configuration. Of course, the present invention can be applied to a circuit that receives and latches a signal driven by the power supply system, and converts the level to an output signal of a second power supply system having a power supply voltage higher in potential than the first power supply system. The present invention is also applicable to a level converter or a driver circuit for converting the logical amplitude of the first power supply system into the logical amplitude of the second power supply system. Further, in the timing chart shown in FIG. 2, in the level conversion circuit for inputting an input signal having a logical amplitude of the first power supply voltage, a high voltage is applied to the power supply terminal VPP until the latch operation of the level conversion circuit is determined. Although timing waveforms are shown for the case where no voltage is applied, it is apparent from FIG. 2 that the circuit of the embodiment described with reference to FIG. It can be seen that even when used as a driven latch circuit, the operation speeds up and the current consumption is reduced.

[0049]

As described above, according to the present invention,
This has the effect of speeding up the level conversion circuit and reducing current consumption.

The reason is as follows. That is,
According to the present invention, an inverter for inverting and outputting an input signal having a first power supply voltage amplitude from an input terminal (VIN), a source having a common connection to a reference potential, and inputting the first power supply voltage amplitude from the input terminal A first and second N-type transistors each having a signal and a signal obtained by inverting the input signal by the inverter input to a gate terminal; and a drain terminal of the first and second N-type transistors. , A first and a second P-type transistor respectively connected between a power supply terminal to which a second power supply voltage higher than the first power supply voltage is applied. And a gate terminal of the second P-type transistor is cross-connected to a drain terminal of the first and second N-type transistors, the output terminal of the inverter (node A When the gate terminal and the drain terminal is connected to a connection point between the gate terminal of the second N-type transistor, the drain terminal of the first N-type transistor and the second P
The input signal from the input terminal (VIN) changes from High level to Low level by providing the third N-type transistor having the source terminal connected to the connection point (node B) with the gate terminal of the type transistor Then, the third N-type transistor is turned on to charge the node B, thereby preventing the node B from being lowered to the negative potential.
Since the node B is further pulled up from the positive potential by the first P-type transistor turned on,
The time required for the transition of the node B to the high level is shortened, so that the time from when the node A changes to the high level to when the node B changes to the high level is shortened, and the node B is connected in series between VPP and the ground. This is because power consumption due to a through current flowing through the second P-type transistor and the second N-type transistor is reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a diagram showing timing waveforms for explaining the operation of the first embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a third exemplary embodiment of the present invention.

FIG. 5 is a timing chart showing an example of control of a high-voltage power supply as a fourth embodiment of the present invention.

6A is a diagram showing an example of a configuration of an EEPROM to which the level conversion circuit of the present invention is applied, and FIG. 6B is a diagram showing an example of voltage setting for writing and erasing of a memory cell; .

FIG. 7 is a diagram showing an example of the configuration of a switching circuit for switching between VCC and VPP as a fifth embodiment of the present invention.

FIG. 8 is a diagram showing a configuration of a conventional level conversion circuit.

FIG. 9 is a diagram showing timing waveforms for explaining the operation of a conventional level conversion circuit.

[Explanation of symbols]

Reference Signs List 10 level conversion circuit 11 booster circuit 100 memory cell 101 Y decoder 102 X decoder 103 bit line 104 source line 105 source decoder 106 word line 107 read / write circuit 108 column switch (Y switch) N1 to N5 N channel MOS transistors P1 to P3 , P11, P12 P-channel MOS transistor VIN input terminal VOUT output terminal

Claims (25)

(57) [Claims] An input signal having a first power supply voltage amplitude and a signal obtained by inverting the input signal are differentially input to a pair of input terminals.
And a power supply terminal connected between a pair of output terminals of the first differential pair and a power supply terminal to which a second power supply voltage higher in potential than the first power supply voltage is applied. And a pair of input terminals of the second differential pair are cross-connected to a pair of output terminals of the first differential pair, and an output terminal of the first differential pair. A level conversion circuit obtained by extracting an output signal obtained by latching the input signal from the input terminal, wherein one of an input terminal of the first differential pair and a first output terminal of a pair of output terminals of the first differential pair. Between the output terminal on the other input terminal side of the differential pair and the connection point of the one input terminal of the second differential pair. A first switch element that is on / off controlled by a potential and pulls up the connection point from the one input terminal side of the first differential pair. Bell conversion circuit. 2. The method according to claim 1, wherein when the one input terminal of the first differential pair is at a high level of the first power supply voltage amplitude,
Switch element is turned on, and the first input terminal of the first differential pair is connected to the first differential element via the first switch element.
By charging the connection point between the output terminal on the other input terminal side of the differential pair and the one input terminal of the second differential pair,
2. The level conversion circuit according to claim 1, wherein the potential at the connection point is pulled up to a high level. 3. The other input terminal of the first differential pair and the output terminal of the first differential pair on the one input terminal side of the pair of output terminals. A second switch element, which is on / off controlled by the potential of the other input terminal of the first differential pair, between the second input terminal and a connection point of the second differential pair with another input terminal of the second differential pair. 3. The level conversion circuit according to claim 1, further comprising: 4. A power supply terminal to which one output terminal voltage of a pair of output terminals of the first differential pair is input and to which the second power supply voltage is applied is connected between a reference terminal and a reference potential. 4. The level conversion circuit according to claim 1, further comprising a buffer circuit. 5. A first driving element for inputting an input signal having an amplitude determined by a first power supply voltage to an input terminal, a second driving element for inputting a complementary signal obtained by inverting the input signal to an input terminal, An output terminal of each of the first and second driving elements;
First and second active load elements connected between a power supply terminal to which a second power supply voltage having a higher potential than the power supply voltage is applied. A control terminal of the load element is cross-connected to the output terminals of the first and second driving elements, and an output signal voltage is output from the output terminal of the first driving element and / or the output terminal of the second driving element. In the level conversion circuit taken out, between the input terminal of the second drive element and the connection point between the output terminal of the first drive element and the control terminal of the second active load element, ON at the potential of the input terminal of the second drive element
A level conversion circuit, comprising: a first switch element that is turned off and pulls up the connection point from an input end of the second drive element. 6. The first switch element is turned on when the input terminal of the second drive element is set to the high level of the first power supply voltage amplitude, and the input terminal of the second drive element is turned on. By charging a connection point between the output terminal of the first drive element and the control terminal of the second active load element via the first switch element, the potential of the connection point is set to the first potential. 6. The level conversion circuit according to claim 5, wherein the power supply voltage is pulled up to a high level side. 7. An input terminal of said first drive element and said second drive element.
Between the output terminal of the driving element and the connection point between the control terminal of the first active load element and the potential of the input terminal of the first driving element. And a second switch element for pulling up a potential at a connection point between an output terminal of the second drive element and a control terminal of the first active load element from an input terminal side of the second drive element. The level conversion circuit according to claim 5. 8. The apparatus according to claim 1, wherein said first switch element comprises a one-way switch.
The level conversion circuit according to any one of the above. 9. The level conversion circuit according to claim 3, wherein said second switch element comprises a one-way switch. 10. An inverter which inputs an input signal of a first power supply voltage amplitude input from an input terminal and inverts and outputs the input signal; an input signal of the first power supply voltage amplitude input from the input terminal; First and second transistors each functioning as a driving element by inputting an output signal from an inverter to a gate terminal; output terminals of the first and second transistors; and a first power supply voltage. And third and fourth transistors respectively connected to a power supply terminal to which a high-potential second power supply voltage is applied, and configured to load the first and second transistors. In a level conversion circuit in which gate terminals of third and fourth transistors are cross-connected to output terminals of the first and second transistors, the output terminal of the inverter and the second transistor A fifth transistor that is diode-connected is inserted between a connection point between the transistor and the gate terminal of the transistor and a connection point between the output terminal of the first transistor and the gate terminal of the fourth transistor; A level conversion circuit characterized in that: 11. A diode-connected sixth transistor is inserted between the input terminal and a connection point between the output terminal of the second transistor and the gate terminal of the third transistor. The level conversion circuit according to claim 10, wherein: 12. An inverter that inputs an input signal of a first power supply voltage amplitude input from an input terminal and inverts and outputs the input signal, an input signal of the first power supply voltage amplitude input from the input terminal, First and second transistors each of which inputs an output signal from an inverter to a gate terminal and functions as a driving element; and forms a load on the first and second transistors and is lower than the first power supply voltage. Third and fourth transistors respectively connected to a power supply terminal to which a high-potential second power supply voltage is applied; output terminals of the first and second transistors; and third and fourth transistors. And a fifth transistor and a sixth transistor, respectively, connected between the first and second transistors and having a gate terminal to which the second power supply voltage is applied, wherein the gates of the third and fourth transistors are provided. A level conversion circuit having a terminal crossed with the output terminals of the fifth and sixth transistors, wherein a connection point between the output terminal of the inverter and the gate terminal of the second transistor; A diode-connected seventh transistor is inserted between the output terminal of the third transistor and the connection point of the gate terminal of the fourth transistor. 13. A diode-connected eighth transistor is inserted between the input terminal and a connection point between the output terminal of the sixth transistor and the gate terminal of the third transistor. 13. The level conversion circuit according to claim 12, wherein: 14. The semiconductor device according to claim 10, wherein said first, second, and fifth transistors comprise N-channel MOS transistors, and said third and fourth transistors comprise P-channel MOS transistors. Level conversion circuit as described. 15. The semiconductor device according to claim 15, wherein the sixth transistor is an N-channel transistor.
12. The semiconductor device according to claim 11, comprising an OS transistor.
Level conversion circuit as described. 16. The semiconductor device according to claim 16, wherein said first, second, fifth to seventh transistors comprise N-channel MOS transistors, and said third and fourth transistors comprise P-channel MOS transistors. Item 13. The level conversion circuit according to Item 12. 17. The voltage supply to the power supply terminal is switched from the first power supply voltage to the second power supply voltage when the latch output of the level conversion circuit is determined. The level conversion circuit according to claim 1. 18. An inverter for inverting and outputting an input signal of a first power supply voltage amplitude input from an input terminal, and a source connected in common to a reference potential, and an input of the first power supply voltage amplitude from the input terminal. First and second N-type transistors each having a signal and a signal obtained by inverting the input signal by the inverter input to a gate terminal; and a drain terminal of the first and second N-type transistors. A first and a second P-type transistor respectively connected to a power supply terminal to which a second power supply voltage higher in potential than the first power supply voltage is applied; And a gate terminal of a second P-type transistor cross-connected to a drain terminal of the first and second N-type transistors, wherein the output terminal of the inverter is connected to the second N-type transistor. A gate terminal and a drain terminal are connected to a connection point with the gate terminal of the transistor, and a source terminal is connected to a connection point between the drain terminal of the first N-type transistor and the gate terminal of the second P-type transistor. A level conversion circuit comprising a third N-type transistor. 19. A gate connected in series between the power supply terminal to which the second power supply voltage is applied and a reference potential, and a connection point between the second N-type transistor and the second P-type transistor is connected to a gate. 19. A CMOS inverter comprising a third P-type transistor and a fourth N-type transistor connected to the terminal and connected to the output terminal by connecting the drain terminals to each other. Level conversion circuit. 20. A boosted voltage generating circuit for receiving a control signal and generating a boosted voltage forming a second power supply voltage when the control signal is active; and inputting an output of the boosted voltage generating circuit to an input terminal. A first switch that is controlled to be turned on and off by inputting a control signal to a control terminal; a power supply terminal to which a first power supply voltage lower than the second power supply voltage is applied; 20. A second switch connected between an output terminal and the level conversion circuit according to any one of claims 1 to 19, wherein the control signal is input as an input signal, and the output is the second signal. A level conversion circuit connected to a control terminal of a switch, wherein the first power supply voltage or the second power supply voltage is taken out from a connection point between the first switch and the second switch. And the first switch A connection point between the switch and the second switch is connected to the power supply terminal of the level conversion circuit. 21. An output of the level conversion circuit according to any one of claims 1 to 19, wherein the output is connected to at least one of a common source line, a common gate line, and a common drain line in the memory cell array of the EEPROM. A semiconductor memory device. 22. When the output of the level conversion circuit is determined, a power supply potential supplied to a power supply terminal of the level conversion circuit is switched from the first power supply voltage to the second power supply voltage which is a boosted power supply voltage. 22. The semiconductor memory device according to claim 21, further comprising means. 23. A semiconductor device comprising: first and second differential pairs connected in cascade between a high-potential-side power supply terminal and a low-potential-side power supply terminal; and a pair of input terminals of the first differential pair. Are differentially input with an input signal and a signal obtained by inverting the input signal, a pair of output terminals of the first differential pair are cross-connected to a pair of input terminals of the second differential pair, A latch circuit that outputs a signal obtained by latching the input signal from one or both of a pair of output terminals of a first differential pair, wherein one input terminal of the first differential pair and the first differential pair Between the output terminal of the pair of output terminals on the other input terminal side of the first differential pair and the connection point of one input terminal of the second differential pair. A latch circuit, comprising: a first switch element that is turned on / off by a potential on the one input terminal side of a moving pair. 24. Another input terminal of the first differential pair, and an output terminal on one input terminal side of the first differential pair among a pair of output terminals of the first differential pair. A second switch element that is on / off controlled by the potential of the other input terminal of the first differential pair between the second switch element and a connection point with another input terminal of the second differential pair. 24. The level conversion circuit according to claim 23, further comprising: 25. A level conversion circuit using the latch circuit according to claim 23, wherein the output signal obtained by latching the input signal is supplied to the high voltage side power supply terminal after the output signal is determined. The second potential higher than the power supply voltage of the first
Wherein the power supply voltage is supplied to the high potential side power supply terminal.