KR100719679B1 - Level shifter - Google Patents

Abstract

The level shifter according to an embodiment of the present invention is composed of an initial charging part and n level shifter parts respectively connected to the initial charging part, and the level shifter part is output from the initial charging part. A first transistor T1 to which a signal is applied to a gate; A capacitor C connected between the first node N1 and the input voltage IN terminal; A second transistor T2 connected to a gate of the first node N1 and connected between a second power supply VDDH and an output voltage OUT terminal; A gate is connected to the first node N1, and a third transistor T3 connected between the inverted input voltage INb and the output voltage OUT terminal is included.

Description

Level shifter

1A and 1B are circuit diagrams showing a conventional level shifter structure.

2A and 2B are circuit diagrams of a level shifter according to an embodiment of the present invention.

3A and 3B are views for explaining the operation of the level shifter circuit shown in Fig. 2A.

4A and 4B are views for explaining the operation of the level shifter circuit shown in Fig. 2B.

5A and 5B are circuit diagrams of a level shifter according to another embodiment of the present invention.

The present invention relates to a level shifter, and more particularly, to a level shifter that overcomes power consumption and propagation delay problems.

1A and 1B are circuit diagrams showing a conventional level shifter structure.

1A is a circuit diagram for a level up shifter, and FIG. 1B is a circuit diagram for a level down shifter.

Here, VDDH shown in FIG. 1A is a supply voltage of a level up shifter, VDDL and VSS shown in FIG. 1B are supply voltages of a level down shifter, IN is an input voltage of a level up / down shifter, and OUT is an output voltage. Indicates.

Hereinafter, the structure and operation of the level up shifter will be described with reference to FIG. 1A.

Referring to FIG. 1A, a conventional level up shifter includes first and second N-channel transistors NM1 and NM2 that receive an input voltage IN and an inverted input voltage INb; The latch circuit is configured to level up the input voltage, and the latch circuit includes first and second P-channel transistors PM1 and PM2.

The NM1 and NM2 gates are connected to the input voltage IN and the inverted input voltage INb, the source is connected to the ground voltage GND, and the drains of the first and second nodes A and B are respectively. Is connected to the latch circuit. However, the second node B is connected to the output voltage OUT.

Gates and drains of the PM1 and the PM2 constituting the latch circuit are alternately connected between the first and second nodes, respectively, and the source is connected to VDDH which is a supply voltage of the level up shifter.

In the conventional level up shifter having the above structure, for example, if the input voltage IN is in the range of 0V to 5V and the output voltage OUT is in the range of 0V to 10V, INb is low level when IN is high, that is, 5V. That is, when 0V and IN are at the low level (0V), INb is at the high level (5V).

When IN is 5V, NM1 to which IN is applied is turned on and NM2 to which INb is applied is turned off. Accordingly, PM2 is turned on through the turned-on NM1 and the output voltage OUT is boosted up to the level of 10V by the supply voltage VDDH.

On the other hand, when IN is 0V, NM2 to which INb is applied is turned on and NM1 to which IN is applied is turned off, so that the output voltage OUT becomes 0V.

The level down shifter shown in FIG. 1B also operates on the same principle as the level up shifter described above.

Referring to the operation of the conventional level up shifter in more detail as follows.

First, when the input voltage IN transitions from the low level (0V) to the high level (5V), the NM1 is turned on and the NM2 is turned off. As the NM1 is turned on, the first node A is turned low and the PM2 is turned on. Therefore, the second node B is at a high level, and the PM1 is turned off.

Accordingly, the voltage level of the second node B is equal to the boosted voltage through the PM2, that is, VDDH, and this voltage 10V is provided as an output voltage OUT.

On the other hand, when the input voltage IN transitions from the high level (5V) to the low level (0V), the NM1 is turned off, the NM2 is turned on. As the NM2 is turned on, the second node B is turned low and the PM1 is turned on. Thus, the first node A is at a high level and the PM2 is turned off.

Accordingly, the voltage level of the second node B becomes low level (0V) by turning on the NM2, and this voltage (0V) is provided as an output voltage OUT.

However, in the conventional level shifter structure, since the PM2 is turned on at the time when the input voltage IN transitions from the high level to the low level, the NM2 transitions from the turned off state to the turned on state, Both the PM2 and the NM2 are turned on during the interval, so that a current path is formed between the PM2 and the NM2.

On the contrary, at the time when the input voltage IN transitions from the low level to the high level, both the PM1 and the NM1 remain turned on to form a current path between the PM1 and NM1, and a short circuit current generated at this time Is a disadvantage of increasing the power consumption of the circuit.

In addition, the conventional level shifter structure requires two phases when the output voltage is generated when the input voltage transitions from the low level to the high level, but outputs when the input voltage transitions from the high level to the low level. One phase is needed when the voltage is generated. That is, there is a problem in that the rising propagation delay and the falling propagation delay are different from each other in the output waveform due to different operation steps when generating the output voltage.

In addition, in the conventional level shifter structure, the circuit operates only when the transistors NM1 and NM2 to which the input voltage is applied are larger than the cross-coupled transistors PM1 and PM2. The disadvantage is that the width of NM2 must be quite large.

In this way, when the W (Width) / L (Length) of the transistors NM1 and NM2 to which the input voltage is applied, that is, the size, is increased, the capacitance value viewed by the input signal is increased so that the input voltage is low level (0V). The slope that transitions from to high level (5V) or from high level (5V) to low level (0V) becomes smaller. That is, the short-circuit current described above is generated because the PM1 and PM2 and the corresponding NM1 and NM2 are both turned on until the opposing cross-coupled transistors PM1 and PM2 that are structurally symmetrical turn on. As a result, the short circuit current mentioned above is further increased and thus the power consumption is very large.

The present invention is composed of an initial charging part (initial charging part) and n level shifter parts (level shifter parts) connected to the initial charging part, respectively, wherein the initial charging part initializes the charging of the capacitors provided in each level shifter part, Each of the level shifters reduces the short circuit current by a voltage boosting operation using a capacitor coupling effect to implement a low power consumption circuit, and a rising propagation delay and a falling propagation delay of the output waveform. Its purpose is to provide a level shifter configured to maintain a uniform propagation delay.

In order to achieve the above object, the level shifter according to an embodiment of the present invention includes an initial charging part and an n level shifter part respectively connected to the initial charging part, and the level shifter part includes: A first transistor T1 to which a signal output from the initial charging unit is applied to a gate; A capacitor C connected between the first node N1 and the input voltage IN terminal; A second transistor (T2) having a gate connected to the first node (N1) and connected between a second power supply (VDDH) and an output voltage (OUT) terminal; A gate is connected to the first node N1, and a third transistor T3 connected between the inverted input voltage INb and the output voltage OUT terminal is included.

Here, the source of the first transistor T1 is connected to the first power source VDDL, the drain is connected to the first node N1, and the first power source VDDL is less than the second power source VDDH. It is characterized by a low positive voltage.

In addition, the second transistor T2 and the third transistor T3 are implemented in different types to operate as a pull up transistor and a pull down transistor, and the second transistor T2 It is a P-channel transistor, the third transistor (T3) is characterized in that the N-channel transistor.

In addition, the source of the second transistor T2 is connected to the second power supply VDDH, the drain is connected to the output voltage out 1 to out n terminals, and the source of the third transistor T3 is inverted. Connected to the input voltage INb terminal, and the drain is connected to the output voltage out 1 to out n terminals.

The initial charging unit may include a booster circuit unit configured to receive an initialization signal and an inverted reset signal resetb and boost the voltage to a predetermined voltage, and output a buffer to stabilize the output voltage of the booster circuit unit. The circuit unit may include first and second N-channel transistors NM1 and NM2 that receive an initialization signal and an inverted initialization signal resetb; The latch circuit is configured to level up the input voltage, and the latch circuit includes first and second P-channel transistors PM1 and PM2.

The level shifter according to another embodiment of the present invention may include an initial charging part and n level shifter parts respectively connected to the initial charging part, and the level shifter part may include the initial charging part. A first transistor (T1) to which a signal output from is applied to a gate; A capacitor C connected between the first node N1 and the inverted input voltage INb terminal; A second transistor T2 connected to a gate of the first node N1 and connected between a second power supply VDDH and an output voltage OUT terminal; A gate is connected to the first node N1, and a third transistor T3 connected between an input voltage IN and an output voltage OUT terminal is included.

Here, the source of the first transistor T1 is connected to the second power source VDDH, and the drain thereof is connected to the first node N1.

In addition, the level shifter according to another embodiment of the present invention, a step-down circuit unit for receiving the reset signal (reset) and the inverted reset signal (resetb) to step down and output a predetermined voltage, and output voltage of the step-down circuit unit It consists of an initial charging part (initial charging part) comprising a buffer for stabilizing and n level shifter parts (level shifter part) connected to each of the initial charging unit,

Each of the level shifters may include a first transistor T1 having a signal output from the initial charging unit applied to a gate, and disposed between a first node N1 and a ground voltage GND or a third power supply VSS; A capacitor C connected between the first node N1 and an input voltage IN or an inverted input voltage INb terminal; A second transistor T2 connected to a gate of the first node N1 and connected between a third power supply VSS and an output voltage OUT terminal; A gate is connected to the first node N1 and a third transistor T3 connected between an inverted input voltage INb or an input voltage IN terminal and an output voltage OUT terminal is included. It is done.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A and 2B are circuit diagrams of a level shifter according to an embodiment of the present invention.

However, the first power source VDDL and the second power source VDDH shown in FIGS. 2A and 2B are supply voltages of the level shifter, and IN and INb are input voltages and inverted input voltages of the level shifter, out 1 to out. n represents the output voltage.

In this case, the second power source VDDH is a positive voltage higher than that of the first power source VDDL, and preferably has a value twice as high as that of the first power source VDDL.

According to an exemplary embodiment of the present invention, the second power source VDDH is applied with 10V and the first power source VDDL is applied with 5V.

Hereinafter, the structure and operation of the level shifter according to an embodiment of the present invention will be described with reference to FIG. 2.

First, the level shifter according to the embodiment of the present invention illustrated in FIG. 2A includes an initial charging part 200 and n level shifter parts 300 connected to the initial charging part 200, respectively. It consists of.

That is, n level shifter units 300 are provided to provide level-shifted voltages for the input voltages for each channel, and initial charging of capacitors C respectively provided in the n level shifter units 300 is performed. One initial charging unit 200 is characterized in that for connecting to each level shifter (300).

Through this, the initial charging unit 200 initializes the charging of the capacitors provided in each level shifter unit, and each level shifter unit 300 boosts the voltage using a capacitor coupling effect in the level shifting of the input voltage. By reducing the short circuit current, the IC achieves a low power consumption circuit and maintains the rising propagation delay and falling propagation delay of the output waveform uniformly.

First, the initial charging unit 200 receives an initialization signal reset and an inverted initialization signal resetb, a boosting circuit unit 210 for boosting and outputting a predetermined voltage, and a buffer unit for stabilizing an output voltage of the boosting circuit unit. It consists of 220.

The booster circuit unit 210 may have the same structure as that of the conventional level shifter shown in FIG. 1. Accordingly, the booster circuit unit illustrated in FIG. 2 may reset the reset signal and the inverted reset signal resetb. First and second N-channel transistors NM1 and NM2 provided; The latch circuit is configured to level up the input voltage, and the latch circuit includes first and second P-channel transistors PM1 and PM2.

The NM1 and NM2 gates are respectively connected to an initialization signal reset and an inverted initialization signal resetb, a source is connected to a ground voltage GND, and a drain is respectively connected to the first and second nodes A and B. Is connected to the latch circuit. However, the second node B is connected to the output voltage OUT.

Gates and drains of the PM1 and PM2 constituting the latch circuit are intersected and connected between the first and second nodes, respectively, and the source is connected to VDDH which is a supply voltage of the boost circuit part.

In the case of the booster circuit having the above structure, for example, if the initialization signal has a range of 0V to 5V and the output voltage OUT has a range of 0V to 10V, the initialization signal resetb is inverted when the initialization signal is at a high level, that is, 5V. ) Becomes low level, that is, 0V, and the inverted initialization signal resetb becomes high level (5V) when the initialization signal reset is low level (0V).

When the reset is 5V, NM1 to which reset is applied is turned on and NM2 to which resetb is applied is turned off. Accordingly, PM2 is turned on through the turned-on NM1 and the output voltage OUT is boosted up by the supply voltage VDDH to be 10V.

On the other hand, when reset is 0V, NM2 to which resetb is applied is turned on, and NM1 to which reset is applied is turned off so that the output voltage OUT becomes 0V.

As such, the output voltages of the booster circuit unit are transferred to the n level shifter units through the buffer unit 220. In this case, as shown in FIG. 2A, the buffer unit may have a structure in which two inverters are connected in series.

The level shifter 300 may include a first transistor T1 to which a signal output from the initial charging unit is applied as a gate; A capacitor C connected between the first node N1 and the input voltage IN terminal; A second transistor T2 connected to a gate of the first node N1 and connected between a second power supply VDDH and an output voltage OUT terminal; A gate is connected to the first node N1, and a third transistor T3 is connected between the inverted input voltage INb and the output voltage OUT terminal.

Here, the source of the first transistor T1 is connected to the first power source VDDL and the drain is connected to the first node N1.

On the other hand, the level shifter according to the embodiment of the present invention illustrated in FIG. 2B includes an initial charging part 400 and n level shifter parts 500 connected to the initial charging part 400, respectively. N level shifter units 500 are provided to provide level shifted voltages for the input voltages for each channel, and the capacitors C provided in the n level shifter units 500, respectively. One initial charging unit 400 is connected to each level shifter 500 for the initial charging of the configuration and operation of the initial charging unit 400 is the same as the embodiment shown in FIG.

However, unlike the embodiment illustrated in FIG. 2A, the level shifter 500 includes a first transistor T1 to which a signal output from the initial charging unit 400 is applied to a gate; A capacitor C connected between the first node N1 and the inverted input voltage INb terminal; A second transistor T2 connected to a gate of the first node N1 and connected between a second power supply VDDH and an output voltage OUT terminal; A gate is connected to the first node N1, and a third transistor T3 connected between an input voltage IN and an output voltage OUT terminal is included.

That is, compared with the embodiment illustrated in FIG. 2A, the first power source VDDL as the supply voltage is removed, and the input voltage IN and the inverted input voltage INb are inputted oppositely.

Accordingly, the source of the first transistor T1 is connected to the first power source VDDL in the case of the embodiment of FIG. 2A, the second power source VDDH in the case of the embodiment of FIG. 2B, and the drain is the first source. It is connected to node N1.

In addition, although the gates of the second transistor T2 and the third transistor T3 are each connected to the first node N1, the second transistor T2 and the third transistor T3 are configured to be different types and are not simultaneously turned on.

That is, the second transistor T2 operates as a pull up transistor, and the third transistor T3 operates as a pull down transistor.

2A and 2B, the second transistor T2 is a P-channel transistor, and the third transistor T3 is composed of an N-channel transistor.

That is, the level shifter unit according to the embodiment of the present invention, which initializes and charges one capacitor, initially, prevents reverse current that may occur due to a capacitor coupling effect. A first transistor, a second transistor T2 as a pull-up transistor and a third transistor T3 as a pull-down transistor for receiving a voltage boosted by the capacitor coupling as an input signal through a gate. .

In this case, the source of the second transistor T2 is connected to the second power supply VDDH which is a supply power supply, and the drain is connected to the output voltage out 1 to out n terminals, and the source of the third transistor T3 is connected. Is connected to the inverted input voltage (INb) terminal and the drain is connected to the output voltage (out 1 ~ out n) terminal.

In addition, the second power supply (VDDH) is higher than the first power supply (VDDL) used to charge the capacitor (C), preferably characterized in that the voltage is twice as high as the first power supply (VDDL). .

3A to 3C are diagrams for describing an operation of the level shifter circuit shown in FIG. 2A.

Referring to Figures 3a to 3c, the operation of the level shifter circuit according to an embodiment of the present invention shown in Figure 2a is as follows.

However, in the description of the operation, the input voltage IN is 0V to 5V, the output voltage OUT is 0V to 10V, the first power supply VDDL is 5V, the second power supply VDDH is 10V, and the initialization signal ( A case where reset) is 0V to 5V will be described as an example.

First, referring to FIG. 3A, when the input signal IN is applied at an initial low level, that is, 0V, an initialization signal reset of the booster circuit unit provided in the initial charging unit is also provided at a low level (0V).

Accordingly, the initial charging unit outputs a low level, that is, 0V and is provided to the gate of the first transistor T1 provided in the level shifter unit through a buffer unit, and the first transistor T1 is a P-channel transistor, so As a result, the first transistor T1 is turned on.

Accordingly, 5V is applied to the first node N1, and a voltage of 5V is initially charged to the capacitor C.

On the other hand, since the inverted input voltage INb is applied at a high level, that is, 5V, the voltage difference between the gate and the source of the third transistor T3 as a pull-down transistor becomes 0V. Accordingly, the third transistor T3 is On the contrary, the second transistor T2 as the pull-up transistor is turned on, and the output voltage out 1 to out n is supplied by the second power supply VDDH input to the source of the second transistor T2. 10V.

In addition, after 5V is applied to the first node N1 and 5V is charged to the capacitor C, as shown in FIG. 3B, an initialization signal of the booster circuit unit provided in the initial charging unit is reset. Is converted to a high level (5V), and thus the initial charging unit outputs a high level, that is, 10V such as VDDH, and is provided to the gate of the first transistor T1 provided in the level shifter. The first transistor T1 is turned off.

As the first transistor T1 is turned off, the first node is in a floating state, and the capacitor C is maintained with 5 V initially charged, and the output voltages out 1 to out n are also ahead. 10V is maintained as in FIG. 3A.

That is, according to the present invention, the capacitor may be charged with the difference between the first power source VDDL and the input voltage without being affected by the threshold voltage of the first transistor T1.

Here, when the input signal IN is initially input at the low level, as shown in FIGS. 3A and 3B, the initialization signal reset is high at the low level (0V) in the boosting circuit unit provided in the initialization charging unit. The first transistor T1 is turned off and the first node is floated, thereby maintaining the 5 V initially charged in the capacitor C.

In addition, referring to FIG. 3C, when the input signal IN is shifted from the low level (0V) to the high level (5V) and inputted, the first node (N1) may be affected by a capacitor coupling effect. The voltage is boosted to IN + VDDL, or 10V.

At this time, since the first transistor T1 is maintained in a turn-off state, a reverse current, which may be caused by a capacitor coupling effect, is suppressed, thereby reducing the voltage of the first node N1. 10V can be maintained.

On the other hand, the inverted input voltage INb is at the low level (0V) so that the voltage difference between the gate and the source of the third transistor T3 as the pull-down transistor is 10V. Accordingly, the third transistor T3 is turned on. On the contrary, the second transistor T2 as the pull-up transistor is turned off so that the output voltages out 1 to out n become 0V.

In addition, when the output voltage (out 1 ~ out n) is 0V, when the input signal IN transitions from the high level (5V) to the low level (0V), the first node by the capacitor coupling effect (capacitor coupling) effect N1 becomes 5V, and the inverted input voltage INb also becomes 5V such that reverse current flows toward the output voltage out 1 to out n terminal through the third transistor T3, which is a pull-down transistor. As shown in FIG. 3A, the output voltages (out 1 to out n) are rapidly charged to 10V.

That is, in the case of the level shifter part having the above structure, the driving capability due to the voltage difference between the gate and the source of the second transistor T2, which is a pull-up transistor, and the third transistor T3, which is a pull-down transistor, is caused by voltage boosting. It alleviates the difference.

In addition, after the input voltage IN is structurally transitioned, only one of the second transistor T2, which is a pull-up transistor, and the third transistor T3, which is a pull-down transistor, is turned on, so the short circuit current is very small and the output voltage ( out 1 ~ out n) terminal goes from 0V to 0V or from 0V to 10V, the same phase (step), so that the rising propagation delay (falling propagation delay) and falling propagation delay (falling propagation delay) can be equally matched.

Next, FIGS. 4A to 4C are diagrams for describing an operation of the level shifter circuit shown in FIG. 2B.

4A to 4C, the operation of the level shifter circuit according to the embodiment of the present invention shown in FIG. 2B will be described.

However, in the description of the operation, the input voltage IN is 0V to 5V, the output voltage OUT is 0V to 10V, the second power supply VDDH is 10V, and the reset signal is 0V to 5V. This will be described as an example.

Compared with the embodiment illustrated in FIG. 2A, the first power source VDDL is not provided. Accordingly, the size of the second power source VDDH may be more freely provided.

First, referring to FIG. 4A, when the input signal IN is applied at the first low level, that is, 0V, and thus the inverted input signal is applied at the first high level, that is, 5V, the booster circuit unit provided in the initial charging unit is provided. The initialization signal of is also provided at the low level (0V).

Accordingly, the initial charging unit outputs a low level, that is, 0V, and is provided to the gate of the first transistor T1 provided in the level shifter unit. The first transistor T1 is a P-channel transistor, so the first transistor 1 transistor T1 is turned on.

Accordingly, the first node N1 becomes VDDH, that is, 10V by the first transistor T1, and the capacitor C is provided between the first node and the inverted input voltage INb. Both ends of the capacitor C are charged VDDH-5V, that is, 5V.

On the other hand, since the input voltage IN is applied at a low level, that is, 0V, the voltage difference between the gate and the source of the third transistor T3 as a pull-down transistor is 10V, and accordingly, the third transistor T3 is turned on. On the contrary, the second transistor T2 as the pull-up transistor is turned off so that the output voltages out 1 to out n become 0V.

In addition, after 5V is applied to the first node N1 and 5V is charged to the capacitor C, as shown in FIG. 4B, an initialization signal of the booster circuit unit provided in the initial charging unit is reset. Is converted to a high level (5V), and thus the initial charging unit outputs a high level, that is, 10V such as VDDH, and is provided to the gate of the first transistor T1 provided in the level shifter. The first transistor T1 is turned off.

As the first transistor T1 is turned off, the first node is in a floating state, and the capacitor C maintains an initial charged 5V, and also output voltages (out 1 to out n). 0V is maintained as in FIG. 3A.

That is, according to the present invention, the capacitor may be charged with the difference between the first power source VDDL and the input voltage without being affected by the threshold voltage of the first transistor T1.

Here, when the input signal IN is initially input at the low level, as shown in FIGS. 3A and 3B, the initialization signal reset is high at the low level (0V) in the boosting circuit unit provided in the initialization charging unit. The first transistor T1 is turned off and the first node is floated, thereby maintaining the 5 V initially charged in the capacitor C.

5C, the input signal IN transitions from the low level (0V) to the high level (5V), that is, the inverted input signal INb transitions from the high level (5V) to the low level (0V). When inputted, the voltage of the first node N1 is converted to VDDH-5V, that is, 5V, in order to maintain the voltage value stored in the capacitor C according to the capacitor coupling effect.

At this time, since the first transistor T1 is maintained in a turn-off state, a reverse current, which may be caused by a capacitor coupling effect, is suppressed, thereby reducing the voltage of the first node N1. 5V can be maintained.

On the other hand, the input voltage IN becomes the high level 5V, and the voltage difference between the gate and the source of the third transistor T3 as the pull-down transistor becomes 0V. Accordingly, the third transistor T3 is turned off, and on the contrary, the second transistor T2 as the pull-up transistor is turned on so that the output voltage out 1 to out n is the source of the second transistor T2. The 10V is set by the second power supply VDDH input to.

That is, in the case of the level shifter part having the above structure, the driving capability due to the voltage difference between the gate and the source of the second transistor T2, which is a pull-up transistor, and the third transistor T3, which is a pull-down transistor, is caused by voltage boosting. It alleviates the difference.

In addition, after the input voltage IN is structurally transitioned, only one of the second transistor T2, which is a pull-up transistor, and the third transistor T3, which is a pull-down transistor, is turned on, so the short circuit current is very small and the output voltage ( out 1 ~ out n) terminal goes from 0V to 0V or from 0V to 10V, the same phase (step), so that the rising propagation delay (falling propagation delay) and falling propagation delay (falling propagation delay) can be equally matched.

5A and 5B are circuit diagrams of a level shifter according to another embodiment of the present invention.

However, this is a circuit diagram for a level down shifter, and in comparison with the level up shifter shown in FIG. 2, the difference is that the third power supply VSS as the supply voltage is a negative voltage level in its configuration. have.

At this time, the third power source VSS is a supply voltage of the level down shifter, IN and INb are input voltages and inverted input voltages of the level down shifter, and OUT is an output voltage.

5A and 5B, a level down shifter according to an embodiment of the present invention includes an initial charging part 600 and n level shifter parts connected to the initial charging part 600, respectively. (700).

First, the initial charging unit 600 receives an initialization signal (reset) and an inverted initialization signal (resetb) to step down to a predetermined voltage (level down) and outputs the step-down circuit unit 610, and the step-down circuit unit 610 The buffer unit 620 stabilizes the output voltage.

The step-down circuit unit 610 may include first and second P-channel transistors pm1 and pm2 that receive an initialization signal and an inverted initialization signal resetb; The latch circuit is configured to level down the input voltage, and the latch circuit includes first and second N-channel transistors nm1 and nm2.

The pm1 and pm2 have their gates connected to the reset signal and the inverted reset signal resetb, the source is connected to the first voltage VDDH, and the drains are respectively the first and second nodes A and B. Is connected to the latch circuit. However, the second node B is connected to the output voltage OUT.

Gates and drains of nm1 and nm2 constituting the latch circuit are alternately connected between the first and second nodes, and a source is connected to a third power supply VSS, which is a supply voltage of the step-down circuit portion.

In the case of the step-down circuit section having the above structure, for example, the input voltage IN is output in a range of 0V to 5V and the output voltage OUT is in a range of -5V to 5V.

As such, the output voltage of the step-down circuit unit is transmitted to the n level shifter units through the buffer unit 620, respectively. In this case, as shown in FIG. 5, the buffer unit may have a structure in which two inverters are connected in series.

In addition, the level shifter 700 receives a signal output from the initial charging unit as a gate, respectively, and includes a first transistor provided between the first node N1 and the ground voltage GND or the third power supply VSS. (T1); A capacitor C connected between the first node N1 and an input voltage IN or an inverted input voltage INb terminal; A second transistor T2 connected to a gate of the first node N1 and connected between a third power supply VSS and an output voltage OUT terminal; A gate is connected to the first node N1 and includes a third transistor T3 connected between an inverted input voltage INb or an input voltage IN terminal and an output voltage OUT terminal.

That is, in the embodiment illustrated in FIG. 5A, the level shifter 700 is provided with a signal output from the initial charging unit as a gate, and is provided between the first node N1 and the ground voltage GND. One transistor T1; A capacitor C connected between the first node N1 and the input voltage IN terminal; A second transistor T2 connected to a gate of the first node N1 and connected between a third power supply VSS and an output voltage OUT terminal; A gate is connected to the first node N1 and includes a third transistor T3 connected between an inverted input voltage INb terminal and an output voltage OUT terminal.

In the exemplary embodiment illustrated in FIG. 5B, the level shifter 700 receives a signal output from the initial charging unit as a gate, and includes a first transistor provided between the first node N1 and the third power source VSS. (T1); A capacitor C connected between the first node N1 and the inverted input voltage INb terminal; A second transistor T2 connected to a gate of the first node N1 and connected between a third power supply VSS and an output voltage OUT terminal; A gate is connected to the first node N1, and a third transistor T3 connected between an input voltage IN terminal and an output voltage OUT terminal is included.

Since the operation of the level down shifter having such a configuration operates on the same principle as the operation of the level up shifter described above with reference to FIGS. 2 to 4, the detailed description thereof will be omitted.

According to the present invention, a voltage boosting operation using a capacitor coupling effect greatly reduces the short circuit current to implement a low power consumption circuit, and a rising propagation delay and a falling propagation delay of an output waveform. Falling propagation delay) can be kept uniform.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (18)

An initial charging part including a boosting circuit part for receiving an initializing signal reset and an inverted initializing signal resetb and boosting the voltage to a predetermined voltage, and a buffer part for stabilizing an output voltage of the boosting circuit part; N level shifter parts connected to the initial charging unit, respectively, The level shifter unit may include a first transistor T1 to which a signal output from the initial charging unit is applied to a gate; A capacitor C connected between the first node N1 and the input voltage IN terminal; A second transistor T2 connected to a gate of the first node N1 and connected between a second power supply VDDH and an output voltage OUT terminal; And a third transistor (T3) connected to a gate of the first node (N1) and connected between an inverted input voltage (INb) and an output voltage (OUT) terminal. The method of claim 1, A level shifter, wherein a source of the first transistor (T1) is connected to a first power source (VDDL) and a drain is connected to a first node (N1). The method of claim 2, The first power supply (VDDL) is a level shifter, characterized in that the voltage is less than the second power supply (VDDH). The method of claim 1, And the second transistor (T2) and the third transistor (T3) are implemented in different types to operate as pull up transistors and pull down transistors. The method of claim 4, wherein And the second transistor (T2) is a P-channel transistor, and the third transistor (T3) is an N-channel transistor. The method of claim 1, And a source of the second transistor (T2) is connected to the second power source (VDDH) and a drain is connected to an output voltage (out 1 to out n) terminal. The method of claim 1, The source of the third transistor (T3) is connected to the inverted input voltage (INb) terminal, the drain is connected to the output voltage (out 1 ~ out n) terminal level shifter. delete The method of claim 1, The booster circuit unit may include first and second N-channel transistors NM1 and NM2 for receiving an initialization signal and an inverted initialization signal resetb; And a latch circuit for leveling up the input voltage, wherein the latch circuit comprises first and second P-channel transistors (PM1, PM2). An initial charging part including a boosting circuit part for receiving an initializing signal reset and an inverted initializing signal resetb and boosting the voltage to a predetermined voltage, and a buffer part for stabilizing an output voltage of the boosting circuit part; N level shifter parts connected to the initial charging unit, respectively, The level shifter unit may include a first transistor T1 to which a signal output from the initial charging unit is applied to a gate; A capacitor C connected between the first node N1 and the inverted input voltage INb terminal; A second transistor T2 connected to a gate of the first node N1 and connected between a second power supply VDDH and an output voltage OUT terminal; And a third transistor (T3) connected to a gate of the first node (N1) and connected between an input voltage (IN) and an output voltage (OUT) terminal. The method of claim 10, A level shifter, wherein a source of the first transistor (T1) is connected to the second power source (VDDH) and a drain is connected to a first node (N1). The method of claim 10, The second transistor (T2) and the third transistor (T3) is implemented in different types, the level shifter, characterized in that it operates as a pull up transistor and a pull down transistor. The method of claim 12, And the second transistor (T2) is a P-channel transistor, and the third transistor (T3) is an N-channel transistor. The method of claim 10, And a source of the second transistor (T2) is connected to the second power source (VDDH) and a drain is connected to an output voltage (out 1 to out n) terminal. The method of claim 10, The source of the third transistor (T3) is a level shifter, characterized in that connected to the input voltage (IN) terminal, the drain is connected to the output voltage (out 1 ~ out n) terminal. delete The method of claim 10, The booster circuit unit may include first and second N-channel transistors NM1 and NM2 for receiving an initialization signal and an inverted initialization signal resetb; And a latch circuit for leveling up the input voltage, wherein the latch circuit comprises first and second P-channel transistors (PM1, PM2). An initial charging part including a voltage reduction circuit unit for receiving an initialization signal reset and an inverted initialization signal resetb and stepping down the voltage to a predetermined voltage and outputting a buffer; And n level shifter parts connected to the initial charging unit, respectively. Each of the level shifters may include a first transistor T1 having a signal output from the initial charging unit applied to a gate, and disposed between a first node N1 and a ground voltage GND or a third power supply VSS; A capacitor C connected between the first node N1 and an input voltage IN or an inverted input voltage INb terminal; A second transistor T2 connected to a gate of the first node N1 and connected between a third power supply VSS and an output voltage OUT terminal; A gate is connected to the first node N1, and a third transistor T3 connected between an inverted input voltage INb or an input voltage IN terminal and an output voltage OUT terminal is included. Level shifter.

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