KR101752003B1 - Liquid crystal display - Google Patents

Abstract

The present invention relates to a liquid crystal display, and more particularly, to a liquid crystal display (LCD) device, in which a gate pulse is applied to remaining gate lines except for 3k (k is a positive integer) And supplies gate pulses to the remaining gate lines except for the (3k + 2) -th gate lines during the (N + 1) -th frame period, And a gate driving circuit for supplying a gate pulse to the gate driving circuit.

Description

[0001] LIQUID CRYSTAL DISPLAY [0002]

The present invention relates to a liquid crystal display device.

A liquid crystal display device of an active matrix driving type displays a moving picture by using a thin film transistor (hereinafter referred to as "TFT") as a switching element. This liquid crystal display device can be downsized as compared with a cathode ray tube (CRT), and is applied to a display device in a portable information device, an office machine, a computer, etc., and is also applied to a television, thereby quickly replacing a cathode ray tube.

The liquid crystal display device has been greatly improved in manufacturing cost and image quality due to the development of its driving method and manufacturing process. In recent years, the pixel arrangement of the liquid crystal display device is applied to the pixel arrangement as shown in Fig. 1, so that the number of source drive ICs (Integrated Circuits) is reduced to 1/3, and the TRD (Triple rate driving) Technology has been proposed.

1, one pixel of a TRD liquid crystal display device includes a red subpixel R, a green subpixel G, and a blue subpixel G arranged in parallel in the column direction (y-axis direction) . The red subpixels R of the pixels are arranged side by side along the line direction (x-axis direction) in 3i (i is a positive integer) +1 line (LINE # 1, LINE # 4). The green subpixels G of the pixels are arranged along the line direction in the (3i + 2) th line (LINE # 2, LINE # 5). The blue subpixels B of the pixels are arranged along the line direction in the (3i + 3) th line (LINE # 3, LINE # 6).

In the conventional TRD liquid crystal display device as shown in FIG. 1, the subpixel line direction length is longer than the column direction length. Therefore, the subpixel has a long structure in the line direction. Due to the sub-pixel structure long in the line direction, there is a problem that the legibility of the text is lowered when a small text is displayed on an existing TRD liquid crystal display device.

FIG. 2 shows experimental results showing "A" and "Sub-pixel" by applying a clear type to the TRD liquid crystal display device as shown in FIG. Clear type is a Microsoft Windows font rendering technique that improves the appearance of strings in a specific way on a computer display screen.

As can be seen from FIG. 2, the conventional TRD liquid crystal display device has a clear pixel type structure, which is poor in readability in the clear type and has subpixels long in the column direction, Type character readability is reduced by 30% or more. As a result, the conventional TRD liquid crystal display device is not applied as a commercial product due to low character readability. Further, the power consumption of the conventional TRD liquid crystal display device is relatively high.

The present invention provides a liquid crystal display device capable of reducing the number of source drive ICs required for driving a data line of a liquid crystal display panel, improving readability of characters, and lowering power consumption.

The liquid crystal display device of the present invention includes data lines formed along a column direction, gate lines formed along a line direction orthogonal to the column direction, and data lines arranged in a matrix form defined by the data lines and the gate lines A liquid crystal display panel including a plurality of pixels, an image analyzer for analyzing the input image and determining whether the input image is a still image, a data analyzing unit for converting the digital video data of the input image into a data voltage, The gate pulse is supplied to the gate lines other than the gate lines except for 3k (where k is a positive integer) +1 gate lines for N (N is a natural number) frame period when the input image is a still image, and N The gate pulse is supplied to the gate lines other than the (3k + 2) -th gate lines during the (+ During the second frame period includes a gate driving circuit for supplying a gate pulse to the remaining gate lines other than said 3k + 3-th gate line.
The subpixels within one pixel share one data line to continuously charge the time-division-supplied data voltage through one data line.
The column direction length of each of the subpixels is longer than the line direction length of each of the subpixels.

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The present invention shares subpixels within a pixel with one data line. The subpixels are fabricated such that the column direction length is longer than the line direction length, and charge the data voltages supplied in a time division manner through one data line. In addition, if the input image is a still image, the output of the gate driving circuit is controlled in the horizontal interlace mode to reduce the driving frequency of the pixels to 2/3. As a result, the present invention can reduce the number of source drive ICs necessary for driving the data lines of the liquid crystal display panel, improve the readability of characters, and reduce power consumption of the source drive IC while reducing display quality deterioration on static display.

1 is a view showing a part of a pixel array of a conventional TRD liquid crystal display device.
FIG. 2 is a diagram showing an experiment result of displaying characters as a clear type in the pixels as in FIG. 1. FIG.
3 is a block diagram illustrating a liquid crystal display device according to an embodiment of the present invention.
FIG. 4 is an equivalent circuit diagram showing a part of a pixel array according to the liquid crystal display panel shown in FIG. 3. FIG.
FIG. 5 is a diagram showing an experiment result of displaying a clear type character in a liquid crystal display device having the pixel array shown in FIG.
6 is a diagram showing the dot inversion polarity of the liquid crystal display panel in the progressive mode.
FIG. 7 is a waveform diagram showing a data voltage and a gate pulse for driving a dot-inversion as shown in FIG.
8A to 8C are diagrams showing dot inversion polarities of a liquid crystal display panel during three consecutive frame periods in the horizontal interlace mode.
FIG. 9A is a waveform diagram showing a data voltage and a gate pulse for driving a dot inversion as shown in FIG. 8A. FIG.
FIG. 9B is a waveform diagram showing a data voltage and a gate pulse for driving a dot inversion as shown in FIG. 8B.
9C is a waveform diagram showing a data voltage and a gate pulse for driving a dot inversion as shown in FIG. 8C.
FIG. 10 is a diagram illustrating driving states of specific subpixels in the (3i + 1) th column shown in FIGS. 8A to 8B during a 16-frame period.
11 is a flowchart illustrating a method of driving a liquid crystal display according to an exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

3, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal display panel 100, an image analysis unit 110, a timing controller 101, a data driving circuit 102, a gate driving circuit 103, And the like.

In the liquid crystal display panel 100, a liquid crystal layer is formed between two glass substrates. The liquid crystal display panel 100 includes pixels arranged in a matrix form by an intersection structure of the data lines 105 and the gate lines 106. [ The pixel arrangement of the liquid crystal display panel 100 may be realized as shown in FIG.

The TFT array substrate of the liquid crystal display panel 100 is provided with data lines 105, gate lines 106 intersecting with the data lines 105, intersections of the data lines 105 and gate lines 106, A pixel electrode 1 of a liquid crystal cell Clc connected to the TFT, a storage capacitor Cst connected to the pixel electrode 1, and the like are formed. The data lines 105 are formed along the column direction (y-axis direction), and the gate lines 106 are formed along the line direction (x-axis direction) perpendicular to the column direction.

The liquid crystal cells Clc are connected to the TFT and driven by the electric field between the pixel electrodes 1 and the common electrode 2. [ The common electrode 2 is supplied with the common voltage Vcom. The common electrode 2 may be formed on the TFT array substrate and / or the color filter array substrate. A black matrix, a color filter, and the like are formed on the color filter array substrate of the liquid crystal display panel 100. A polarizing plate is attached to each of the TFT array substrate and the color filter array substrate of the liquid crystal display panel 100. An alignment film for setting a pre-tilt angle of liquid crystal molecules is formed on a surface of the TFT array substrate and the color filter array substrate, which face the liquid crystal layer, respectively.

The liquid crystal display panel 100 may be implemented by a vertical electric field driving method such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode or by a horizontal electric field driving method such as an IPS (In Plane Switching) mode and an FFS (Fringe Field Switching) Lt; / RTI > The liquid crystal display device of the present invention can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, and a reflective liquid crystal display device. In a transmissive liquid crystal display device and a transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The image analysis unit 110 analyzes digital video data of an image input from the host system 104 to determine whether the currently input image is a still image or a moving image. The image analysis algorithm uses a known moving image / still image judgment algorithm for detecting a motion vector and judging a moving image and a still image based on the motion vector or judging a moving image and a still image through data comparison between frames. The image analysis unit 110 may be embedded in the host system 104 or the timing controller 101.

The timing controller 101 supplies digital video data (RGB) of the input image input from the host system 104 to the data driving circuit 102. The timing controller 101 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE and a dot clock CLK from the host system 104, And generates timing control signals for controlling the operation timing of the driving circuit 102 and the gate driving circuit 103. [ The timing control signals include a gate timing control signal for controlling the operation time of the gate drive circuit 103, a data timing control signal for controlling the operation timing of the data drive circuit 102 and the polarity of the data voltage.

The gate timing control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), and the like. The gate start pulse GSP is applied to the gate drive IC which generates the first gate pulse to control the gate drive IC so that the first gate pulse is generated. The gate shift clock GSC is a clock signal commonly input to the gate drive ICs, and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output of the gate drive ICs.

The data timing control signal includes a source start pulse SSP, a source sampling clock SSC, a polarity control signal POL, and a source output enable signal SOE. The source start pulse SSP controls the data sampling start timing of the data driving circuit 102. The source sampling clock SSC is a clock signal that controls the sampling timing of data in each of the source drive ICs on the basis of the rising or falling edge. The source output enable signal SOE controls the output timing of the data driving circuit 102. The polarity control signal POL indicates the polarity inversion timing of the data voltage outputted from the data driving circuit 102. [

The timing controller 101 receives the still image / moving image determination result input from the image analysis unit 110 and converts the gate timing control signals GSP, GSC, and GOE into a horizontal interlace mode if the input image is a still image Occurs. The timing controller 101 generates the gate timing control signals GSP, GSC and GOE in a progressive mode when the input image is a moving image.

The gate timing control signals in the progressive mode are generated in the same manner as the gate timing control signals in the conventional normal driving state.

The gate timing control signals in the horizontal interlace mode are applied to gate pulses supplied to 3k (k is a positive integer) +1 gate lines, gate pulses supplied to 3k + 2 gate lines, 3k + 3 gate lines The supplied gate pulse is selectively blocked. To this end, the gate driving circuit 103 includes a first shift register for sequentially supplying an output to 3k + 1-th gate lines, a second shift register for sequentially supplying an output to 3k + 2-th gate lines, And a third shift register sequentially supplying an output to the (3 + 3) th gate lines. The timing controller 101 controls a gate start pulse GSP applied to each of the shift registers, a gate shift signal GSP applied to each of the shift registers G1, G2, and G3 so that the outputs of the first through third shift registers of the gate driving circuit 103 can be independently controlled in the horizontal interfering mode, The clock GSC and the gate output enable signal GOE to the shift registers of the gate driving circuit 103 independently.

The host system 104 may be a video source such as a set-top box, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system . In addition, the host system 104 includes a system on chip (hereinafter referred to as "SoC") including a scaler to display graphic data from an external video source device on the liquid crystal display panel 100 Into a suitable format. The host system 104 outputs image data and timing signals (Vsync, Hsync, DE, CLK) from a video source to a timing controller (not shown) via an interface such as a Low Voltage Differential Signaling (LVDS) interface or a Transition Minimized Differential Signaling (101) and the image analysis unit (110).

The data driving circuit 102 includes a plurality of source drive ICs. The data driving circuit 102 latches the digital video data RGB input from the timing controller 101 in response to the data timing control signal. The data driving circuit 102 converts the digital video data RGB into an analog positive / negative gamma compensation voltage in response to the polarity control signal POL to generate a positive / negative data voltage. The positive polarity / negative polarity data voltages output from the data driving circuit 102 are supplied to the data lines 105. The source drive ICs of the data driving circuit 102 may be connected to the data lines 105 of the liquid crystal display panel 100 by a COG (Chip On Glass) process or a TAB (Tape Automated Bonding) process.

The gate driving circuit 103 outputs a gate pulse synchronized with the data voltage in response to gate timing control signals using a level shifter and a shift register. The gate driving circuit 103 supplies gate pulses, which are synchronized with the data voltage, to the gate lines 106 in a non-sequential manner in response to the gate timing control signals in the horizontal interlace mode. The gate drive circuit 103 sequentially supplies the gate lines 106 with gate pulses synchronized with the data voltage in response to the gate timing control signals in the progressive mode. The gate driving circuit 103 may be formed directly on the TFT array substrate of the liquid crystal display panel 100 in a GIP (Gate In Panel) manner or may be connected to the gate lines 106 of the liquid crystal display panel 100 in a TAB manner have.

When the gate timing control signals in the horizontal interlace mode are generated, the gate driving circuit 103 sequentially applies gate pulses to the remaining gate lines excluding the (3k + 1) -th gate lines during N (N is a natural number) The gate pulses are not supplied to the (+1) th gate lines. The gate driving circuit 103 sequentially applies gate pulses to the remaining gate lines except the (3k + 2) -th gate lines during the (N + 1) -th frame period in response to the gate timing control signals in the horizontal interlace mode, Gate pulses are not supplied to the gate lines. In addition, the gate driving circuit 103 sequentially applies gate pulses to the remaining gate lines except the (3k + 3) -th gate lines during the (N + 2) -th frame period in response to the gate timing control signals in the horizontal interlace mode, Gate pulses are not supplied to the third gate lines.

4 is an equivalent circuit diagram showing a part of the pixel array of the liquid crystal display panel 100 shown in Fig. In Fig. 4, D1 to D3 are data lines, and G1 to G9 are gate lines.

Referring to FIG. 4, one pixel includes a red subpixel R, a green subpixel G, and a blue subpixel G arranged in parallel along the line direction (x-axis direction). The red subpixels R of the pixels are arranged side by side in the column direction (y-axis direction) in the (3i + 1) -th column. The green subpixels G of the pixels are arranged side by side in the column direction in the (3i + 2) th column. And the blue subpixels (B) of the pixels are arranged side by side in the column direction in the (3i + 3) th column.

In the pixel array of FIG. 4, one pixel of subpixels (RGB) shares the same data line and continuously charges the data voltage supplied in a time-division manner through that data line. As a result, the liquid crystal display of the present invention can reduce the number of data lines 105 and source driver ICs by one-third compared to a general liquid crystal display device in which each of the subpixels is connected to an independent data line.

The pixel array structure of FIG. 4 will be described in detail with reference to the connection relationship between the subpixels of the first pixel pix1 and the data lines, which time-divisionally charges the data voltages from the first data line D1.

A pixel electrode and a TFT of a red subpixel R are defined as a first pixel electrode Pl and a first TFT T1, respectively. The pixel electrode and the TFT of the green subpixel G are defined as the second pixel electrode P2 and the TFT T2 respectively and the pixel electrode of the blue subpixel B and the TFT are defined as the third pixel electrode (P3) and a third TFT (T3). In order to time-division drive the sub-pixels of the first pixel, gate pulses are sequentially applied to the first to third gate lines G1 to G3.

The first TFT T1 supplies a red data voltage from the first data line D1 to the first pixel electrode P1 in response to the first gate pulse from the first gate line G1. A gate electrode of the first TFT (T1) is connected to the first gate line (G1), and a drain electrode is connected to the first data line (D1). The source electrode of the first TFT (T1) is connected to the first pixel electrode (Pl). The second TFT T2 supplies the data voltage from the first data line D1 to the second pixel electrode P2 in response to the second gate pulse from the second gate line G2. The gate electrode of the second TFT T2 is connected to the second gate line G2, and the drain electrode thereof is connected to the first data line D1. And the source electrode of the second TFT T2 is connected to the second pixel electrode P2. The third TFT T3 supplies the data voltage from the first data line D1 to the third pixel electrode P3 in response to the third gate pulse from the third gate line G3. The gate electrode of the third TFT T3 is connected to the third gate line G3, and the drain electrode thereof is connected to the first data line D1. And the source electrode of the third TFT T3 is connected to the third pixel electrode P3.

In FIG. 4, the first gate line G1 is disposed over the pixels and the second and third gate lines G2 and G3 are disposed under the pixels, but are not limited thereto. For example, the first gate line G1 may be formed below the pixels along with the second and third gate lines G2 and G3.

In the pixel array shown in Fig. 4, the column direction length of the subpixel is longer than the line direction length. Thus, the subpixel has a long structure in the column direction. Due to the long sub-pixel structure in the line direction, if a small text is displayed in the pixel array as shown in Fig. 4, the text readability of the text becomes significantly higher than the pixel array of Fig. 1, as seen in Fig.

The liquid crystal display device is driven by a version method in which the polarity of the data voltage is N (N is a natural number) in order to reduce the deterioration of the liquid crystal and the afterimage.

6 is a diagram showing the dot inversion polarity of the liquid crystal display panel in the progressive mode. FIG. 7 is a waveform diagram showing a data voltage and a gate pulse for driving a dot-inversion as shown in FIG.

Referring to Figs. 6 and 7, the polarity control signal POL is inverted to one horizontal period period. One horizontal period means one line scanning time in which data is written to pixels of one display line in the liquid crystal display panel 100. [ The polarity control signal POL is inverted in phase every frame to invert the polarity of the data voltage charged in the pixels every frame period. The source drive ICs reverse the polarity of the data voltage supplied to the data lines D1 to D3 in response to the polarity control signal POL. Each of the data voltages is supplied to the data lines for about 1/3 horizontal period.

The gate drive circuit 103 sequentially supplies gate pulses G1 to G9 with gate pulses having a pulse width of approximately one horizontal period to compensate for a relatively insufficient pixel charge time. n (n is a natural number) gate pulse is overlapped with the (n-1) th gate pulse by about 2/3 of the pulse width, and overlaps with the (n + 1) th gate pulse by about 2/3 of the pulse width.

The pixels charge the data voltages to be displayed after precharging two data voltages and hold them for one frame period. For example, in FIG. 6, the blue subpixel B of the first pixel pix1 has the positive polarity data voltage Vp to be displayed after precharging the red and green data voltages R + and G + And the blue data voltage B + is held for approximately one frame period.

In FIG. 6, the polarities of the data voltages supplied to the odd data lines D1 and D3 and the even data line D2 at the same time are different from each other. The polarities of the data voltages supplied simultaneously to the odd data lines D1 and D3 and the even data line D2 are inverted every horizontal period. Accordingly, the data voltages charged in the subpixels of the first pixel are positive data voltages, and the data voltages charged in the subpixels of the second pixel neighboring the first pixel in the same display line are the negative data voltages. As a result, the pixel array of Fig. 6 operates with a version with horizontal 3 dots and vertical 1 dots.

The current of the source drive IC becomes large when transitioning from the positive data voltage to the negative data voltage and vice versa when transitioning from the negative data voltage to the positive data voltage. Therefore, the power consumption of the source drive IC increases as the number of transitions between voltages having different polarities increases. As shown in FIG. 7, since the three data voltages are continuously generated with the same polarity data voltage, the power consumption of the present invention can be reduced to about 1/3 or less as compared with the conventional liquid crystal display device.

8A to 8C are diagrams showing dot inversion polarities of a liquid crystal display panel during three consecutive frame periods in the horizontal interlace mode. 8A to 8C, D1 and D2 are data lines, and G1 to G6 are gate lines. FIG. 9A is a waveform diagram showing a data voltage and a gate pulse for driving a dot inversion as shown in FIG. 8A. FIG. FIG. 9B is a waveform diagram showing a data voltage and a gate pulse for driving a dot inversion as shown in FIG. 8B. 9C is a waveform diagram showing a data voltage and a gate pulse for driving a dot inversion as shown in FIG. 8C.

The data timing control signal and the data voltages output from the source drive IC are substantially the same in the progressive mode and the horizontal interlace mode.

In the horizontal interlace mode, the gate driving circuit 103 does not supply gate pulses to the (3k + 1) th gate lines as shown in Figs. 8A and 9A during the Nth frame period in response to the gate timing control signal in the horizontal interlace mode 3k + 2, and 3k + 3 < th > gate lines. As a result, during the Nth frame period of the horizontal interlace mode, the TFT is turned off in the sub-pixels of the 3i + 1th columns of the pixel array, so that the sub-pixels are not driven. Therefore, during the Nth frame period of the horizontal interlace mode, the subpixels of the 3i + 2 and 3i + 3 columns are driven to charge the data voltages, whereas the subpixels of the (3i + 1) th columns are not driven.

The gate driving circuit 103 responds to the gate timing control signal in the horizontal interlace mode to supply gate pulses to the (3k + 2) -th gate lines during the (N + 1) -th frame period as shown in FIGS. 8B and 9B, And the (3k + 3) th gate lines. As a result, during the (N + 1) th frame period of the horizontal interlace mode, the TFTs are turned off in the sub-pixels of the (3i + 2) th columns of the pixel array, so that the sub-pixels are not driven. Therefore, during the (N + 1) th frame period of the horizontal interlace mode, the subpixels of the (3i + 1) th and (3i + 3) th columns are driven to charge the data voltages, while the subpixels of the (3i + 2) th columns are not driven.

The gate drive circuit 103 supplies the gate pulse to the (3k + 3) th gate lines during the (N + 2) -th frame period in response to the gate timing control signal in the horizontal interlace mode, And the (3k + 2) th gate lines. As a result, during the (N + 1) th frame period of the horizontal interlace mode, the TFTs are turned off in the sub-pixels of the (3i + 3) th columns of the pixel array, so that the sub-pixels are not driven. Therefore, during the (N + 1) th frame period of the horizontal interlace mode, the subpixels of the (3i + 3) th columns are driven to charge the data voltages, whereas the subpixels of the (3i + 3) th columns are not driven.

FIG. 10 is a diagram illustrating a driving state of a specific sub-pixel in a 3i + 1th column in a liquid crystal display panel during a 16-frame period. In Fig. 10, a hatched box means a frame period during which a specific pixel is not driven, and a box marked with +/- signifies frame periods during which a specific pixel is driven and a positive / negative data voltage is charged to the specific pixel . By switching the operation mode to the horizontal interlace mode when a still image is input, it is possible to drive each of the subpixels at a low frequency of 40 Hz at a 60 Hz frame frequency, as shown in FIGS. 8 to 10, Power can be lowered.

11 is a flowchart illustrating a method of driving a liquid crystal display according to an exemplary embodiment of the present invention.

11, the present invention analyzes an input image and determines whether the input image is a still image or a moving image. (S1) If the input image is a still image, the liquid crystal display panel 100 is moved in the horizontal interlace mode (S2 and S3). On the other hand, if the input image is a moving image, the liquid crystal display panel 100 is scanned in the above-described progressive mode, and the brightness of the moving image reproduced in the liquid crystal display device Thereby increasing the display quality (S2 and S4)

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100: liquid crystal display panel 101: timing controller
102: data driving circuit 104: gate driving circuit
110: Image analysis section

Claims (5)

And a plurality of pixels arranged in a matrix form defined by the data lines and the gate lines, wherein the data lines are formed along the column direction, the gate lines are formed along the line direction orthogonal to the column direction, Display panel;
An image analyzer for analyzing an input image and determining whether the input image is a still image;
A data driving circuit for converting the digital video data of the input image into a data voltage and supplying the data voltage to the data lines; And
A gate pulse is supplied to the gate lines other than the gate lines of 3k (where k is a positive integer) +1 during the N (N is a natural number) frame period when the input image is a still image, And a gate driving circuit for supplying gate pulses to the remaining gate lines excluding the (3k + 2) -th gate line during the (N + 2) -th frame period and,
The subpixels within one pixel share one data line to continuously charge the time-division supplied data voltage through one data line,
And a column direction length of each of the subpixels is longer than a line direction length of each of the subpixels. The method according to claim 1,
The subpixels in one pixel are arranged in parallel along the line direction,
And the subpixels of the same color are arranged in parallel along the column direction.
The method according to claim 1,
Wherein the pixels include a first pixel for charging first to third data voltages supplied in a time division manner via a first data line,
Wherein the first pixel comprises:
(I + 1) th column in the liquid crystal display panel in response to the first gate pulse from the (3k + 1) -th gate line, the first data voltage from the first data line to the first pixel A first TFT for supplying an electric current to the electrode;
A second TFT for supplying a second data voltage from the first data line to a second pixel electrode arranged in a (3i + 2) th column of the liquid crystal display panel in response to a second gate pulse from the (3k + ; And
A third TFT for supplying a third data voltage from the first data line to a third pixel electrode arranged in a (3i + 3) th column of the liquid crystal display panel in response to a third gate pulse from the (3k + 3) And the liquid crystal display device. The method of claim 3,
Further comprising a timing controller for supplying digital video data of the input video to the data driving circuit and controlling an operation timing of the data driving circuit and the gate driving circuit,
The timing controller includes:
In response to a video determination result from the video analysis unit, controls the gate driving circuit in a horizontal interlace mode in every frame period when the input video is a still video,
Wherein the controller controls the gate driving circuit in a progressive mode every frame period when the input image is a moving image in response to a video determination result from the image analysis unit.
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