KR101577830B1 - liquid crystal display - Google Patents

Abstract

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device having liquid crystal display panels having liquid crystal cells arranged in a matrix form with TFTs formed at intersections of data lines and gate lines intersected with each other. A data driving circuit for converting digital video data into positive / negative data voltages and inverting the polarity of data voltages supplied simultaneously to the data lines according to a horizontal polarity pattern having a length of 8 dots or more; And a gate driving circuit for supplying a scan signal to the gate lines.

Description

[0001] LIQUID CRYSTAL DISPLAY [0002]

The present invention relates to a liquid crystal display device in which a horizontal polarity pattern is extended to 8 dots or more.

A liquid crystal display device of an active matrix driving type displays a moving picture by using a thin film transistor (hereinafter referred to as "TFT") as a switching element. This liquid crystal display device can be downsized as compared with a cathode ray tube (CRT), and is applied to a display device in a portable information device, an office machine, a computer, etc., and is also applied to a television, thereby quickly replacing a cathode ray tube.

The liquid crystal display device is driven in an inversion mode in which the polarity of the data voltage charged in the adjacent liquid crystal cells is opposite to each other and the polarity of the data voltage is periodically inverted in order to reduce direct current residual image and prevent deterioration of the liquid crystal. Most of the liquid crystal display apparatuses are applied with a version system with one horizontal and one vertical dots as shown in Fig. 1 and a version system with one horizontal dots and two vertical dots as shown in Fig.

1 is a view showing a polar pattern of a version system in which a version is a horizontal 1 dot and a vertical 1 dot. A version of 1 horizontal dot and 1 vertical dot reverses the polarity of data voltages charged in horizontal and vertical neighboring liquid crystal cells by one dot (or one liquid crystal cell) unit.

Fig. 2 is a diagram showing a polar pattern of a version system of horizontal 1 dot and vertical 2 dot. In the version of 1 horizontal and 1 vertical dots, the polarities of the data voltages charged in the horizontally adjacent liquid crystal cells are inverted in units of one dot, and the polarities of the data voltages charged in vertically adjacent liquid crystal cells are set to 2 dots . In the inversion method as shown in Figs. 1 and 2, the polarities of the data voltages are inverted every frame.

The liquid crystal cells of one horizontal line are simultaneously charged through the TFTs turned on simultaneously according to the same gate pulse, as can be seen from the polarity sign +/- shown in Figs. 1 and 2 The horizontal polarity pattern of the data voltages includes patterns in which the "+ - + -" or "- + + -" pattern is repeated.

When the data of the special pattern in which the white gradation data and the black gradation data are regularly repeated are input to the liquid crystal display driven by the inversion method as shown in FIGS. 1 and 2, the polarity of the data voltages charged at the same time Polarity.

Figs. 3 and 4 are diagrams showing examples of special patterns. Fig.

3 is an example of a one-pixel inverted pattern.

Referring to FIG. 3, one pixel includes RGB sub-pixels. The one pixel inverted pattern is a pattern in which data voltages charged in neighboring pixels in the horizontal and vertical directions alternate with white gradation and black gradation. If the liquid crystal display device to which the one-pixel inversion pattern is input is driven by the version method of horizontal 1 dot and vertical 2 dot as shown in FIG. 2, the polarity deflection of the pixels to which the white gradation data voltage is charged in each of the horizontal lines The polar deflection becomes large when viewed in each of the R sub-pixel, the G sub-pixel and the B-sub pixel. Also, the polarity deflection of each of the R + B sub-pixels, R + G sub-pixels, and G + B sub-pixels becomes large. For example, in FIG. 3, among the pixels of the first line (LINE # 1) that simultaneously charges the data voltages by the first gate pulse, the polarity of the pixels charging the white gradation voltage is "+ R, -G, + B "And is biased to the positive polarity (+). Of the pixels for charging the white gradation data voltage in the first line LINE # 1, the R sub-pixel, the B sub-pixel and the R + B sub-pixel each only charge the positive white gradation voltage, Only the negative white gradation voltage is charged.

Figure 4 is an example of a smear pattern.

Referring to FIG. 4, a smear pattern is a pattern in which data voltages charged in neighboring sub-pixels are alternated with white gradation and black gradation, and gradations of the same data voltages are the same in sub-pixels having the same color. If the liquid crystal display device to which the smear pattern is input is driven by a version scheme of horizontal 1 dot and vertical 2 dot as shown in FIG. 2, the sub-pixels to which the white gradation data voltage is charged in each of the horizontal lines, The polarity of the polarity of the polarity of the polarity of the polarity of the polarity of the polarity of the polarity of the polarity is increased.

3 and 4 are input to a liquid crystal display device driven by a version method of horizontal 2 dot and vertical 2 dot although not shown, pixels (or sub-pixels) for charging data voltages simultaneously by the same gate pulse Pixels) of the pixel are severely polarized.

As described above, when the polarity of the pixels (or sub-pixels) that simultaneously charge the data voltages by the same gate pulse shifts to a certain polarity, the common voltage applied to the common electrode by the coupling of the pixel electrode and the common electrode The data voltage changes in the polarity deflection direction. Due to the common voltage that varies with the polarity deviation of the data voltage, the liquid crystal cells in the horizontal line direction charging the polarity-deflected data voltages at the same time have a lower charge amount of the data voltage, resulting in lowered luminance and color distortion.

When the crosstalk pattern data as shown in Fig. 5 is input to the liquid crystal display device driven by the inversion method as shown in Figs. 1 and 2, a horizontal crosstalk is observed. The crosstalk pattern includes a white square pattern disposed in the center portion of the black background. When the data polarity of the cross pattern is inverted by the inversion method as shown in FIGS. 1 and 2, the polarity deflection is largely generated at the upper and lower lines without the white square pattern, and the luminance is lowered. However, In the central lines including the pattern, the degree of polarity deflection is relatively small, which is relatively brighter than the upper and lower lines.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a liquid crystal display device capable of preventing polarity deflection of liquid crystal cells addressing data at the same time, And a display device.

According to an aspect of the present invention, there is provided a liquid crystal display device comprising: a liquid crystal display panel having liquid crystal cells arranged in a matrix form with TFTs formed at intersections of data lines and gate lines intersecting with each other; A data driving circuit for converting digital video data into positive / negative data voltages and inverting the polarity of data voltages supplied simultaneously to the data lines according to a horizontal polarity pattern having a length of 8 dots or more; And a gate driving circuit for supplying a scan signal to the gate lines.

The present invention controls the polarity of the data voltages charged in the liquid crystal cells simultaneously addressing the data to a horizontal polarity pattern having a length of 8 dots or more so that data of a special pattern or crosstalk pattern in which white gradation and black gradation alternate Polarity deflection can be prevented when input. As a result, the present invention can prevent the fluctuation of the common voltage due to the polarity deviation of the data voltage, thereby realizing a liquid crystal display device in which display quality is not deteriorated in any data.

In the following embodiments, it is assumed that the horizontal polarity pattern is defined as a polarity pattern of data voltages charged in liquid crystal cells which are simultaneously and simultaneously addressed with data. This horizontal polarity pattern has a length of 8 dots or more and is repeated in one line of the liquid crystal display panel at the same time. If the length of the horizontal polarity pattern is 8 dots, the horizontal polarity pattern includes a positive polarity and a negative polarity pattern combination of data voltages simultaneously supplied to eight neighboring data lines through eight adjacent output channels in the data driving circuit . One dot has the same meaning as one sub-pixel or one liquid crystal cell. The horizontal polarity pattern includes polarity patterns in which the polarity and the polarity are alternated according to a predetermined rule. In the following embodiments, the horizontal polarity pattern is exemplified by a polar pattern such as "+ - - + - + + -" or "- + + - + - - +" going from left to right, but its length and polarity pattern are various Can be selected.

Hereinafter, a preferred embodiment of the present invention will be described with reference to FIGS.

Referring to FIG. 6, a liquid crystal display device according to an embodiment of the present invention includes a liquid crystal display panel 100, a timing controller 101, a data driving circuit 102, and a gate driving circuit 103. The data driving circuit 102 includes a plurality of source drive ICs. The gate drive circuit 103 includes a plurality of gate drive ICs.

In the liquid crystal display panel 100, a liquid crystal layer is formed between two glass substrates. The liquid crystal display panel includes liquid crystal cells Clc arranged in a matrix form by an intersection structure of the data lines 105 and the gate lines 106. [

Data lines 105, gate lines 106, TFTs, and a storage capacitor Cst are formed on a lower glass substrate of the liquid crystal display panel 100. [ The liquid crystal cells Clc are connected to the TFT and driven by the electric field between the pixel electrodes 1 and the common electrode 2. [ On the upper glass substrate of the liquid crystal display panel 100, a black matrix, a color filter, and a common electrode 2 are formed.

On the upper glass substrate and the lower glass substrate of the liquid crystal display panel 100, a polarizing plate is attached and an alignment film for setting a pre-tilt angle of the liquid crystal is formed.

The common electrode 2 is formed on an upper glass substrate in a vertical electric field driving mode such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode. The common electrode 2 is formed of an IPS (In Plane Switching) mode, an FFS (Fringe Field Switching) Is formed on the lower glass substrate together with the pixel electrode 1 in the same horizontal electric field driving system. The common electrode 2 may be formed on the upper glass substrate when the pixel array of the liquid crystal display panel 100 is implemented as shown in FIG. 7, and when the pixel array of the liquid crystal display panel 100 is implemented as shown in FIG. 8 And may be formed on the lower glass substrate in a pattern in a direction parallel to the data lines between the data lines.

The liquid crystal display panel 100 applicable to the present invention can be implemented in any liquid crystal mode as well as a TN mode, a VA mode, an IPS mode, and an FFS mode. The liquid crystal display device of the present invention can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, and a reflective liquid crystal display device. In a transmissive liquid crystal display device and a transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The timing controller 101 supplies digital video data RGB input from the system board 104 to the data driving circuit 102. The timing controller 101 inputs timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE and a dot clock CLK from the system board 104 And generates control signals for controlling the operation timings of the data driving circuit 102 and the gate driving circuit 103. The control signals include a gate timing control signal for controlling the operation time of the gate drive circuit 103, a data timing control signal for controlling the operation timing of the data drive circuit 102 and the vertical polarity of the data voltage.

The gate timing control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), and the like. The gate start pulse GSP is applied to the gate drive IC which generates the first gate pulse to control the gate drive IC so that the first gate pulse is generated. The gate shift clock GSC is a clock signal commonly input to the gate drive ICs, and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output of the gate drive ICs.

The data timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), and a source output enable (SOE) And the like. The source start pulse SSP controls the data sampling start timing of the data driving circuit. The source sampling clock SSC is a clock signal for controlling the sampling timing of data in the data driving circuit 102 on the basis of the rising or falling edge. The polarity control signal POL controls the polarity inversion timing of the data voltage output from the data driving circuit 102. [ The source output enable signal SOE controls the output timing of the data driving circuit 102. The source start pulse SSP and the source sampling clock SSC may be omitted if the digital video data to be input to the data driving circuit 102 is transmitted in the mini LVDS interface standard.

Each of the source driver ICs of the data driving circuit 102 includes a shift register, a latch, a digital-analog converter, an output buffer, and the like. The data driving circuit 102 latches the digital video data RGB under the control of the timing controller 101. The data driving circuit 102 converts the digital video data RGB into an analog positive / negative gamma compensation voltage in response to the polarity control signal POL to invert the polarity of the data voltage, The polarity of the data voltage is inverted by the repetitive pattern of the pattern. The data driving circuit 102 simultaneously supplies the data voltages whose polarities are converted to the data lines 105 in a repetitive pattern of a horizontal polarity pattern having a length of 8 dots or more each time gate pulses are supplied to the gate lines G1 to Gn do.

The gate driving circuit 103 sequentially supplies gate pulses to the gate lines 106 in response to gate timing control signals.

7 is an equivalent circuit diagram showing a part of a pixel array according to the first embodiment of the present invention.

In the pixel array of FIG. 7, the data lines D1 to D8 and the gate lines G1 to G4 are crossed. In this pixel array, the liquid crystal cells of the red sub pixel R, the liquid crystal cells of the green sub pixel G, and the liquid crystal cells of the blue sub pixel B are arranged along the column direction. Each of the TFTs applies a data voltage from the data lines D1 to D8 to the pixel electrodes of the liquid crystal cells arranged on the left side (or right side) of the data lines D1 to D8 in response to gate pulses from the gate lines G1 to G5, . In the pixel array shown in Fig. 4, one pixel includes a red sub-pixel R, a green sub-pixel G and a blue sub-pixel B adjacent to each other along a row direction (or a line direction) orthogonal to the column direction . When the resolution of the pixel array shown in Fig. 4 is m x n, m x 3 (where 3 is RGB) data lines and n gate lines are required. Gate pulses synchronized with the data voltage are sequentially supplied to the gate lines G1 to G5 of the pixel array, and the gate pulses are generated with a pulse width of approximately one horizontal period. Each time a gate pulse is applied to the gate lines G1 to G5, the data driving circuit 102 simultaneously outputs data voltages whose polarity is inverted in a horizontal polarity pattern having a length of 8 dots or more, Lt; / RTI > Therefore, the liquid crystal cells arranged horizontally in the same lines LINE # 1 to LINE # 4 charge the data voltages whose polarity is inverted to a horizontal polarity pattern having a length of 8 dots or more.

8 is an equivalent circuit diagram showing a part of the pixel array according to the second embodiment of the present invention.

The pixel array of Fig. 8 requires m2 / 3x3 data lines and n2 / 3 gate lines when the resolution is mxn. Thus, the pixel array of FIG. 8 can reduce the number of data lines and gate lines compared to the pixel array of FIG. In the pixel array shown in Fig. 8, the liquid crystal cells of the red sub pixel R, the liquid crystal cells of the green sub pixel G, and the liquid crystal cells of the blue sub pixel B are arranged along the column direction. In this pixel array, one pixel includes a red sub-pixel R, a green sub-pixel G and a blue sub-pixel B adjacent to each other along a line direction orthogonal to the column direction. In this pixel array, two lines are selected according to the gate pulses supplied to the three gate lines. The pulse width of the gate pulse is approximately 2/3 horizontal period. Common lines to which a common voltage is supplied are formed between the data lines D1 to D8 at predetermined intervals and are formed in a direction parallel to the data lines D1 to D8. For example, between the second data line D2 and the third data line D3, between the fourth data line D4 and the fifth data line D5, between the sixth data line D6 and the seventh data line D6, Between the data lines D7, a common line may be formed, respectively. Liquid crystal cells of the odd-numbered lines LINE # 1 and LINE # 3 are connected to the gate electrodes G1 and G4 supplied from the third (i is positive integer) +1 gate lines G1 and G4 and the (3i + 2) The data voltage is charged according to the pulses. The liquid crystal cells of the even lines LINE # 2 and LINE # 4 are driven in accordance with gate pulses supplied from the (3i + 2) th gate lines G2 and G5 and the (3i + 3) Charge. No liquid crystal cells are disposed between the (3i + 3) th gate line G3 and the (3i + 1) th gate line G4. When a gate pulse is applied to the (3i + 1) th gate lines G1 and G4 and the (3i + 3) th gate lines G3 and G6, the data driver circuit 102 generates a horizontal polarity pattern having a length of 8 dots or more And supplies the inverted R data voltage and the B data voltage to the data lines D1 to D8. When the gate pulse is applied to the (3i + 2) -th gate lines G2 and G5, the data driving circuit 102 applies the G data voltages whose polarity is inverted to the horizontal polarity pattern having a length of 8 dots or longer, D8. Specifically, the gate driving circuit 103 applies the first gate pulse to the first gate line G1, and then applies the second gate pulse to the second gate line G2. The data driving circuit 102 supplies the R data voltage and the B data voltage, which are synchronized with the first gate pulse, to the data lines D1 to D8 as shown in FIGS. 18 and 19, And supplies the data voltage to the data lines D1 to D8. Subsequently, when the gate driving circuit 103 applies the third gate pulse to the third gate line G3, the data driving circuit 102 supplies the R data voltage and the B data voltage, which are synchronized with the third gate pulse, D1 to D8.

In the pixel array shown in Fig. 8, the connection relations of the TFTs are as follows. The first TFT T1 is turned on according to the first gate pulse to supply the R data voltage from the first data line D1 to the first pixel electrode PE1 of the first line LINE # 1. The drain electrode of the first TFT T1 is connected to the first data line D1, and the source electrode thereof is connected to the first pixel electrode PE1. The gate electrode of the first TFT (T1) is connected to the first gate line (G1). The second TFT T2 is turned on in accordance with the second gate pulse to supply the G data voltage from the second data line D2 to the second pixel electrode PE2 of the first line LINE # 1. The drain electrode of the second TFT T2 is connected to the second data line D2, and the source electrode thereof is connected to the second pixel electrode PE2. And the gate electrode of the second TFT T2 is connected to the second gate line G2. The third TFT T3 is turned on in accordance with the first gate pulse to supply the B data voltage from the second data line D2 to the third pixel electrode PE3 of the first line LINE # 1. The drain electrode of the third TFT T3 is connected to the second data line D2, and the source electrode thereof is connected to the third pixel electrode PE3. The gate electrode of the third TFT T3 is connected to the first gate line G1. The fourth TFT T4 is turned on in accordance with the third gate pulse to supply the R data voltage from the first data line D1 to the fourth pixel electrode PE4 of the second line LINE # 2. The drain electrode of the fourth TFT T4 is connected to the first data line D1, and the source electrode thereof is connected to the fourth pixel electrode PE4. And the gate electrode of the fourth TFT T4 is connected to the third gate line G3. The fifth TFT T5 is turned on in accordance with the second gate pulse to supply the G data voltage from the first data line D1 to the fifth pixel electrode PE5 of the second line LINE # 2. The drain electrode of the fifth TFT T5 is connected to the first data line D1, and the source electrode thereof is connected to the fifth pixel electrode PE5. And the gate electrode of the fifth TFT T5 is connected to the second gate line G2. The sixth TFT T6 is turned on in accordance with the third gate pulse to supply the B data voltage from the second data line D2 to the sixth pixel electrode PE6 of the second line LINE # 2. The drain electrode of the sixth TFT T6 is connected to the second data line D2, and the source electrode thereof is connected to the sixth pixel electrode PE6. And the gate electrode of the sixth TFT T6 is connected to the third gate line G3.

9 is a view showing an example of the horizontal polarity pattern HPP1. In FIG. 9, '+' denotes a positive polarity data voltage, and '-' denotes a negative polarity data voltage.

Referring to FIG. 9, the horizontal polarity pattern HPP1 has a length of 8 dots and determines the polarities of the data voltages in the form of "+ - - + - + + -" or "- + + - + - - +". This horizontal polarity pattern HPP1 can prevent polarity deflection in most data patterns.

The operation effect due to the horizontal polarity pattern HPP1 can be clearly seen in Figs. 10 to 12. Fig. As shown in FIG. 10, when a data pattern in which white gradation and black gradation alternate in one pixel unit is input to the liquid crystal display device, the data driving circuit 102 inverts the polarity of the data voltage according to the horizontal polarity pattern HPP1. The data voltages simultaneously output from the data driving circuit 102 are inverted to a polarity in which "+ - - + - + -" or "- + + - + - - +" is repeated by the horizontal polarity pattern HPP1. The data voltages charged in the liquid crystal cells simultaneously addressing data by the horizontal polarity pattern HPP1 are not polarized on a pixel-by-pixel basis or in a sub-pixel. In the first line LINE # 1 of Figure 10, The RGB data voltage polarities of the gradations are alternated with '+ - -' and '- + +', and alternatively '+ - +' and '- + -' are alternated. As shown in FIG. 10, The data driving circuit 102 inverts the polarity of the data voltage according to the horizontal polarity pattern HPP1 when the data pattern in which the gradation is alternated is input to the liquid crystal display device. Quot; + - - + - + + - "or" - + + - + - - + "is reversed to a polarity that is repeated. The data voltages charged in the liquid crystal cells simultaneously addressing the data by the horizontal polarity pattern HPP1 are not polarized in units of pixels or in the sub-pixels. In the first line (LINE # 1) of FIG. 10, the RGB data voltage polarities of the white gradations are alternated with '+ - -' and '- + +', and '+ - +' and '- + -' . Therefore, the polarities of the data voltages charged in the liquid crystal cells addressing the data at the same time are not deflected to any one polarity, and the common voltage does not fluctuate. Comparing FIG. 3 and FIG. 10, the polarity deflection preventing effect due to the horizontal polarity pattern HPP1 having an 8-dot length can be easily understood.

As shown in FIG. 11, when a data pattern in which white gradation and black gradation alternate in units of one sub-pixel is input to the liquid crystal display device, the data driving circuit 102 inverts the polarity of the data voltage according to the horizontal polarity pattern HPP1 . The data voltages simultaneously output from the data driving circuit 102 are inverted to a polarity in which "+ - - + - + -" or "- + + - + - - +" is repeated by the horizontal polarity pattern HPP1. The data voltages charged in the liquid crystal cells simultaneously addressing the data by the horizontal polarity pattern HPP1 are not polarized in units of pixels or in the sub-pixels. The lines LINE # 1 to LINE # 8 in FIG. 11 (+) And the number of negative data voltages (-) are the same among the white gradation data, the liquid crystal cells that address data at the same time are charged at the same time The polarities of the data voltages are not deflected to any one polarity and the common voltage does not fluctuate.

As shown in FIG. 12, when a data pattern in which white gradation and black gradation alternate in two sub-pixel units is input to the liquid crystal display device, the data driving circuit 102 inverts the polarity of the data voltage according to the horizontal polarity pattern HPP1 . The data voltages simultaneously output from the data driving circuit 102 are inverted to a polarity in which "+ - - + - + -" or "- + + - + - - +" is repeated by the horizontal polarity pattern HPP1. The data voltages charged in the liquid crystal cells simultaneously addressing the data by the horizontal polarity pattern HPP1 are not polarized on a pixel-by-pixel basis or in a sub-pixel. Each of the lines (the first line LINE # 1 The number of positive polarity data voltages (+) and the number of negative polarity data voltages (-) are the same in white gradation data. In each of the lines LINE # 1 to LINE # 8 in FIG. 11, The number of positive polarity data voltages (+) and the number of negative polarity data voltages (-) are the same in white gradation data. Therefore, the data voltages charged in the liquid crystal cells addressing data at the same time The polarity is a polarity Not is not the common voltage is changed.

If the horizontal polarity pattern length is 4 dots or less, polarity deflection may occur in the special pattern as described in the description of the related art. For example, as shown in FIG. 13, the polarities of the data voltages are inverted according to the horizontal polarity pattern HPP2 having a length of four dots of the '+ - - +' shape, The polarities of the data voltages charged in the liquid crystal cells addressing the data are deflected in units of subpixels. For example, in the first line (LINE # 1) of FIG. 14, the R data voltages are all positive (+) and the B data voltages are all negative (-).

FIG. 15 is a diagram showing the polarities of data voltages charged in each of the liquid crystal cells when the polarity of the data voltages is reversed to the horizontal polarity pattern HPP2 of 4-dot length as shown in FIG. 13 in the pixel array of FIG. 16 is a waveform diagram showing data voltages and gate pulses whose polarity is inverted according to the horizontal polarity pattern HPP2 of 4-dot length. When the data voltages whose polarities are inverted to the horizontal polarity pattern HPP2 in which '+ - - +' or '+ + -' are repeated are supplied to the data lines D1 to D8 of the pixel array shown in FIG. 8, The liquid crystal cells of the first line LINE # 1 are charged with the data voltages of the polarity pattern in which "+ + - - - +" is repeated. And black gradation are regularly repeated, a polarity deviation occurs in pixel unit and sub-pixel unit as shown in FIG.

FIG. 18 is a diagram showing the polarities of data voltages charged in each of the liquid crystal cells when the polarity of the data voltages is reversed to the horizontal polarity pattern HPP1 of 8 dot length as shown in FIG. 9 in the pixel array shown in FIG. 19 is a waveform diagram showing data voltages and gate pulses whose polarity is inverted according to a horizontal polarity pattern HPP1 of 8 dot length. The data voltages whose polarity is inverted by the horizontal polarity pattern HPP1 in which '+ - - + - + + -' or '- + + - + - - +' is repeated are applied to the data lines D1 To D8, the liquid crystal cells of the first line LINE # 1 charge the data voltages of the polarity pattern in which '+ + - - - + - + + + -' is repeated by the arrangement of the TFTs. When a data pattern in which the white gradation and the black gradation are regularly repeated in the inversion driven liquid crystal display device with such a polarity pattern is input, as clearly shown in Figs. 18 and 20, the liquid crystal cells for addressing data at the same time The number of positive polarity data voltages (+) and the number of negative polarity data voltages (-) are the same in pixel unit or subpixel unit. Therefore, in the liquid crystal display implemented by the pixel array as shown in FIG. 8, When a data pattern in which black gradations are alternated is input, By reversing the polarity of the data voltages in the same horizontal polarity pattern, the polarities of the data voltages charged in the liquid crystal cells addressing the data at the same time are not biased to any polarity and the common voltage does not fluctuate.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

1 is a view showing a polar pattern of a version system in which a version is a horizontal 1 dot and a vertical 1 dot.

Fig. 2 is a diagram showing a polar pattern of a version system of horizontal 1 dot and vertical 2 dot.

Figs. 3 and 4 are diagrams showing examples of special patterns. Fig.

5 is a diagram showing an example of a crosstalk pattern.

6 is a block diagram showing a liquid crystal display device according to an embodiment of the present invention.

7 is an equivalent circuit diagram showing a part of a pixel array according to the first embodiment of the present invention.

8 is an equivalent circuit diagram showing a part of the pixel array according to the second embodiment of the present invention.

9 is a diagram showing an example of the horizontal polarity pattern of the present invention.

FIGS. 10 to 12 are views showing the polarity deflection preventing effect due to the horizontal polarity pattern shown in FIG.

13 is a view showing an example of a horizontal polarity pattern having a 4-dot length.

14 is a diagram showing polarity deflection due to the horizontal polarity pattern shown in FIG.

FIG. 15 is a diagram showing the polarities of data voltages charged in each of the liquid crystal cells when polarities of data voltages are inverted in a horizontal polarity pattern of four dot length as shown in FIG. 13 in the pixel array of FIG.

16 is a waveform diagram showing data voltages and gate pulses whose polarity is inverted according to a horizontal polarity pattern of 4-dot length.

FIG. 17 is a view showing an example of polarity deflection that appears when data voltages whose polarities are inverted according to a horizontal polarity pattern of 4-dot length are supplied to the pixel array as shown in FIG.

FIG. 18 is a diagram showing polarities of data voltages charged in each of the liquid crystal cells when polarities of data voltages are inverted in a horizontal polarity pattern of 8 dot length as shown in FIG. 9 in the pixel array of FIG.

19 is a waveform diagram showing data voltages and gate pulses whose polarity is inverted according to a horizontal polarity pattern of 8 dot length.

FIG. 18 is a diagram showing an effect of preventing polarity deflection of data voltages charged in each of the liquid crystal cells when polarities of data voltages are inverted in a horizontal polarity pattern of 8 dot length as shown in FIG. 9 in the pixel array of FIG.

Description of the Related Art

100: liquid crystal display panel 101: timing controller

102: Data driving circuit 103: Gate driving circuit

Claims (4)

A liquid crystal display panel having data lines and gate lines crossed and TFTs formed at the intersections and liquid crystal cells arranged in a matrix form; The polarity of the data voltages simultaneously supplied to the data lines in accordance with the horizontal polarity pattern repeated in one line of the liquid crystal display panel is converted into positive / negative data voltages and has a length of 8 dots or more A data driving circuit for inverting the data driving circuit; And And a gate driving circuit for supplying a scan signal to the gate lines, Wherein the horizontal polarity pattern includes: And a polarity pattern of '+ - - + - + + -' or '- + + - + - - +' when the positive polarity is represented by '+' and the negative polarity is represented by '-'. The method according to claim 1, Wherein the polarity pattern of the data voltages simultaneously charged in the liquid crystal cells in the horizontal line direction is the same as the polarity pattern in which the horizontal polarity pattern is repeated. The method according to claim 1, In the liquid crystal display panel, Wherein when the resolution is mxn (m and n are positive integers), m2 / 3x3 data lines and n2 / 3 gate lines are provided. The method of claim 3, The TFTs A first TFT having a drain electrode connected to the first data line, a source electrode connected to the first pixel electrode, and a gate electrode connected to the first gate line; A second TFT having a drain electrode connected to the second data line, a source electrode connected to the second pixel electrode, and a gate electrode connected to the second gate line; A third TFT having a drain electrode connected to the second data line, a source electrode connected to the third pixel electrode, and a gate electrode connected to the first gate line; A fourth TFT having a drain electrode connected to the first data line, a source electrode connected to the fourth pixel electrode, and a gate electrode connected to the third gate line; A fifth TFT having a drain electrode connected to the first data line, a source electrode connected to the fifth pixel electrode, and a gate electrode connected to the second gate line; And A drain electrode connected to the second data line, a source electrode connected to the sixth pixel electrode, and a sixth TFT connected to the third gate line.

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