KR101432568B1 - Apparatus and method for driving liquid crystal display of 2 dot inversion type - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for preventing a horizontal line phenomenon from occurring due to a luminance difference between horizontal lines in a version-driven liquid crystal display device with two dots. The present invention as described above includes a timing controller for appropriately varying an even-numbered high section of a source-out enable signal or a gate-out enable signal to eliminate an imbalance in charged amount between an excellent horizontal line and a radial horizontal line; A gate driver for outputting a gate signal to each gate line of the liquid crystal panel, and a data driver for supplying a pixel signal to each data line.

2 dot inversion, horizontal line phenomenon

Description

 BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an apparatus and a method for driving a two-dot inversion liquid crystal display device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving technique of a liquid crystal display, and more particularly, to a driving apparatus and method for a version liquid crystal display device having two dots suitable for preventing a horizontal line phenomenon occurring in a version driving method with two dots.

2. Description of the Related Art In recent years, as information technology (IT) has advanced, flat panel displays have become more important as visual information delivery media. In order to secure more competitive power in the future, low power consumption, thinness, lightness and high image quality are required.

Description of the Related Art [0005] A liquid crystal display (LCD), which is a typical display device of a flat panel display, is an apparatus for displaying an image using optical anisotropy of a liquid crystal, and has advantages of thinness, small size, low power consumption and high image quality.

Such a liquid crystal display device is a display device capable of displaying a desired image by individually supplying image information to pixels arranged in a matrix form and adjusting the light transmittance of the pixels. Therefore, the liquid crystal display device includes a liquid crystal panel in which pixels, which are minimum units for realizing an image, are arranged in an active matrix form, and a driving unit for driving the liquid crystal panel. In addition, since the liquid crystal display device can not emit light by itself, a backlight unit for supplying light to the liquid crystal display device is provided. The driving unit includes a timing controller, a data driving unit, and a gate driving unit.

1 is a block diagram of a conventional liquid crystal display device. As shown in FIG. 1, a gate control signal GDC and a data control signal DDC for controlling the driving of the gate driver 12 and the data driver 13, A timing controller 11 for sampling the digital pixel data RGB, rearranging and outputting the sampled pixel data RGB; A gate driver 12 for supplying gate signals to the gate lines GL1 to GLn of the liquid crystal panel 14; A data driver 13 for supplying pixel signals to the data lines DL1 to DLm of the liquid crystal panel 14; And a liquid crystal panel 14 which displays liquid crystal cells driven by the gate signal and the pixel signals in a matrix form and displays an image.

The timing controller 11 generates a gate control signal GDC for controlling the gate driving unit 12 and a data control signal for controlling the data driving unit 13 using the vertical and horizontal synchronizing signals and the clock signals supplied from the system DDC). The timing controller 11 samples pixel digital data (hereinafter, referred to as RGB) input from the system, reorders the digital data, and supplies the sampled data to the data driver 13.

As an example of the gate control signal GDC, there are a gate start pulse GSP, a gate shift clock GSC and a gate-out enable GOE. As an example of the data control signal DDC, SSP, a source shift clock SSC, a source-out enable SOE, and a polarity signal POL.

The gate driver 12 sequentially supplies the gate signals to the gate lines GL1 to GLn in response to the gate control signal GDC input from the timing controller 11, The connected thin film transistor (TFT) is turned on in units of the corresponding gate line.

The data driver 13 converts the pixel data RGB into an analog pixel signal (data signal or data voltage) corresponding to the gray scale value in response to the data control signal DDC input from the timing controller 11 , And supplies the converted pixel signals to the data lines DL1 to DLm on the liquid crystal panel 14. [

The liquid crystal panel 14 has a data line (DL1~DLm) and a gate line, to the intersection of the (GL1~GLn) having a plurality of liquid crystal cells (C _LC) disposed in a matrix form a plurality of liquid crystal cells (C _LC Are driven by the pixel signal and the gate signal to display a desired image.

In the above description, the gate driver 12 and the data driver 13 are separately provided from the liquid crystal panel 14. However, in recent years, they have been widely used in various fields such as COF (Chip On Film), COG (Chip On Glass) In the liquid crystal panel 14 by a mounting technique such as the above.

In order to prevent deterioration of the liquid crystal cells, the liquid crystal display device uses an inversion method. In particular, in order to compensate for a dot-inversion method in which a large amount of electric power is consumed, A version method with a vertical two-dot as shown in FIG. 2B is mainly used.

FIGS. 2A and 2B show polarity of a pixel signal supplied to the liquid crystal cells divided into a radix frame (previous frame) and an excellent frame (current frame) in a version with a vertical two-dot version. In the odd-numbered frame and the odd-numbered frame shown in Figs. 2A and 2B, the polarity of the pixel signal is changed in the horizontal direction by the dot unit as in the conventional dot-inversion method, There is a characteristic that it changes in 2 dot unit.

3 is a waveform diagram of a pixel signal driven in accordance with the vertical 2-dot inversion method.

However, due to the load characteristic of the data driver 13, a difference in the amount of charge between the excellent horizontal line and the odd horizontal line appears in the version with a vertical two-dot pattern, which is represented by a luminance difference. For example, FIG. 4 shows the amount of charged charges of two consecutive pixels in the vertical direction in FIG. 2A or FIG. 2B, where the charged charge amount Qo of the pixel located on the odd horizontal line is greater than the even horizontal line Is smaller than the charged charge amount Qe of the pixel located at the pixel position.

The reason for this is that for pixels located in the radix horizontal line, the polarity changes from positive (+) to negative (-) signals, or vice versa, require a relatively long charging rise or fall time , Since the pixels located on the excellent horizontal line are changed in the signal of the same polarity, such time is less necessary.

In this case, when the TN mode is used as a reference, a pixel having a small amount of charge Qo located on the odd horizontal line is located on the even horizontal line and becomes relatively brighter than a pixel having a large amount of charge Qe. As a result, a luminance difference is generated between the odd horizontal line and the excellent horizontal line, thereby causing a 2-line dim phenomenon on the screen as shown in FIG.

The horizontal line phenomenon may be caused by a pixel voltage deviation due to parasitic capacitance between adjacent two gate lines. FIGS. 6A and 6B show the parasitic capacitance generation site and equivalent circuit.

That is, parasitic capacitance Cpp is generated between the storage metal for the storage capacitance and the pixel electrode of the previous stage in the vicinity of the adjacent gate lines GLn and GLn + 1, thereby causing a luminance difference between the corresponding horizontal lines As shown in Fig. 5, a horizontal line phenomenon occurred on the screen.

In the conventional liquid crystal display device in which the vertical 2-dot inversion method is applied, the difference in the amount of charge between the excellent horizontal line and the odd horizontal line, or the luminance difference between the odd horizontal line and the excellent horizontal line due to parasitic capacitance between two adjacent horizontal lines There is a problem that a 2-line dim phenomenon occurs.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to prevent the occurrence of a luminance difference between an odd horizontal line and an excellent horizontal line by appropriately varying a section of a gate-out enable signal with respect to an excellent horizontal line.

According to an aspect of the present invention, there is provided a timing controller for varying a high-order high period of a source-out enable signal or a gate-on enable signal so as to eliminate an unbalanced phenomenon of a charged amount between an excellent horizontal line and an odd- Wow; A gate driver for outputting a gate signal to each gate line of the liquid crystal panel in response to a gate control signal supplied from the timing controller; And a data driver for supplying a pixel signal to each data line of the liquid crystal panel in response to a data control signal supplied from the timing controller.

According to another aspect of the present invention, there is provided a method for controlling a memory device, the method comprising: determining whether a memory for changing a high-order high-level section of a source-out enable signal or a gate- Outputting the source high enable signal or the gate high enable high signal of the gate enable signal; When a memory for changing the high-order high period of the source-out enable signal or the gate-out enable signal is connected and the header information of the memory satisfies the condition, the source-out enable signal or the gate- And adjusting the high interval according to the value set in the memory by the adjuster and outputting the adjusted interval.

The present invention increases the odd-numbered high-level periods of the source-out enable signal and the gate-out enable signal so that the output times of the corresponding even-numbered pixel signals are reduced correspondingly, There is an effect that it is possible to prevent the phenomenon of the horizontal line (2-line dim) from being generated due to the elimination of the phenomenon and thereby the luminance difference between the odd horizontal line and the excellent horizontal line.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 7 is a block diagram showing an embodiment of a driving apparatus for a 2-dot inversion type liquid crystal display according to the present invention. As shown in FIG. 7, the gate driving unit 72 and the data driving unit 73 And outputs the gate control signal GDC and the data control signal DDC and appropriately varies the odd high section of the source out enable signal or the gate out enable signal so that the amount of charge A timing controller 71 for eliminating an imbalance phenomenon; A gate driver 72 for outputting a gate signal to each of the gate lines GL1 to GLn of the liquid crystal panel 74 in response to a gate control signal supplied from the timing controller 71; A data driver 73 for supplying a pixel signal to the data lines DL1 to DLm of the liquid crystal panel 74 in response to a data control signal supplied from the timing controller 71; And a liquid crystal panel 74 for displaying an image by providing liquid crystal cells driven by the gate signal and the pixel signal in a matrix form.

The timing controller 71 is configured to vary the high-order high period of the source-out enable signal or the gate-out enable signal based on the header value stored in the primitive 71A.

Hereinafter, the operation of the present invention will be described in detail with reference to FIGS. 8 to 10. FIG.

The timing controller 71 in the control board 70 generates a gate control signal GDC for controlling the gate driver 72 by using the vertical / horizontal synchronizing signal Hsync / Vsync supplied from the system and the clock signal CLK, And a data control signal DDC for controlling the data driver 73. In addition, the timing controller 71 samples digital pixel data (RGB) input from the system, rearranges the sampled pixel data, and supplies the same to the data driver 73.

The gate driver 72 sequentially supplies the gate signal to the gate lines GL1 to GLn in response to the gate control signal GDC input from the timing controller 71, ) Are turned on. Accordingly, the pixel signals supplied through the data lines DL1 to DLm are stored in the respective storage capacitors C _ST through the thin film transistors TFT.

To be more specific, the gate driver 72 shifts the gate start pulse according to the gate shift clock to generate a shift pulse. In response to the shift clock, the gate driver 72 supplies a gate signal composed of a gate on / off period (signal) to the corresponding gate line GL in each horizontal period. In this case, the gate driver 72 supplies the gate-on signal only in the enable period in response to the gate-out enable signal, and supplies the gate-off signal (gate-low signal) in the other periods.

The data driver 73 converts the pixel data RGB into an analog pixel signal (data signal or data voltage) corresponding to the gray level value in response to the data control signal DDC input from the timing controller 71 , And supplies the converted pixel signals to the data lines DL1 to DLm on the liquid crystal panel 74. [

To be more specific, the data driver 73 shifts the source start pulse according to the source shift clock to generate a sampling signal. The data driver 73 sequentially receives and latches the pixel data RGB in units of a predetermined unit in response to the sampling signal. The data driver 73 converts the latched pixel data RGB into analog pixel signals and supplies them to the data lines DL1 to DLm. In this case, the data driver 73 converts the polarity control signal into a positive polarity pixel signal and a negative polarity pixel signal. For example, the data driver 73 inverts the polarity of the pixel signal in a vertical two-dot inversion manner in response to a polarity control signal whose polarity is inverted every two horizontal periods. The data driver 73 supplies the pixel signals to the data lines DL1 to DLm only during the enable period in response to the source output enable signal.

The liquid crystal panel 74 is formed in each crossing portion of the plurality of liquid crystal cells (C _LC) arranged in a matrix, a data line (DL1~DLm) and gate line (GL1~GLn) each of the liquid crystal cell (C _LC (TFT) connected to each of the TFTs.

The thin film transistor TFT is turned on when a gate signal is supplied from the gate line GL and supplies a pixel signal supplied through the data line DL to the liquid crystal cell C _LC . The thin film transistor TFT is turned off when a gate off signal is supplied through the gate line GL, so that the pixel signal charged in the liquid crystal cell C _LC is maintained.

The liquid crystal cell C _LC includes a common electrode and a pixel electrode connected to the thin film transistor TFT via a liquid crystal. The liquid crystal cell C _LC further includes a storage capacitor C _ST to maintain the charged pixel signal stably until the next pixel signal is charged. The storage capacitor C _ST is formed between the pixel electrode and the previous gate line. In such a liquid crystal cell C _LC , the alignment state of the liquid crystal having dielectric anisotropy is varied according to the pixel signal charged through the thin film transistor (TFT), so that the light transmittance is adjusted to realize the gradation.

In the above description, the gate driver 72 and the data driver 73 are separately provided from the liquid crystal panel 74. In recent years, however, they have been described as COF (Chip On Film), COG ) Mounted on the liquid crystal panel 14 by a mounting technique such as a soldering method.

When the ON intervals of all the gate signals are set to the same interval, the liquid crystal display device of the present invention is driven by the vertical two-dot driving method. In this case, due to the load characteristic of the data driver 73, Differences in the amount of charge charge appear between the lines, which appear as a luminance difference.

The reason why the luminance difference between the excellent horizontal line and the odd-numbered horizontal line is generated is that the voltage of the pixel located at the odd-numbered (or even-th) horizontal line is changed from the positive (+) to negative (Or the odd-numbered) horizontal line is changed in the signal of the same polarity, the polarity of the polarity is changed, and thus the comparatively long rise time or fall time is required. This is because less time is required and relatively more charging time can be secured.

The luminance difference between the excellent horizontal line and the odd-numbered horizontal line is also generated by the parasitic capacitance between two adjoining gate lines.

In this case, when a TN mode is used as a reference, a pixel having a small amount of charged charges located on a radial horizontal line is positioned in a superior horizontal line, and becomes relatively brighter than a pixel having a large amount of charged charges, A difference is generated, thereby causing a 2-line dim phenomenon.

Therefore, in the present invention, the control board 70 is provided with an eipulm 71A. By using the eipulm 71A, the odd high section of the source-out enable signal SOE is varied as shown in Fig. 8, Thereby eliminating the imbalance in the charge amount between the lines.

For example, if the high-order high period of the source-out enable signal SOE is increased, the output time of the even-numbered pixel signal is correspondingly reduced. Therefore, as shown in FIG. 8, if the odd-numbered high section of the source-out enable signal SOE is fixed and the odd-numbered high section is appropriately increased, the imbalance in the amount of charge between the odd-numbered horizontal line and the odd-numbered horizontal line can be eliminated.

Hereinafter, the odd-numbered high-level change process of the source-out enable signal SOE for eliminating the unbalanced charge amount between the odd / even horizontal lines according to the present invention will be described.

When the power is turned on, the timing controller 71 determines whether the i-pillar 71A is connected to itself, and if it is determined that the i-pillar 71A is not connected, the timing controller 71 does not perform the high-interval change process of the source-out enable signal SOE (S1, S4)

The timing controller 71 reads the first column of the primitive 71A as shown in FIG. 10 when it is determined that the primitive 71A is connected to itself. The first column is used as a header to perform the high-interval change process of the source-out enable signal SOE according to this value. (S2)

If any one of the data values of addresses 00h to 04h among the header values 'FFh' is present, the process of changing the duration of the source-out enable signal SOE is not performed. In other words, even if the values of the addresses 05h and 06h are changed, if any of the data values of the addresses 00h to 04h is 'FFh', the original high section of the source out enable signal SOE is not changed (S3, S4)

If the data values of the addresses 00h to 04h are all recorded as '00' in the header, the length of the high section of the source-out enable signal SOE is determined according to the data values of the addresses 05h and 06h.

The data value of the address 05h is a value that determines the odd-numbered high period of the source-out enable signal SOE, and is set to a fixed value (e.g., 0.279 mu s) depending on the model. On the other hand, the data value of the address 06h is a value for determining the odd high period of the source-out enable signal SOE, and is set by the coordinator in a predetermined range, for example, within a range of from a minimum of 0.279 mu s to a maximum of 3.007 mu s Lt; / RTI >

To this end, the coordinator connects the PC or the controller to the EEPROM 71A via a connector, and then sets the odd high section of the source-out enable signal within the range from the minimum of 0.279 μs to the maximum of 3.007 μs, At this time, it is set to an optimum value which does not cause a 2-line dim phenomenon through several adjustment processes while viewing the screen.

In addition, the data value of the address 07h is a value that determines the access period of the iipulm 71A so that the timing controller 71 performs the high-interval change process of the source-out enable signal SOE.

That is, the upper bit value of the data value of the address 07h is a value for determining whether or not periodic access operation is performed. If the value is '1', periodic access operation is performed, and if it is '0', periodic access operation is not performed. If the lower bit value of the data value of the address 07h is a value for determining the access period, the access operation is performed every 55 frame cycles. If the value is '0', the access operation is performed only when the pattern is blue 31 gray pattern.

In other words, when the data value of the address 07h is '00' or '01', the periodic access operation is not performed. If the data value of the address 07h is '10', the access operation is performed every 55 frames. Also, if the data value of the address 07h is '11', the access operation is performed only when the pattern is blue (or white) 31 gray pattern.

For reference, the remaining part of the data area of the I-fill ROM 71A except for the header part of the first column is a data area related to the color coordinate information and the vendor information.

In the above description, the high period of the source-out enable signal SOE is varied to eliminate the luminance difference between the odd horizontal line and the excellent horizontal line, but the present invention is not limited thereto.

As another example of this, it is possible to change the high section of the gate-out enable signal GOE. In this case, the same effect can be obtained.

1 is a block diagram of a conventional liquid crystal display device.

Figures 2a and 2b are pixel polarity arrangements of a version 2 frame with vertical 2 dots.

3 is a waveform diagram of a pixel signal of a version system in which vertical two dots are provided.

Fig. 4 is a waveform chart showing the charge amount of the odd and even pixels. Fig.

5 is a schematic view of a screen in which a horizontal line phenomenon appears due to a luminance difference between adjacent horizontal lines;

6A is a plan view of a liquid crystal panel showing a generation site of parasitic capacitance;

6B is an equivalent circuit diagram of a liquid crystal panel according to the generation of parasitic capacitance.

7 is a block diagram of a driving apparatus for a 2-dot inversion type liquid crystal display device according to the present invention.

8 is a waveform diagram showing a variable section of a source-out enable signal;

9 is a control flowchart of a driving method in a 2-dot inversion type liquid crystal display device according to the present invention.

FIG. 10 is a data format of the Ipium that is applied to the present invention. FIG.

DESCRIPTION OF THE REFERENCE SYMBOLS

70: control board 71: timing controller

71A: Iipyrine 72: Gate driver

73: data driver 74: liquid crystal panel

Claims (7)

A timing controller for varying an odd-numbered high-level interval of any one of a source-out enable signal and a gate-out enable signal according to high-range variable information of a memory, Wow; A gate driver for outputting a gate signal to each gate line of the liquid crystal panel in response to a gate control signal supplied from the timing controller; And a data driver for supplying a pixel signal to each data line of the liquid crystal panel in response to a data control signal supplied from the timing controller, The high- Wherein the address information is recorded in a header area of the memory. The apparatus as claimed in claim 1, wherein the memory comprises iupilm. delete 2. The method of claim 1, wherein the high-interval variable information comprises information indicating whether or not to perform the high-interval variable process, information indicating how much the high-level variable information is to be varied, an access period of the memory to perform the high- Information is included in at least one of the two dot inversion liquid crystal display devices. A first step of outputting, if the change condition of the odd-numbered high interval is not satisfied with respect to any one of the source-out enable signal and the gate-out enable signal, the odd-numbered high- And a second step of adjusting and outputting the odd-numbered high-level interval according to the set value of the coordinator when the change-over condition of the odd-numbered high-level interval of the source-out enable signal or the gate- The changing condition of the even-numbered high- The memory for changing the corresponding high-order high period is not connected, or the header information of the memory does not satisfy the condition. delete 6. The method of claim 5, The set value of the second process is set to a value at which the adjuster does not cause a horizontal line phenomenon through one or more correction processes while viewing the screen The method comprising the steps of:

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