TWI552138B - Display and gate driver thereof - Google Patents

Description

Display and its gate drive circuit

The present invention relates to a display and a gate drive circuit thereof, and more particularly to a display having a plurality of latch circuits and a gate drive circuit therefor.

Liquid crystal displays (LCDs) have been in development for many years. Early developments in LCD TVs focused on light weight and small size, and successfully replaced the bulky and bulky cathode ray tube display. In recent years, with the development of memory in pixel (MIP) technology, the function of changing only part of the picture data has been paid more and more attention. In addition, the shift register in a conventional gate driver is not suitable for products of memory pixel (MIP) technology because of the limitation of having to transmit signals from the first stage. Therefore, it is generally replaced by a decoder circuit, so that only a part of the picture data can be changed and the power consumption can be reduced.

Please refer to FIG. 1, which is a circuit diagram of a decoding circuit 10 for a gate driver. The decoding circuit 10 has a plurality of output terminals O ₁ to O ₇ , and each of the output terminals O ₁ to O ₇ is coupled to a corresponding one of the scan lines in the display. The decoding circuit 10 causes the output terminals of the output terminals O ₁ to O ₇ to output a gate high potential according to the digital signal including the three bits A ₀ , A ₁ and A ₂ , and the remaining output terminals are gated. Very low potential. The decoding circuit 10 includes a plurality of inverters 12 for respectively inverting and outputting three bits A ₀ , A _{1 ,} and A ₂ . The decoding circuit 10 further includes a plurality of logic gates 14 coupled to the input end of the decoding circuit 10 and the inverter 12 for pairing the bits A ₀ , A ₁ and A ₂ and the bits A ₀ , A ₁ and A The inverse phase element of ₂ performs an operation to output a gate high potential to the scan line to be driven.

However, conventional decoding circuits use a large number of logic gate circuits, and the number of transistors required thereof greatly increases as the resolution of the display increases. Furthermore, each time the resolution of the display is doubled, each circuit of the gate driver of the display used to control the voltage level of the scan line needs to add an AND logic gate, and each logic The gate will use six transistors. Taking the decoding circuit 10 of FIG. 1 as an example, when the resolution is multiplied, that is, from eight output terminals to sixteen output terminals, each of the original output terminals O ₁ to O ₇ must be additionally used. In addition to setting one and logic gates, the other eight additional outputs must also have three and logic gates for each output. In other words, when the decoding circuit 10 is boosted from eight outputs to sixteen outputs, at least 192 (i.e., (8x1 + 8x3) x 6) transistors are added. Therefore, in the case of conventional decoding circuits, the number of transistors required is quite large.

One embodiment of the present invention provides a gate drive circuit. The gate drive circuit includes a logic control circuit and M latch circuits. The logic control circuit is coupled to the M scan lines for changing the voltage level of one of the M scan lines from the first voltage level to the second voltage level according to the digital signal and the pulse signal. And making the voltage level of the other one of the M scan lines the first voltage level. Where M is an integer greater than one. Each of the latching circuits is coupled to the logic control circuit and a corresponding one of the M scan lines for latching the corresponding voltage level of the corresponding scan line when the voltage level is at the first voltage level. The voltage level of the scan line.

An embodiment of the invention provides a display. The display comprises a plurality of data lines, a plurality of scan lines, a plurality of pixels, at least one source driving circuit, and the aforementioned gate driving circuit. Each pixel is coupled to a corresponding data line and a corresponding scan line. The at least one source driving circuit is coupled to the plurality of data lines for transmitting the data signal to the pixels by the plurality of data lines.

10‧‧‧Decoding circuit

12, 142, 162‧‧ ‧ inverter

14‧‧‧ and logic gate

16‧‧‧ pixels

18‧‧‧ memory unit

100‧‧‧ display

110‧‧‧ pixel array

120‧‧‧Source drive circuit

130‧‧ ‧ gate drive circuit

130A, 130B‧‧‧ gate drive circuit

140A, 140B‧‧‧ logic control circuit

144‧‧‧ input

150‧‧‧Switch Module

152‧‧‧First stage circuit

154‧‧‧Second stage circuit

156‧‧‧ third-level circuit

160, 160A, 160B, 160C, 160D‧‧‧ latch circuit

C1‧‧‧ capacitor

CK‧‧‧ clock signal

/CK‧‧‧Inverted signal of clock signal CK

C _P ‧‧‧pixel capacitor

A ₀ , A ₁ , A ₂ , D0, D1, D2‧‧‧ bits

/D0, /D1, /D2‧‧‧ anti-phase elements

D _P ‧‧‧ pixel data

G ₁ to G _M , G _y ‧‧‧ scan lines

IN‧‧‧ input

N1‧‧‧ second switch

N2, N3, N4, N5, N6‧‧‧ switch

O ₁ to O ₇ ‧‧‧ output

P1‧‧‧ first switch

P2, P3, P4, P5, P6‧‧‧ switch

Q‧‧‧ pixel switch

R‧‧‧resistance

S ₁ to S _P , S _x ‧‧‧ data line

T‧‧‧ clock cycle

T1, t2, t3, t4, t5, t6‧‧

V _COM ‧‧‧ common electrode

VGL‧‧‧first voltage level; gate low potential

VGH‧‧‧second voltage level; gate high potential

Fig. 1 is a circuit diagram of a decoding circuit for a gate driver.

2 is a schematic view of a display according to an embodiment of the present invention.

Figure 3 is a schematic diagram of the pixels of the display of Figure 2.

Fig. 4 is a circuit diagram of a gate driving circuit according to an embodiment of the present invention.

Fig. 5 is a timing chart of the gate driving circuit of Fig. 4.

Fig. 6 is a circuit diagram of a gate driving circuit according to an embodiment of the present invention.

Fig. 7 is a timing chart of the gate driving circuit of Fig. 6.

8 through 11 are circuit diagrams of latch circuits of different embodiments of the present invention, respectively.

First of all, it should be understood that the gate driving circuit disclosed in the present invention is applicable to a display using memory in pixel (MIP) technology, in addition to a general liquid crystal display. Please refer to Figure 2 and Figure 3. 2 is a schematic diagram of a display 100 according to an embodiment of the present invention, and FIG. 3 is a schematic diagram of a pixel 16 of the display 100 of FIG. 2. The display 100 includes a plurality of data lines S ₁ to S _P , a plurality of scanning lines G ₁ to G _M , a pixel array 110 , at least one source driving circuit 120 , and a gate driving circuit 130 , and the pixel array 110 includes a plurality of pixels Picture 16. Wherein, both P and M are integers greater than one. In the present embodiment, the display 100 employs a technique of memory pixels (MIP), each of which has a memory unit 18 and a pixel capacitance C _P . The memory unit 18 is coupled to the pixel capacitor C _P, D _P to the pixel data from said plurality of data lines S ₁ to S _P of a data line S _x wherein receiving and storing pixel data D _P received. In this way, the pixel 16 can perform polarity conversion on the pixel capacitor C _P according to the pixel data D _P stored in the memory unit 18. Therefore, when the gray scale to be displayed by the pixel 16 is unchanged, the pixel 16 does not need to receive the new pixel data D _P from the source driving circuit 120, but can be based on the pixel data D _P stored in the memory unit 18. The polarity of the pixel capacitor C _P is converted.

Please refer to FIG. 4 and FIG. 5, FIG. 4 is a circuit diagram of the gate driving circuit 130A according to an embodiment of the present invention, and FIG. 5 is a timing chart of the gate driving circuit 130A of FIG. The gate drive circuit 130A includes a logic control circuit 140A and M latch circuits 160. Where M is an integer greater than 1, and in the present embodiment M = 8. It will be appreciated that in other embodiments of the invention, M may be other positive integers greater than one, the size of which depends on the number of scan lines of the display to be driven. Further, the control logic circuit 140A is coupled to the scan lines G ₁ to _{G. 8,} according to the time and the clock signal CK based contain three bits D0, D1 and D2 of the digital signal, the scan lines G ₁ to _{G's. 8} wherein a voltage level of the scanning line by the first voltage into a second voltage level VGL level VGH, and the voltage level of the scanning lines in the other of ₈ scan lines G ₁ to G as the first voltage level VGL . For example, when the bits D0, D1 and D2 are "0", "0", "0", the voltage level of the scanning line G ₁ will be the second voltage level into a first voltage level by the VGL VGH, and the voltage levels of the other scanning lines G ₂ to G ₈ will be the first voltage level VGL; for example, when the bits D0, D1, and D2 are "1", "0", and "0", respectively. , the voltage level of the scanning line G ₁ will be converted by the first voltage level VGL second voltage level VGH, and the other scan lines G _1, G G voltage _{level. 3} to ₈ will be the first voltage level VGL; as another example, when the bits D0, D1 and D2 are "0", "1", "0", the voltage level of the scanning lines G ₃ will be converted into a second voltage level of a first voltage level by the VGL Bit VGH, and the voltage levels of the other scan lines G ₁ , G ₂ , G ₄ to G ₈ will be the first voltage level VGL; the rest can be deduced by analogy. The different combinations of the values of the bits D0, D1, and D2 and the corresponding scan lines to be driven can be referred to Table 1 below.

In this embodiment, the first voltage level VGL is a gate low potential, and the second voltage level VGH is a gate high potential, but the invention is not limited thereto. In addition, each latch circuit 130A of the gate driving circuit 160 is coupled to the control logic circuit 140A and the scanning lines G ₁ to _{G. 8} corresponding to a scanning line to the voltage level corresponding to the scanning line is in the first when a voltage level VGL, the voltage level of the latch (lATCH) scanning lines corresponding thereto, in order to avoid unintended changes due to a voltage level of the scanning lines G ₁ to G _8, and 16 of the pixel unintended Drive. Regarding the manner of operation of the latch circuit 160, further explanation will be given below.

In this embodiment, the clock signal CK is raised from the first voltage level VGL to the second voltage level VGH in each clock cycle T, and then decreased to the first voltage level by the second voltage level VGH. VGL. In addition, the value of the bit D0 is switched every other clock cycle T (switching from "0" to "1" or "1" to "0"), and the value of the bit D1 is every two o'clock. The pulse period T (i.e., 2T) is switched once, and the value of the bit D2 is switched every four clock cycles T (i.e., 4T). According to the waveform of FIG. 5, the voltage level of the bit D0 is switched from the first voltage level VGL to the second voltage level VGH every other clock period T, or is switched by the second voltage level VGH. Up to the first voltage level VGL; the voltage level of the bit D1 is switched to the second voltage level VGH by the first voltage level VGL every two clock cycles T (ie, 2T), or by the second voltage The level VGH is switched to the first voltage level VGL; and the voltage level of the bit D2 is switched to the second voltage level VGH from the first voltage level VGL every four clock cycles T (ie, 4T). Or switching from the second voltage level VGH to the first voltage level VGL. In this way, the voltage levels of the scan lines G ₁ to G ₈ can be sequentially increased to the second voltage level VGH. Therefore, the gate driving circuit 130A can generate the scanning line signal at the same timing as the gate driver having the shift register, so that the gate driving circuit 130A is suitable for driving a general liquid crystal display. . In addition, also by controlling the three bits D0, D1 and D2, the value of the scanning lines G ₁ to G ₈ in a voltage level of some specific scanning line is the second voltage level VGH, to be coupled to ground The pixel 16 of this particular scan line is driven, so the gate drive circuit 130A is also suitable for driving a display using memory pixel (MIP) technology.

Referring again to FIG. 4, in this embodiment, the logic control circuit 140A is controlled by the package. The digital signal includes three bits D0, D1, and D2, and the logic control circuit 140A includes three stages of circuits of the first stage circuit 152, the second stage circuit 154, and the third stage circuit 156. The first stage circuit 152, the second stage circuit 154 and the third stage circuit 156 each comprise a plurality of switch modules 150, and the switch module 150 of each stage circuit is controlled by three bits D0, D1, D2. A corresponding bit. In detail, the two switch modules 150 included in the first stage circuit 152 are controlled by the bit D2, and the four switch modules 150 included in the second stage circuit 154 are controlled by the bit D1, and the third stage The eight switch modules 150 included in circuit 154 are controlled by bit D2. The second stage circuit 154 is coupled between the first stage circuit 152 and the third stage circuit 156. In addition, the clock signal CK is input to the logic control circuit 140A by the input terminal 144 of the logic control circuit 140A. Each switch module 150 of the first stage circuit 152 is coupled to the input terminal 144 and the fourth stage circuit 154. Two switch modules 150 in the switch module 150. Each switch module 150 of the second stage circuit 154 is coupled to one of the two switch modules 150 of the first stage circuit 152 and four of the eight switch modules 150 of the third stage circuit 156. Switch module 150.

In an embodiment of the invention, the first stage circuit 152, the second stage circuit 154, and the third The stage circuits 156 can each include an inverter 142 for inverting corresponding bits received by the stages of the circuit to output the inverse phase elements of the corresponding bits. In particular, the inverter 142 of the first stage circuit 152 is used to invert the bit D2 to output the inverse phase element of the bit D2; the inverter 142 of the second stage circuit 154 The pixel D1 is inverted to output the inverse phase element of the bit D1; and the inverter 142 of the third stage circuit 156 is used to invert the bit D0 to output the inverse phase element of the bit D0. . In addition, each switch module 150 can include a first switch P1 and a second switch N1, and the first switch P1 and the second switch N1 are controlled by a corresponding bit of the digital signal and an inverse phase of the corresponding bit. yuan. In detail, each of the switch modules 150 of the first stage circuit 152 has its first switch P1 and the second switch N1 controlled by the inverse phase elements of the bit D2 and the bit D2, respectively; each of the second stage circuits 154 The first switch P1 and the second switch N1 of a switch module 150 are respectively controlled by the reverse phase elements of the bit D1 and the bit D1; the first switch P1 of each switch module 150 of the third stage circuit 156 is The second switch N1 is controlled by the bit phase D0 and the inverse phase element of the bit D0, respectively. In the present embodiment, the first switch P1 is a P-type transistor (for example, a P-type thin film transistor), and the second switch N1 is an N-type transistor (for example, an N-type thin film transistor).

According to the circuit structure and control mode of the logic control circuit 140A, the display For each doubling of the resolution, each circuit of the logic control circuit 140A for controlling the voltage level of the scan line only needs to add another switch module 150. Therefore, compared with the conventional decoder circuit 10 and the logic gate 14 need to use six transistors, each switch module 150 of the logic control circuit 140A only needs to use two transistors, so the logic control circuit The 140A's wiring is simpler and the required wiring area is smaller.

Please refer to FIG. 6 and FIG. 7. FIG. 6 is a circuit diagram of a gate driving circuit 130B according to another embodiment of the present invention, and FIG. 7 is a timing chart of the gate driving circuit 130B of FIG. The gate drive circuit 130B includes a logic control circuit 140B and M latch circuits 160. Where M is an integer greater than 1, and in the present embodiment M = 8. It should be understood that M can be other positive integers greater than one, and the size depends on the number of scan lines of the display to be driven. Similarly to the logic control circuit 140A, the logic control circuit 140B is also coupled to the scan lines G ₁ to G ₈ for making the scan line according to the clock signal CK and the digital signal including the three bits D0, D1 and D2. voltage _{level. 8} G ₁ to one of the scan lines G from the first into the second voltage level VGL voltage level VGH, and the voltage level of the scanning lines G ₁ to G other scanning _{lines. 8} It is the first voltage level VGL. For example, when the bits D0, D1 and D2 are "0", "0", "0", the voltage level of the scanning line G ₁ will be the second voltage level into a first voltage level by the VGL VGH, and the voltage levels of the other scanning lines G ₂ to G ₈ will be the first voltage level VGL. Please also refer to Figures 7 and 5. In the present embodiment, the timing chart of the gate driving circuit 130B is completely identical to the timing chart of the gate driving circuit 130A. In other words, when the clock signal CK based and contains three bits basis D0, D1 and D2 of the digital signal, the gate driving circuit 130B can scan lines G ₁ to G ₈ voltage levels sequentially lifted to a second voltage level Bit VGH. In addition, also by controlling the three bits D0, D1 and D2, the value of the gate driving circuit 130B scan lines G ₁ to G ₈ in a voltage level of some specific scanning line is the second voltage level VGH is driven by a pixel 16 coupled to the particular scan line, so the gate drive circuit 130B is also suitable for driving a display using memory pixel (MIP) technology. Therefore, the values of the scanning lines and the corresponding bit elements D0, D1, and D2 driven by the gate driving circuit 130B can also be referred to Table 1 above. Further, the function of the latch circuit 160 in the gate driving circuit 130B is the same as that in the gate driving circuit 130A, and the operation of the latch circuit 160 will be described in the following description.

Please refer to FIG. 6, in this embodiment, it is controlled by the logic control circuit 140B comprises three bits D0, D1 and D2 of the digital signal, and the scan lines G ₁ to _{G. 8} is coupled to each scan line The three switch modules 150 of the logic control circuit 140B, and each of the three switch modules 150 are controlled by different bits of the digital signal. When the voltage level of any one of the scan lines is changed from the first voltage level VGL to the second voltage level VGH, the three switch modules 150 coupled to the scan line are turned on to enable the clock signal CK. The three switch modules 150 coupled to the scan line are transferred to the scan line. For example, the three switch modules 150 to which the scan line G ₁ is coupled are controlled by the bits D0, D1, and D2, respectively. When the bits D0, D1 and D2 are "0", the scanning line G ₁ is coupled to three switch module 150 will be turned on, the clock signal CK via the scan lines G ₁ is coupled to the three switches module 150 transmits to the scan line G _1. In addition, in other embodiments of the present invention, the three bits D0, D1, and D2 are first subjected to inversion processing to generate inverse phase elements /D0, /D1, and /D2 of the bits D0, D1, and D2. Each of the switch modules 150 may include a first switch P1 and a second switch N1, and the first switch P1 and the second switch N1 are controlled by a corresponding bit of the digital signal and an inverse phase element of the corresponding bit .

According to the circuit structure and control mode of the logic control circuit 140B in FIG. Each time the resolution of the display is doubled, each circuit of the logic control circuit 140B for controlling the voltage level of the scan line only needs to add another switch module 150. Therefore, compared with the conventional decoder circuit 10 and the logic gate 14 need to use six transistors, each switch module 150 of the logic control circuit 140B only needs to use two transistors, so the logic control circuit The 140B's wiring is simpler and the required wiring area is smaller.

The mode of operation of the latch circuit 160 described above will be described below in terms of various embodiments. Please refer to FIG. 8. FIG. 8 is a circuit diagram of a latch circuit 160A according to an embodiment of the present invention. Input terminal of the latch circuit 160A is IN is coupled to the logic control circuit 140A or 140B, and the output terminal of the latch circuit 160A is coupled to the display 100 a plurality of scan lines G ₁ to G _M of the scan line G _y, where y Is an integer and 1≦y≦M. The latch circuit 160A includes a capacitor C1 and two switches P2 and N2. In the present embodiment, the switches P2 and N2 may be a P-type transistor (for example, a P-type thin film transistor) and an N-type transistor (for example, an N-type thin film transistor). For the sake of convenience of explanation, it is assumed here that the scanning line G _y is the scanning line G ₁ of the first strip, that is, y=1. Please refer to Figure 8 and refer to Table 1 and Figure 5 or Figure 7 at the same time. During the period t1, since the bits D0, D1, and D2 are all "0", the clock signal CK is input to the latch circuit 160A from the input terminal IN. At this time, since the voltage level of the clock signal CK is the first voltage level VGL, the switches P2 and N2 are turned on, so that both ends of the capacitor C1 are biased by the first voltage level VGL.

During the period t2, since the bits D0, D1, and D2 are all "0", the clock signal CK is input to the latch circuit 160A from the input terminal IN. In addition, since the voltage level of the clock signal CK is the second voltage level VGH, the switches P2 and N2 are turned off. At this time, the voltage level of the scanning line G ₁ is the second voltage level VGH, and the capacitor C1 is charged by the bias of the first voltage level VGL and the second voltage level VGH.

During the period t3, since the bits D0, D1, and D2 are all "0", the clock signal CK It will be input to the latch circuit 160A by the input terminal IN. At this time, since the voltage level of the clock signal CK is the first voltage level VGL, the switches P2 and N2 are turned on, so that the capacitor C1 is discharged due to the bias of the first voltage level VGL at both ends thereof. .

During the period t4, since the bit D0 is "1", the electrical connection between the input terminal IN and the logic control circuit 140A or 140B is cut off, so that the clock signal CK cannot be input to the latch via the input terminal IN. Circuit 160A. At this time, because the voltage level of the clock signal CK of a first voltage level VGL, it switches P2 and N2 will be turned on, so that the scanning lines G ₁ is biased to a first voltage level VGL is, the scanning line G The voltage level of ₁ is latched at the first voltage level VGL.

During the period t5, since the bit D0 is "1", the electrical connection between the input terminal IN and the logic control circuit 140A or 140B is cut off, so that the clock signal CK cannot be input to the latch via the input terminal IN. Circuit 160A. At this time, due to voltage levels of the clock signal CK to the second level voltage VGH, it will close switches P2 and N2, the scanning lines G ₁ in a floating state.

During the period t6, since the bit D0 is "1", the electrical connection between the input terminal IN and the logic control circuit 140A or 140B is cut off, so that the clock signal CK cannot be input to the latch via the input terminal IN. Circuit 160A. At this time, because the voltage level of the clock signal CK of a first voltage level VGL, it switches P2 and N2 will be turned on, so that the scanning lines G ₁ is biased to a first voltage level VGL is, the scanning line G The voltage level of ₁ is latched at the first voltage level VGL.

Please refer to FIG. 9. FIG. 9 is a circuit diagram of a latch circuit 160B according to another embodiment of the present invention. A latch circuit 160B is coupled to the input terminal IN logic control circuit 140A or 140B, 160B of the latch circuit and an output terminal coupled to the display 100 a plurality of scan lines G ₁ to G _M of the scan line G _y. The latch circuit 160B includes a resistor R. One end of the resistor R is coupled to the scan line G _y , and the other end of the resistor R is biased by the first voltage level VGL . The resistor R has a very large resistance value (generally between 400KΩ and 600KΩ), so when the pulse signal CK is input to the latch circuit 160B via the input terminal IN, and the voltage level of the clock signal CK is the second voltage level VGH. The voltage level of the scan line G _y is converted to the second voltage level VGH, and the current flowing through the resistor R is not excessive. In addition, when the electrical connection between the input terminal IN and the logic control circuit 140A or 140B is cut off, the scan line G _y is biased by the resistor R and subjected to the bias of the first voltage level VGL, thereby making the scan line at this time. The voltage level of G _y is latched at the first voltage level VGL.

Please refer to FIG. 10, which is a circuit diagram of a latch circuit 160C according to still another embodiment of the present invention. The latch circuit 160C is coupled to the input terminal IN logic control circuit 140A or 140B, and the output terminal of the latch circuit 160C, the display 100 is coupled to a plurality of scan lines G ₁ to G _M of the scan line G _y. The latch circuit 160C includes a capacitor C1, an inverter 162, and switches P2, P3, N2, and N3. In the present embodiment, the switches P2 and P3 are P-type transistors (for example, P-type thin film transistors), and the switches N2 and N3 are N-type transistors (for example, N-type thin film transistors). When the pulse signal CK is input to the latch circuit 160B via the input terminal IN, and the voltage level of the clock signal CK is the second voltage level VGH, the voltage level of the scan line G _y is converted to the second voltage level. VGH. When the electrical connection between the input terminal IN and the logic control circuit 140A or 140B is cut off, the capacitor C1 discharges, and the voltage level of the scan line G _y is lowered to the first voltage level VGL, so that the switch P3 is turned on, thereby enabling the scanning line G _y is biased to a first voltage level VGL. At this time, the inverter 162 outputs a high potential, and the switch N3 is also turned on. In addition, when the voltage level of the pulse signal CK is the first voltage level VGL, the switches P2 and N2 are turned on. Therefore, when the electrical connection between the input terminal IN and the logic control circuit 140A or 140B is cut off, the voltage level of the scan line G _y is latched at the first voltage level VGL.

Please refer to FIG. 11. FIG. 11 is a circuit diagram of a latch circuit 160D according to an embodiment of the present invention. Input terminal of the latch circuit 160D of IN is coupled to the logic control circuit 140A or 140B, and the output terminal of the latch circuit 160D is coupled to the display 100 a plurality of scan lines G ₁ to G _M of the scan line G _y, where y Is an integer and 1≦y≦M. The latch circuit 160D includes a capacitor C1, three inverters 162, 164, and 166, and a plurality of switches P2 to P6 and N2 to N6. In the present embodiment, the switches P2 to P6 are P-type transistors (for example, P-type thin film transistors), and the switches N2 to N6 are N-type transistors (for example, N-type thin film transistors). For the sake of convenience of explanation, it is assumed here that the scanning line G _y is the scanning line G ₁ of the first strip, that is, y=1. Please refer to Figure 11 and refer to Table 1 and Figure 5 or Figure 7 at the same time. During the period t1, since the bits D0, D1, and D2 are all "0" and /D0 is "1", the clock signal CK is input from the input terminal IN to the latch circuit 160A, and the switches P3 and N4 are Turn on, and switches P5 and N6 are off. At this time, since the voltage level of the clock signal CK is the first voltage level VGL, the switches P2, N2, and P4 are turned on, and the switch N3 is turned off, so that both ends of the capacitor C1 are subjected to the first voltage level VGL. The bias voltage, and the voltage level at the input of the inverter 164 is the second voltage level VGH due to the opening of the switches P3 and P4, and causes the switch P6 to be turned on and the switch N5 to be turned off. Since the switches P2 and N2 are turned on, the voltage level of the input terminal of the inverter 164 is the second voltage level VGH, and the input of the scan line G _y is because the voltage level of the clock signal CK is the first voltage level VGL. The voltage level of the terminal is the first voltage level VGL.

During the period t2, since the bits D0, D1, and D2 are all "0" and /D0 is "1", the clock signal CK is input from the input terminal IN to the latch circuit 160A, and the switches P3 and N4 are Turn on, and switches P5 and N6 are off. At this time, since the voltage level of the clock signal CK is the second voltage level VGH, the switches P2, N2, and P4 are turned off, and the switch N3 is turned on, so that the capacitor C1 is respectively subjected to the second voltage level due to its two ends. VGH is charged with the bias of the first voltage level VGL, and the voltage level of the input terminal of the inverter 164 is the first voltage level VGL due to the opening of the switches N3 and N4, and the switch N5 is turned on and the switch P6 is turned off. . Since the voltage level of the input terminal of the inverter 164 is the first voltage level VGL, the voltage level of the input end of the scan line G _y is the second voltage level VGH.

During the period t3, since the bits D0, D1 and D2 are both "0" and /D0 is "1", the clock signal CK is input from the input terminal IN to the latch circuit 160A, and the switches P3 and N4 will Turn on, and switches P5 and N6 are off. At this time, since the voltage level of the clock signal CK is the first voltage level VGL, the switches P2, N2, and P4 are turned on, and the switch N3 is turned off, so that the capacitor C1 is subjected to the first voltage level because both ends thereof. The bias voltage of the VGL is discharged, and the voltage level at the input of the inverter 164 is the second voltage level VGH due to the opening of the switches P3 and P4, and causes the switch P6 to be turned on and the switch N5 to be turned off. Since the switches P2 and N2 are turned on, the voltage level of the input terminal of the inverter 164 is the second voltage level VGH, and the input of the scan line G _y is because the voltage level of the clock signal CK is the first voltage level VGL. The voltage level of the terminal is the first voltage level VGL.

During the period t4, since the bit D0 is "1" and /D0 is "0", the electrical connection between the input terminal IN and the logic control circuit 140A or 140B is cut off, so that the clock signal CK cannot be passed. The input terminal IN is input to the latch circuit 160D. In addition, since /D0 is "0", switches P5 and N6 are turned on, and switches P3 and N4 are turned off. In addition, due to the action of the capacitor C1, the voltage level of the input terminal IN is maintained at the first voltage level VGL, so that the switch P4 is turned on and the switch N3 is turned off. At this time, because the voltage level of the clock signal CK of a first voltage level VGL, it switches P2 and N2 will be turned on, so that the scanning lines G ₁ is biased to a first voltage level VGL is turned on and causes the switch P6 The switch N5 is turned off. P5 and P6 is turned on by the switch, so the input terminal of the inverter 164 will be biased to a second voltage level VGH, the output of the inverter 164 is a first voltage level VGL, so the voltage of the scan line G ₁ Quasi The bit is latched at the first voltage level VGL.

During the period t5, since the bit D0 is "1" and /D0 is "0", the electrical connection between the input terminal IN and the logic control circuit 140A or 140B is cut off, so that the clock signal CK cannot be passed. The input terminal IN is input to the latch circuit 160D. In addition, since /D0 is "0", switches P5 and N6 are turned on, and switches P3 and N4 are turned off. In addition, due to the action of the capacitor C1, the voltage level of the input terminal IN is maintained at the first voltage level VGL, so that the switch P4 is turned on and the switch N3 is turned off. At this time, since the voltage level of the clock signal CK is the first voltage level VGL, the switches P2 and N2 are turned off, and the switch P6 is turned on and the switch N5 is turned off. P5 and P6 is turned on by the switch, so the input terminal of the inverter 164 will be biased to a second voltage level VGH, the output of the inverter 164 is a first voltage level VGL, so the voltage of the scan line G ₁ Quasi The bit is latched at the first voltage level VGL.

During the period t6, since the bit D0 is "1", /D0 is "0", and the voltage level of the clock signal CK is the first voltage level VGL, the operation mode of the latch circuit 160D and the time period t6 at this time. as the operation mode in a period, the voltage level of the scanning line G ₁ is latched in the first level voltage VGL.

Since the latch circuits 160A to 160B are at the first voltage level VGL when the voltage level of the scan line scan line G _y is at the first voltage level VGL, the voltage level of the scan line G _y is latched, so that the scan line can be avoided. The voltage level of G _y produces an unexpected change, while the pixel 16 is driven unintended. Therefore, the image quality of the display 100 can be further ensured.

In summary, since the display of the present invention and its gate driving circuit adopt a new circuit structure, each time the resolution of the display is doubled, each of the gate driving circuits is used to control the voltage level of the scanning line. The circuit only needs to add two more transistors. Therefore, the logic control circuit of the gate driving circuit of the present invention has a simpler wiring pattern and a required wiring area than the use of six transistors for each AND gate logic gate of the conventional decoding circuit. It will be smaller. In addition, since the latch circuit of the gate driving circuit of the present invention latches the voltage level of the scan line when the voltage level of the scan line is at the first voltage level, the voltage level of the scan line can be avoided. The bit produces unintended changes that ensure the image quality of the display.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

130A‧‧‧Gate drive circuit

140A‧‧‧Logic Control Circuit

142‧‧‧Inverter

144‧‧‧ input

150‧‧‧Switch Module

152‧‧‧First stage circuit

154‧‧‧Second stage circuit

156‧‧‧ third-level circuit

160‧‧‧Latch circuit

D0, D1, D2‧‧‧ bits

CK‧‧‧ clock signal

G ₁ to G ₈ ‧‧‧ scan line

P1‧‧‧ first switch

N1‧‧‧ second switch

Claims (8)

A gate driving circuit includes: a logic control circuit coupled to the M scan lines for causing a voltage level of one of the scan lines to be based on a digital signal and a clock signal a voltage level is converted to a second voltage level, and the voltage levels of the other scan lines in the scan lines are the first voltage level, where M is an integer greater than 1; and M latches a latch circuit coupled to the logic control circuit and a corresponding one of the scan lines for latching when a voltage level of the corresponding scan line is at the first voltage level Locking the voltage level of the scan line corresponding to the strip; wherein: the digit signal is a N-bit digital signal, N is an integer greater than 1, and each scan line is coupled to the N switch modules of the logic control circuit And the N switch modules are controlled by different bits of the digital signal; and the clock signal is input to the logic control circuit by an input of the logic control circuit, and when there is any scan line voltage The level is changed from the first voltage level to the When the voltage level is two, the N switch modules coupled to any one of the scan lines are turned on, so that the clock signal is transmitted to the any one of the N switch modules coupled by any one of the scan lines. Scan line. A gate driving circuit includes: a logic control circuit coupled to the M scan lines for causing a voltage level of one of the scan lines to be based on a digital signal and a clock signal a voltage level is converted to a second voltage level, and the voltage levels of the other scan lines in the scan lines are the first voltage level, where M is an integer greater than 1; and M latches a circuit, each latch circuit is coupled to the logic control circuit and the scan lines a corresponding scan line for latching the voltage level of the corresponding scan line when the voltage level of the corresponding scan line is at the first voltage level; wherein the digital signal is N bits The digital signal, N is an integer greater than 1, the logic control circuit comprises an N-level circuit, wherein each of the N-level circuits comprises a plurality of switch modules, and the switch modules of each stage circuit are subjected to Controls a corresponding bit in the digital signal. The gate driving circuit of claim 2, wherein the clock signal is input to the logic control circuit by an input terminal of the logic control circuit; wherein the first stage circuit of the N-stage circuit comprises two switching modes The second-stage circuit of the N-stage circuit includes four switch modules, and the third-stage circuit of the N-stage circuit includes eight switch modules, and the second-stage circuit is coupled to the first-stage circuit And the third stage circuit; wherein each switch module of the first stage circuit is coupled to the input end of the logic control circuit and two switch modes of the four switch modules of the second stage circuit Each of the switch modules of the second-stage circuit is coupled to one of the two switch modules of the first-stage circuit and four of the eight switch modules of the third-stage circuit Switch module. The gate driving circuit of claim 1, 2 or 3, wherein each of the switch modules includes a first switch and a second switch, and the first switch and the second switch of each switch module are controlled A corresponding bit in the digital signal and an inverse phase element of the corresponding bit. The gate driving circuit of claim 1, 2 or 3, wherein each latch circuit comprises: a switching element coupled to a corresponding scan line and a system voltage, and controlled by the clock signal; as well as A capacitor is coupled between the corresponding scan line and a bias voltage. The gate driving circuit of claim 1, 2 or 3, wherein each of the latch circuits includes a resistor coupled between a corresponding scan line and a bias voltage. A display comprising: a plurality of data lines; a plurality of scan lines; a plurality of pixels, each of the pixels being coupled to a corresponding data line and a corresponding scan line; at least one source driving circuit coupled And the data lines for transmitting the data signals to the pixels by the data lines; and the gate driving circuit of claim 1, 2 or 3. The display device of claim 7, wherein each of the pixels has a memory unit and a pixel capacitor, and the memory unit is coupled to the pixel capacitor for receiving from one of the data lines of the data lines. a pixel data and storing the pixel data to perform polarity conversion on the pixel capacitor according to the pixel data stored in the memory unit.