CN106128378B

CN106128378B - Shift register unit, shift register and display panel

Info

Publication number: CN106128378B
Application number: CN201610490981.1A
Authority: CN
Inventors: 蓝学新; 胡胜华; 朱绎桦
Original assignee: Tianma Microelectronics Co Ltd; Xiamen Tianma Microelectronics Co Ltd
Current assignee: Tianma Microelectronics Co Ltd; Xiamen Tianma Microelectronics Co Ltd
Priority date: 2016-06-28
Filing date: 2016-06-28
Publication date: 2020-01-07
Anticipated expiration: 2036-06-28
Also published as: CN106128378A

Abstract

The application discloses a shift register unit, a shift register and a display panel. The shift register unit comprises a latch, wherein the latch comprises a first clock signal input end, a second clock signal input end, an input signal end, a first transistor, a second transistor, a first inverter and a second inverter; the grid electrode of the first transistor is connected with the input end of a first clock signal, the first pole of the first transistor is connected with the input signal end, and the second pole of the first transistor is connected with the input end of the first phase inverter; the grid electrode of the second transistor is connected with the input end of the second clock signal, the first pole of the second transistor is connected with the second pole of the first transistor, and the second pole of the second transistor is connected with the output end of the second inverter; the output end of the first phase inverter is connected with the input end of the second phase inverter, and the output end of the second phase inverter is connected with the output end of the latch; the channel type of the first transistor and the second transistor is the same. The embodiment is beneficial to reducing the size of the frame of the display panel.

Description

Shift register unit, shift register and display panel

Technical Field

The application relates to the technical field of display, in particular to a shift register unit, a shift register and a display panel.

Background

In one conventional design of a display panel, a pixel array, a plurality of gate lines, and data lines crossing the gate lines in an insulating manner may be disposed on a central region of the display panel. And a grid driving circuit for driving the grid lines to scan can be arranged in the frame range of the display panel. The gate driving circuit generally includes a plurality of cascaded shift register units. The frame of the lcd is becoming narrower and narrower, and the width of the frame is determined by the number and size of the circuit elements in the shift register unit.

Fig. 1 is a schematic circuit diagram of a shift register unit of the prior art, in fig. 1, the shift register unit 100 includes two clock signal input terminals CK11 and CK12, a high level signal input terminal Vgh1, a low level signal input terminal Vgl1, a shift signal input terminal Stv11, a shift signal output terminal Next1, a Reset signal terminal Reset1, a gate driving signal output terminal Gout1, a latch 111, a nand gate 112, and a buffer circuit 113. The latch 11 includes 12 TFTs (Thin Film transistors) for shifting the shift signal input terminal Stv11 under the control of signals input from the clock signal input terminal CK11, the high-level signal input terminal Vgh1, and the low-level signal input terminal Vgl1, and outputting the shifted signal to the shift signal output terminal Next1, and the nand gate 112 and the buffer circuit 113 are used for converting the signal output from the shift signal output terminal Next1 and outputting a gate driving signal to the gate driving signal output terminal Gout 1. Due to the large number of shift register unit TFTs, it is difficult to further reduce the size of the display frame.

Disclosure of Invention

In order to solve the above technical problem, the present application provides a shift register unit, a shift register and a display panel.

In a first aspect, the present application provides a shift registering unit, including a latch, the latch including a first clock signal input terminal, a second clock signal input terminal, an input signal terminal, a first transistor, a second transistor, a first inverter, and a second inverter; a gate of the first transistor is connected to the first clock signal input terminal, a first pole of the first transistor is connected to the input signal terminal, and a second pole of the first transistor is connected to the input terminal of the first inverter; the grid electrode of the second transistor is connected with the second clock signal input end, the first pole of the second transistor is connected with the second pole of the first transistor, and the second pole of the second transistor is connected with the output end of the second inverter; the output end of the first phase inverter is connected with the input end of the second phase inverter, and the output end of the second phase inverter is connected with the output end of the latch; the channel type of the first transistor and the second transistor is the same.

In a second aspect, the present application provides a shift register, which includes N cascaded shift register units as described above, where N is a positive integer.

In a third aspect, the present application provides a display panel, which includes a plurality of scan lines and the shift register, where an output terminal of each stage of shift register unit in the shift register is connected to one scan line.

The shift register unit, the shift register and the display panel realize shift output of grid signals through a small number of transistors, simplify the circuit structure of the shift register unit, reduce power consumption of the shift register and facilitate design of narrow frames.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, with reference to the accompanying drawings in which:

FIG. 1 is a schematic circuit diagram of a shift register unit according to the prior art;

FIG. 2 is a circuit diagram of an embodiment of a latch in a shift register unit;

FIG. 3 is a circuit diagram of another embodiment of a latch in a shift register unit;

FIG. 4 is a circuit diagram of one embodiment of a shift register cell including the latch of FIG. 2;

FIG. 5 is a circuit diagram of another embodiment of a shift register cell including the latch of FIG. 2;

FIG. 6 is a circuit diagram of one embodiment of a shift register cell including the latch of FIG. 3;

FIG. 7 is a circuit diagram of another embodiment of a shift register cell including the latch of FIG. 3;

FIG. 8 is a timing diagram illustrating an operation of a shift register unit according to an embodiment of the present disclosure;

FIG. 9 is a schematic diagram of an embodiment of a shift register provided herein;

fig. 10 is a schematic structural diagram of another embodiment of a shift register provided in the present application.

Detailed Description

The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. It should be noted that, for convenience of description, only the portions related to the related invention are shown in the drawings.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

Referring to fig. 2, a circuit structure diagram of an embodiment of a latch in a shift register unit according to the present application is shown. As shown IN fig. 2, the latch 200 includes a first clock signal input terminal CK1, a second clock signal input terminal CK2, an input signal terminal IN, a first transistor M1, a second transistor M2, a first inverter R1, and a second inverter R2.

IN the latch 200, a gate of the first transistor M1 is connected to the first clock signal input terminal CK1, a first pole of the first transistor M1 is connected to the input signal terminal IN, and a second pole of the first transistor M1 is connected to the input terminal of the first inverter R1; a gate of the second transistor M2 is connected to the second clock signal input terminal CK2, a first pole of the second transistor M2 is connected to a second pole of the first transistor M1, and a second pole of the second transistor M2 is connected to an output terminal of the second inverter R2; the output of the first inverter R1 is connected to the input of the second inverter R2 and the output of the second inverter R2 is connected to the output Next of the latch 200. Wherein, the channel types of the first transistor M1 and the second transistor M2 are the same. In fig. 2, the first transistor M1 and the second transistor M2 are both N-type transistors for illustration, and in practical applications, the first transistor M1 and the second transistor M2 may also be both P-type transistors, which is not limited in this application.

IN the present embodiment, the first transistor M1 is turned on or off IN response to a signal input from the first clock signal input terminal CK1, and the first transistor M1 transfers a signal input from the input signal terminal IN to the input terminal of the first inverter R1 and the first pole of the second transistor M2 when turned on. The second transistor M2 is turned on or off in response to a signal inputted from the second clock signal input terminal CK2, and the second transistor M2 transfers a signal of the first pole of the second transistor M2 to the output terminal Next of the latch 200 when turned on. The first inverter R1 is used to invert the signal outputted from the second pole of the first transistor M1 and output the inverted signal to the input terminal of the second inverter R2, and the second inverter R2 is used to invert the signal outputted from the first inverter R1 and output the inverted signal to the output terminal Next of the latch 200, so as to realize the latch of the signal inputted from the input signal terminal IN.

Alternatively, the first clock signal input terminal CK1 is used for inputting a first signal, the second clock signal input terminal CK2 is used for inputting a second signal, and the input signal terminal IN is used for inputting a single pulse signal. The first signal and the second signal are clock signals with the same period, and the duty ratios of the first signal and the second signal are equal.

Further, the first inverter R1 may include a fourth transistor M24 and a fifth transistor M25. Wherein the gate of the fourth transistor M24 and the gate of the fifth transistor M25 are connected to each other to form the input terminal of the first inverter R1, and the second poles of the fourth transistor M24 and the fifth transistor M25 are connected to each other to form the output terminal of the first inverter R1; the fourth transistor M24 and the fifth transistor M25 are respectively one of an N-type transistor and a P-type transistor, and have different channel types. First electrodes of P-type transistors of the fourth transistor M24 and the fifth transistor M25 are connected to the first voltage signal input terminal Vgh, and first electrodes of N-type transistors of the fourth transistor M24 and the fifth transistor M25 are connected to the second voltage signal input terminal Vgl. In fig. 2, the fourth transistor M24 is a P-type transistor, and the fifth transistor M25 is an N-type transistor, wherein a first pole of the fourth transistor M24 is connected to the first voltage signal input terminal Vgh, and a first pole of the fifth transistor M25 is connected to the second voltage signal input terminal Vgl. The second inverter R2 and the first inverter R1 are similar in circuit structure and include two transistors having different channel types.

As can be seen from fig. 2, compared with the structure of the conventional shift register unit 100, the present embodiment simplifies the circuit structure of the latch 200 of the shift register unit, and reduces the number of transistors in the latch 200, so as to reduce the frame area occupied by the shift register unit, thereby facilitating the design of a narrow frame; meanwhile, the number of transistors in the shift register unit is reduced, so that the power consumption of the shift register can be reduced.

With continued reference to FIG. 3, a circuit diagram of another embodiment of a latch in a shift register cell is shown. As shown IN fig. 3, the latch 300 includes a first clock signal input terminal CK1, a second clock signal input terminal CK2, an input signal terminal IN, a first transistor M1, a second transistor M2, a first inverter R1, and a second inverter R2.

IN the latch 300, a gate of the first transistor M1 is connected to the first clock signal input terminal CK1, a first pole of the first transistor M1 is connected to the input signal terminal IN, and a second pole of the first transistor M1 is connected to the input terminal of the first inverter R1; a gate of the second transistor M2 is connected to the second clock signal input terminal CK2, a first pole of the second transistor M2 is connected to a second pole of the first transistor M1, and a second pole of the second transistor M2 is connected to an output terminal of the second inverter R2; the output of the first inverter R1 is connected to the input of the second inverter R2 and the output of the second inverter R2 is connected to the output Next of the latch 300. Wherein, the channel types of the first transistor M1 and the second transistor M2 are the same.

In this embodiment, the latch 300 further includes a third inverter R3. An input terminal of the third inverter R3 is connected to the first clock signal input terminal CK1, and an output terminal of the third inverter R3 is connected to the second clock signal input terminal CK 2.

The

latch

200 or 300 is in a signal transmission state when the first transistor M1 is controlled to be turned on by a signal inputted from the first clock signal input terminal CK1, and is converted into a latch state when the second transistor M2 is controlled to be turned on by a signal inputted from the second clock signal input terminal CK 2. Alternatively, the first clock signal input terminal CK1 is used for inputting a first signal, the second clock signal input terminal CK2 is used for inputting a second signal, and the input signal terminal IN is used for inputting a single pulse signal. The first signal and the second signal are clock signals with the same period, and the duty ratios of the first signal and the second signal are equal.

It can be seen from fig. 3 that, unlike the embodiment shown in fig. 2, the third inverter R3 controls the signals input from the first clock signal input terminal CK1 and the second clock signal input terminal CK2 to be inverted simultaneously in the embodiment shown in fig. 3, and the signal input from the second clock signal input terminal CK2 and the signal input from the first clock signal input terminal CK1 are inverted signals. Therefore, based on the example shown in fig. 2, the circuit structure of the latch 300 shown in fig. 3 can eliminate the influence on the stability of the circuit caused by the fact that the signal input from the second clock signal input terminal CK2 and the clock signal input from the first clock signal input terminal CK1 are not the same in the time of inversion, and ensure that no delay occurs when the latch 300 is switched from the transmission state to the latch state, so that the signal in the latch is more stable. In addition, after the third inverter is added, the source of the gate signal of the second transistor M2 is the constant voltage signal input by the first voltage signal input terminal Vgh in the inverter or the constant voltage signal input by the second voltage signal input terminal Vgl, and compared with the embodiment shown in fig. 2 in which the clock signal input by the second clock signal input terminal is used to directly control the on or off of the second transistor M2, the state of the second transistor M2 in this embodiment is more stable, thereby further improving the stability of the potential signal at the node where the second pole of the first transistor M1 is connected with the first pole of the second transistor M2.

In some embodiments, the shift register unit further includes a nand gate and a buffer circuit. The input end of the NAND gate is connected with the output end of the latch, and the output end of the NAND gate is connected with the input end of the buffer circuit. Referring to FIG. 4, a circuit diagram of an embodiment of a shift register unit including the latch of FIG. 2 is shown.

As shown in fig. 4, the shift register unit 400 includes a latch 200, a nand gate 410, and a buffer circuit 420. The input of the nand gate 410 is connected to the Next output of the latch 200, and the output of the nand gate 410 is connected to the input of the buffer circuit 420.

The buffer circuit 420 may include a fourth inverter R4, a fifth inverter R5, and a sixth inverter R6. Wherein, the input end of the fourth inverter R4 is connected with the input end of the buffer circuit 420, and the output end of the fourth inverter R4 is connected with the input end of the fifth inverter R5; the output end of the R5 of the fifth inverter is connected with the input end of the R6 of the sixth inverter; the output terminal of the sixth inverter R6 is connected to the output terminal Gout of the shift register unit.

The nand gate 410 may include a first input 411 and a second input 412. In comparison with fig. 3, the latch 200 shown in fig. 4 does not include the third inverter R3, the first input 411 of the nand gate 410 is connected to the output Next of the latch 200, and the second input 412 of the nand gate 420 is connected to the second clock input CK 2. The output 413 of the nand gate 410 is connected to the input of the fourth inverter R4.

As shown in FIG. 4, the shift register cell 400 further includes a first voltage signal input Vgh and a second voltage signal input Vgl. The first voltage signal input terminal Vgh is used to input a first voltage signal having a constant voltage value, and the second voltage signal input terminal Vgl is used to input a second voltage signal having a constant voltage value. Wherein the voltage values of the first voltage signal and the second voltage signal are not equal.

In fig. 4, the nand gate 410 performs a nand operation on the input signal, and outputs the nand operation on the signal output from the Next output terminal of the latch 200 and the signal input from the second clock signal input terminal CK2 to the buffer circuit 420. Specifically, the nand gate 410 may include a sixth transistor M46, a seventh transistor M47, an eighth transistor M48, and a ninth transistor M49. Wherein, the sixth transistor M46 and the seventh transistor M47 are P-type transistors, and the eighth transistor M48 and the ninth transistor M49 are N-type transistors. The gate of the sixth transistor M46 is connected to the first input 411 of the nand gate 410, the gate of the seventh transistor M47 is connected to the second input 412 of the nand gate 410, the first poles of the sixth transistor M46 and the seventh transistor M47 are both connected to the first voltage signal input Vgh, and the second poles of the sixth transistor M46 and the seventh transistor M47 are both connected to the output 413 of the nand gate 410. The gate of the eighth transistor M48 is connected to the first input terminal 411, the first pole of the eighth transistor M48 is connected to the second pole of the ninth transistor M49, the second pole of the eighth transistor M48 is connected to the output terminal 413 of the nand gate, the gate of the ninth transistor M49 is connected to the second input terminal 412, and the first pole of the ninth transistor M49 is connected to the second voltage signal input terminal Vgl. The signal at the output end 413 of the nand gate 410 is provided by the first voltage signal input end Vgh or the second voltage signal input end Vgl, so that the signal output by the nand gate 410 is stable and is not affected by the potential fluctuation when the clock signal is inverted.

The buffer circuit 420 can perform voltage stabilization, noise reduction, and other processing on the signal output by the nand gate 410, so as to enhance the driving capability of the shift register unit 400.

Further, the shift register unit 400 may further include a reset unit 430. The Reset unit 430 may include a first voltage signal input terminal Vgh, a Reset signal input terminal Reset, and a third transistor M43. The gate of the third transistor M43 is connected to the Reset signal input terminal Reset, the first pole of the third transistor M43 is connected to the first voltage signal input terminal Vgh, and the second pole of the third transistor M43 is connected to the output terminal of the first inverter R1. The third transistor M43 may be a P-type transistor or an N-type transistor (the third transistor M43 is a P-type transistor in fig. 4 as an example). When the third transistor M43 is turned on, the signal inputted from the first voltage signal input terminal Vgh is transmitted to the output terminal of the first inverter R1 and the input terminal of the second inverter R2, the second inverter R2 inverts the signal inputted from the first voltage signal input terminal Vgh and outputs a signal having an opposite potential to the output terminal of the latch 200, and when a high potential signal is inputted from the first voltage signal input terminal Vgh, the signal at the output terminal of the latch 200 is reset to a low potential signal.

In some alternative implementations, the Reset signal input Reset is used to input a Reset signal. The reset signal may include a pulse signal. When the third transistor M43 is a P-type transistor, the reset signal may be a pulse signal of a low level.

The display is generally used for displaying a plurality of consecutive frames of images, and the reset unit 430 may be used to reset the voltage level output by the output terminal of the latch 200 to a low voltage level when switching images of different frames, and the output terminal Gout of the shift register unit 400 outputs a gate driving signal with a low voltage level, so as to prevent the currently scanned image from being affected by the gate driving signal of the previous frame of image.

In other embodiments, the buffer circuit may include an inverter. FIG. 5 is a circuit diagram of another embodiment of a shift register cell including the latch of FIG. 2. As shown in fig. 5, the shift register unit 500 includes a latch 200, a nand gate 510, a buffer circuit 520, and a reset unit 530. The circuit structures of the nand gate 510 and the reset unit 530 are the same as those of the nand gate 410 and the reset unit 430 in the shift register unit shown in fig. 4, respectively. The buffer circuit 520 may include a seventh inverter R7, an input of the seventh inverter R7 is connected to the input of the buffer circuit 520, that is, to the output of the nand gate 510, and an output of the seventh inverter R7 is connected to the output Gout of the shift register unit 500. The circuit structure of the seventh inverter R7 may be the same as that of the first inverter R1 in the latch 200.

Compared with the embodiment shown in fig. 4, the shift register unit 500 shown in fig. 5 further reduces the number of transistors in the buffer circuit, further simplifies the circuit structure of the shift register unit, and can realize a narrower frame design.

With further reference to FIG. 6, a circuit diagram of one embodiment of a shift register cell including the latch of FIG. 3 is shown. As shown in fig. 6, the shift register unit 600 includes a latch 300, a nand gate 610, and a buffer circuit 620.

The buffer circuit 620 may include a fourth inverter R4, a fifth inverter R5, and a sixth inverter R6. Wherein, the input end of the fourth inverter R4 is connected with the input end of the buffer circuit 620, and the output end of the fourth inverter R4 is connected with the input end of the fifth inverter R5; the output end of the R5 of the fifth inverter is connected with the input end of the R6 of the sixth inverter; an output terminal of the sixth inverter R6 is connected to an output terminal Gout of the shift register unit 600.

The nand gate 610 may include a first input 611 and a second input 612. The latch 300 of FIG. 6 includes a third inverter R3, and in this case, the shift register cell 600 may further include a third clock signal input CK 3. The third clock signal input terminal CK3 is used for inputting a third signal, which is a clock signal having the same period and the same duty ratio as the first signal input to the first clock signal input terminal CK 1. The first input 611 of the nand-gate 610 is connected to the Next output of the latch 300, and the second input 612 of the nand-gate 610 is connected to the third clock input CK 3. The output 613 of the nand gate 610 is connected to the input of the fourth inverter R4.

As shown in FIG. 6, the shift register cell 600 further includes a first voltage signal input Vgh and a second voltage signal input Vgl. The first voltage signal input terminal Vgh is used to input a first voltage signal having a constant voltage value, and the second voltage signal input terminal Vgl is used to input a second voltage signal having a constant voltage value. Wherein the voltage values of the first voltage signal and the second voltage signal are not equal.

The buffer circuit 620 can perform voltage stabilization, noise reduction, and other processing on the signal output by the nand gate 610, so as to enhance the driving capability of the shift register unit 600.

Further, the shift register unit 600 may further include a reset unit 630. The Reset unit 630 may include a first voltage signal input terminal Vgh, a Reset signal input terminal Reset, and a third transistor M63. The gate of the third transistor M63 is connected to the Reset signal input terminal Reset, the first pole of the third transistor M63 is connected to the first voltage signal input terminal Vgh, and the second pole of the third transistor M63 is connected to the output terminal of the first inverter R1. The third transistor M63 may be a P-type transistor or an N-type transistor (the third transistor M63 is a P-type transistor in fig. 6 as an example). When the third transistor M63 is turned on, the signal inputted from the first voltage signal input terminal Vgh is transmitted to the output terminal of the first inverter R1 and the input terminal of the second inverter R2, the second inverter R2 inverts the signal inputted from the first voltage signal input terminal Vgh and outputs a signal having an opposite potential to the output terminal of the latch 300, and when a high potential signal is inputted from the first voltage signal input terminal Vgh, the signal at the output terminal of the latch 300 is reset to a low potential signal.

In some alternative implementations, the Reset signal input Reset is used to input a Reset signal. The reset signal may include a pulse signal. When the third transistor M63 is a P-type transistor, the reset signal may be a pulse signal of a low level.

The display is generally used for displaying continuous multi-frame images, and the reset unit 630 may be used to reset the potential outputted from the Next output terminal of the latch 300 to a low potential when switching images of different frames, and the output terminal Gout of the shift register unit 600 outputs a gate driving signal with a low potential, so as to prevent the currently scanned image from being affected by the gate driving signal of the previous frame image.

In other embodiments, the buffer circuit may include an inverter. FIG. 7 is a circuit diagram of another embodiment of a shift register cell including the latch of FIG. 3. As shown in fig. 7, the shift register unit 700 includes a latch 300, a nand gate 710, a buffer circuit 720, and a reset unit 730. The circuit structures of the nand gate 710 and the reset unit 730 are the same as the circuit structures of the nand gate 510 and the reset unit 530 in the shift register unit shown in fig. 5, respectively. The buffer circuit 720 may include a seventh inverter R77, an input of the seventh inverter R77 is connected to an input of the buffer circuit 720, that is, to an output of the nand gate 710, and an output of the seventh inverter R77 is connected to an output Gout of the shift register unit 700. The circuit structure of the seventh inverter R77 may be the same as that of the first inverter R1 in the latch 300.

Compared with the embodiment shown in fig. 6, the shift register unit 700 shown in fig. 7 further reduces the number of transistors in the buffer circuit, further simplifies the circuit structure of the shift register unit, and can realize a narrower frame design.

The shift register unit provided in the above embodiments of the present application can implement shift output of an input signal. The following describes a driving method of a shift register unit provided in an embodiment of the present application with reference to fig. 8.

FIG. 8 is a timing diagram illustrating the operation of the shift register unit 400 according to the embodiment shown in FIG. 4. The signals inputted from the input signal terminal IN, the first clock signal input terminal CK1, and the second clock signal input terminal CK2, and the signals outputted from the output terminal Next of the latch 200 and the output terminal Gout of the shift register unit 400 are shown.

In the first phase T1, when the first clock signal input terminal CK1 inputs a high level signal and the second clock signal input terminal CK2 inputs a low level signal, the first transistor M1 is turned on and the second transistor M2 is turned off. The first transistor M1 transmits a high level signal inputted from the input signal terminal IN to the second pole of the first transistor M1 and the first pole of the second transistor M2. The first and second inverters R1 and R2 invert the high level signal of the second pole of the first transistor M1 twice and output a high level signal to the output terminal Next of the latch 200. The nand gate 410 performs a nand operation on a high level signal output from the Next output terminal of the latch 200 and a low level signal input from the second clock signal input terminal CK2 to output a high level signal, and the buffer circuit 420 inverts the high level signal output from the nand gate 410 three times and outputs a low level signal to the output terminal Gout of the shift register unit 400.

In the second stage T2, the first clock signal input terminal CK1 inputs a low level signal, and the second clock signal input terminal CK2 inputs a high level signal, at which time the first transistor M1 is turned off and the second transistor M2 is turned on. The first pole of the second transistor M2 is maintained at the high level of the first stage T1, and the second transistor M2 transfers the high level signal of its first pole to the output Next of the latch 200. The nand gate 410 performs a nand operation on a high level signal output from the Next output terminal of the latch and a high level signal input from the second clock signal input terminal CK2 to output a low level signal, and the buffer circuit 420 performs a triple inversion on the low level signal output from the nand gate 410 and outputs a high level signal to the output terminal Gout of the shift register unit 400.

In the third stage, the first clock signal input terminal CK1 inputs a high level signal, and the second clock signal input terminal CK2 inputs a low level signal, at which time the first transistor M1 is turned on and the second transistor M2 is turned off. The first transistor M1 transmits a low level signal inputted from the input signal terminal IN to the second pole of the first transistor M1 and the first pole of the second transistor M2. The first inverter R1 and the second inverter R2 perform two inversion operations on the low level signal of the second pole of the first transistor M1 and output a low level signal to the output terminal Next of the latch 200. The nand gate 410 performs a nand operation on a low level signal output from the Next output terminal of the latch and a low level signal input from the second clock signal input terminal CK2 to output a high level signal, and the buffer circuit 420 performs a triple inversion on the high level signal output from the nand gate 410 and outputs a low level signal to the output terminal Gout of the shift register unit 400. As can be seen from fig. 8, there is a delay of at least one clock pulse width between a rising edge of the signal output from the output terminal Gout of the shift register unit 400 and a rising edge of the pulse signal input from the input signal terminal IN, thereby achieving a shift of the pulse signal input from the input signal terminal IN.

The application also provides a shift register, which comprises N cascaded shift register units, wherein N is a positive integer. Please refer to fig. 9, which shows a schematic structural diagram of an embodiment of a shift register provided in the present application.

As shown in FIG. 9, the shift register 900 includes N cascaded shift register units SR11, SR12, SR13, …, SR1N-1 and SR1N, wherein each stage of the shift register units SR11, SR12, SR13, …, SR1N-1 and SR1N may be the shift register units described above with reference to FIGS. 4 to 7. The input signal terminal IN of the first stage SR11 is inputted with the enable signal Stv, and the input signal terminal IN of each of the second to Nth stages SR12 to SR1N is connected to the output terminal Next of the latch IN the previous stage.

If each stage of the shift register units SR11, SR12, SR13, …, SR1N-1, and SR1N in the shift register 900 is the shift register unit shown in fig. 4 or fig. 5, the first clock signal terminal CLK1 and the second clock signal terminal CLK2 of each stage of the shift register units SR11, SR12, SR13, …, SR1N-1, and SR1N correspond to the first clock signal input terminal CK1 and the second clock signal input terminal CK2 of the shift register unit shown in fig. 4 or fig. 5, respectively.

If each stage of the shift register units SR11, SR12, SR13, …, SR1N-1, and SR1N in the shift register 900 is the shift register unit shown in fig. 6 or fig. 7, the first clock signal terminal CLK1 and the second clock signal terminal CLK2 of each stage of the shift register units SR11, SR12, SR13, …, SR1N-1, and SR1N correspond to the first clock signal input terminal CK1 and the third clock signal input terminal CK3 of the shift register unit shown in fig. 6 or fig. 7, respectively.

In the present embodiment, the first clock signal terminal CLK1 and the second clock signal terminal CLK2 are respectively used for receiving the first clock signal CKV11 and the second clock signal CKV 12. The first clock signal CKV11 and the second clock signal CKV12 are clock signals with the same period and the same duty ratio.

Each stage of the shift register cells SR11, SR12, SR13, …, SR1N-1, SR1N may further include a reset signal input RST. The Reset signal input terminals RST of the shift register units SR11, SR12, SR13, …, SR1N-1 and SR1N are all used for receiving a Reset signal Reset 1.

With continued reference to fig. 10, a schematic diagram of another embodiment of a shift register provided herein is shown.

As shown in fig. 10, the shift register 1000 includes N cascaded shift register units SR21, SR22, SR23, SR24, …, and SR2N, where N is a positive integer. Each stage of the shift register units SR11, SR21, SR22, SR23, SR24, … and SR2N can be the shift register units shown in FIG. 4 to FIG. 7. The input signal terminal IN of the first stage SR21 is inputted with the first enable signal Stv1, and the input signal terminal IN of the second stage SR22 is inputted with the second enable signal Stv 2.

If each stage of the shift register units SR21, SR22, SR23, SR24, …, and SR2N in the shift register 1000 is the shift register unit shown in fig. 4 or fig. 5, the first clock signal terminal CLK1 and the second clock signal terminal CLK2 of each stage of the shift register units SR21, SR22, SR23, SR24, …, and SR2N correspond to the first clock signal input terminal CK1 and the second clock signal input terminal CK2 of the shift register units shown in fig. 4 or fig. 5, respectively.

If each stage of the shift register units SR21, SR22, SR23, SR24, …, and SR2N in the shift register 1000 is the shift register unit shown in fig. 6 or fig. 7, the first clock signal terminal CLK1 and the second clock signal terminal CLK2 of each stage of the shift register units SR21, SR22, SR23, SR24, …, and SR2N correspond to the first clock signal input terminal CK1 and the third clock signal input terminal CK3 of the shift register units shown in fig. 6 or fig. 7, respectively.

In the present embodiment, the first clock signal input terminal CLK1 and the second clock signal input terminal CLK2 of the 2i-1 th stage shift register unit SR2(2i-1) respectively input the first clock signal CKV21 and the second clock signal CKV22, and the first clock signal input terminal CLK1 and the second clock signal input terminal CLK2 of the 2 i-th stage shift register unit SR2(2i) respectively input the third clock signal CKV23 and the fourth clock signal CKV 24. The input signal IN of the j-th stage SR2j is connected to the output Next of the latch IN the j-2 th stage SR2(j-2), where i, j is a positive integer and 2i is not less than N, and 2 < j is not less than N. The first clock signal CKV21, the second clock signal CKV22, the third clock signal CKV23 and the fourth clock signal CKV24 have the same period and the same duty ratio.

Each stage of the shift register cells SR21, SR22, SR23, SR24, … and SR2N may further include a reset signal input RST. The Reset signal input terminals RST of the shift register units SR21, SR22, SR23, SR24, … and SR2N are all used for receiving a Reset signal Reset 2.

According to the shift register provided by the embodiment of the application, because the circuit structure of each level of shift register unit is simplified, the number of transistors in the shift register unit is reduced, the frame area occupied by the shift register can be effectively reduced, the size of a frame of a display can be further reduced, and meanwhile, the power consumption of the shift register can be reduced.

The embodiment of the application also provides a display panel, which comprises a plurality of scanning lines and the shift register. The output end of each stage of shift register unit in the shift register is respectively connected with one scanning line and used for outputting a shift signal to one scanning line. When the shift register shown in fig. 9 is used, shift signals can be output to the scanning lines one by one, so that progressive scanning of the display panel is realized; when the shift register shown in fig. 10 is used, the shift signals can be output to the scanning lines in an interlaced manner, and interlaced scanning of the display panel can be realized.

It is understood that the display panel further includes some well-known structures, such as a pixel array, thin film transistors connected to pixel units in the pixel array in a one-to-one correspondence, data lines intersecting with scan lines in an insulating manner, a source driving circuit, and the like. The data lines are used for transmitting data signals to be displayed to each pixel unit through the thin film transistors.

The above description is only a preferred embodiment of the application and is illustrative of the principles of the technology employed. It will be appreciated by a person skilled in the art that the scope of the invention as referred to in the present application is not limited to the embodiments with a specific combination of the above-mentioned features, but also covers other embodiments with any combination of the above-mentioned features or their equivalents without departing from the inventive concept. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims

1. A shift register unit is characterized by comprising a latch, wherein the latch comprises a first clock signal input end, a second clock signal input end, an input signal end, a first transistor, a second transistor, a first inverter and a second inverter;

a gate of the first transistor is connected to the first clock signal input terminal, a first pole of the first transistor is connected to the input signal terminal, and a second pole of the first transistor is connected to the input terminal of the first inverter;

the grid electrode of the second transistor is connected with the second clock signal input end, the first pole of the second transistor is connected with the second pole of the first transistor, and the second pole of the second transistor is connected with the output end of the second inverter;

the output end of the first phase inverter is connected with the input end of the second phase inverter, and the output end of the second phase inverter is connected with the output end of the latch;

the channel types of the first transistor and the second transistor are the same;

the shift register unit further comprises a nand gate, and a first input end and a second input end of the nand gate are respectively connected with the output end of the latch and the second clock signal input end.

2. The shift register unit according to claim 1, further comprising a buffer circuit;

and the output end of the NAND gate is connected with the input end of the buffer circuit.

3. The shift register cell according to claim 2, wherein the buffer circuit includes a fourth inverter, a fifth inverter, and a sixth inverter;

the input end of the fourth inverter is connected with the input end of the buffer circuit, and the output end of the fourth inverter is connected with the input end of the fifth inverter;

the output end of the fifth inverter is connected with the input end of the sixth inverter;

and the output end of the sixth inverter is connected with the output end of the shift register unit.

4. The shift register cell according to claim 2, wherein the buffer circuit comprises a seventh inverter;

the input end of the seventh phase inverter is connected with the input end of the buffer circuit, and the output end of the seventh phase inverter is connected with the output end of the shift register unit.

5. The shift register cell of claim 1, wherein the first clock signal input terminal is for inputting a first signal, and the second clock signal input terminal is for inputting a second signal;

the input signal end is used for inputting a single pulse signal;

the first signal and the second signal are clock signals with the same period, and the duty ratios of the first signal and the second signal are equal.

6. The shift register cell of claim 1, further comprising a first voltage signal input, a reset signal input, and a third transistor;

a gate of the third transistor is connected to the reset signal input terminal, a first pole of the third transistor is connected to the first voltage signal input terminal, and a second pole of the third transistor is connected to an output terminal of the first inverter.

7. The shift register cell of claim 6, wherein the first voltage signal input terminal is configured to input a first voltage signal having a constant voltage value;

the reset signal input end is used for inputting a reset signal, and the reset signal comprises a pulse signal.

8. A shift register comprising N cascaded shift register cells according to claim 1, wherein N is a positive integer.

9. The shift register of claim 8, wherein the input signal terminal of the first stage of the shift register unit is inputted with an enable signal, and the input signal terminal of each of the second to nth stages of the shift register unit is connected to the output terminal of the latch of the previous stage of the shift register unit.

10. The shift register of claim 8, wherein a first enable signal is input to the input signal terminal of the shift register unit of a first stage, a second enable signal is input to the input signal terminal of the shift register unit of a second stage, a first clock signal input terminal and a second clock signal input terminal of the shift register unit of a 2i-1 th stage are respectively input with a first clock signal and a second clock signal, and a first clock signal input terminal and a second clock signal input terminal of the shift register unit of a 2 i-th stage are respectively input with a third clock signal and a fourth clock signal; and the input signal end of the j-th stage of the shift register unit is connected with the output end of the latch in the j-2 th stage of the shift register unit, wherein i and j are positive integers, 2i is less than or equal to N, and j is more than 2 and less than or equal to N.

11. A display panel comprising a plurality of scan lines and the shift register of any one of claims 8-10, wherein the output of each stage of the shift register unit is connected to one of the scan lines.