KR20030051209A - Shift register with level shifter - Google Patents

Abstract

PURPOSE: A shift register having a level shifter is provided to reduce swing range of clock signals and start pulse supplied to the shift register to decrease power consumption. CONSTITUTION: A shift register includes a plurality of stages(ST1) and a plurality of level shifters(LS1). The plurality of stages shift a start pulse inputted through an input terminal to sequentially output shift pulses. The multiple level shifters level-shift voltage levels of the shift pulses respectively supplied from the stages. The stages and the level shifters are composed of only P-channel thin film transistor. The level shifters down minimum voltage level of the shift pulses to negative-polarity voltage. Each of the stages includes an output buffer(54) for selecting one of the first clock signal and the first supply voltage according to voltages of the first and second nodes, the first controller(50) for controlling the first node according to the start pulse, and the second controller(52) for controlling the second node according to the start pulse and the second clock signal.

Description

Shift register with level shifter {SHIFT REGISTER WITH LEVEL SHIFTER}

The present invention relates to a shift register circuit, and more particularly, to a shift register incorporating a level shifter using only thin film transistors of the same type channel. The present invention also relates to a scan driver, a data driver, and a liquid crystal display device including the shift register.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, the gate lines and the data lines are arranged to cross each other, and the liquid crystal cells are positioned in an area where the gate lines and the data lines cross each other. The liquid crystal panel is provided with pixel electrodes and a common electrode for applying an electric field to each of the liquid crystal cells. Each of the pixel electrodes is connected to any one of the data lines via source and drain terminals of a thin film transistor, which is a switching element. The gate terminal of the thin film transistor is connected to one of the gate lines.

The driving circuit includes a gate driver for driving the gate lines and a data driver for driving the data lines. The gate driver sequentially supplies the scanning signals to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel by one line. The data driver supplies a video signal to each of the data lines whenever a gate signal is supplied to any one of the gate lines. Accordingly, the liquid crystal display displays an image by adjusting light transmittance by an electric field applied between the pixel electrode and the common electrode according to the video signal for each liquid crystal cell.

Thin film transistors used in such liquid crystal display devices are classified into amorphous silicon type and polysilicon type depending on whether amorphous silicon and polysilicon are used as semiconductor layers.

The amorphous silicon type thin film transistor has an advantage that the characteristics of the amorphous silicon film are relatively good, so that the characteristics are stable, but it is difficult to apply when the pixel density is improved due to the relatively low charge mobility. In addition, in the case of using an amorphous silicon type thin film transistor, peripheral driving circuits such as the gate driver and the data driver have to be manufactured separately and mounted in the liquid crystal panel, which has a disadvantage in that the manufacturing cost of the liquid crystal display device is high.

On the other hand, the polysilicon thin film transistor has an advantage of not only difficulty in increasing pixel density due to high charge mobility, but also lowering manufacturing cost by allowing peripheral driving circuits to be embedded in the liquid crystal panel. Accordingly, liquid crystal displays using polysilicon thin film transistors have emerged.

1 schematically illustrates a configuration of a liquid crystal display device using a conventional polysilicon thin film transistor.

The liquid crystal display of FIG. 1 includes a liquid crystal panel 10 in which an image display unit 12, data and gate shift registers 14 and 16, and a sampling switch array 15 are formed, and a control circuit and a data drive IC are integrated. A printed circuit board (PCB) 20 having a chip 22 and a level shifter array 24 mounted thereon, and a flexible printed circuit (FPC) film 18 electrically connecting the liquid crystal panel 10 and the PCB 20 to each other. It is provided.

The image display unit 12 displays an image through the matrix of liquid crystal cells LC. Each of the liquid crystal cells LC includes a thin film transistor TFT using polysilicon as a switching element connected to an intersection of the gate line GL and the data line DL. As polysilicon is 100 times faster in charge mobility than amorphous silicon, the response speed of the TFT is fast, so that the liquid crystal cells LC are usually driven in a point-sequential manner. The data lines DL receive a video signal from the sampling switch array 15 driven by the data shift register 14. The gate lines GL are supplied with scan pulses from the gate shift register 16.

The data shift register 14 is composed of a plurality of stages each having an output terminal connected to a sampling switch of the sampling switch array 15. The multiple stages are cascaded as shown in FIG. 2 to sequentially supply sampling signals to the sampling switches by shifting the source start pulse from the control chip 22.

In detail, the plurality of stages ST1 to STn shown in FIG. 2 are cascaded to the source start pulse SP input line and are connected to three clock signal supply lines among the four-phase clock signal C1 to C4 supply lines. Each is connected. The four-phase clock signals C1 to C4 are supplied in a phase delayed form by one clock in sequence as shown in FIG. Each of the stages ST1 to STn shifts the start pulse SP by one clock by using three clock signals among the clock signals C1 to C4. The signals SO1 to SOn respectively output from the stages ST1 to STn of the shift register are supplied as sampling signals and also as start pulses of the next stage.

The gate shift register 16 includes a plurality of stages each having an output terminal connected to each of the gate lines GL. The plurality of stages are cascaded as shown in FIG. 2 to sequentially supply the scan pulses to the gate lines GL by shifting the start pulses from the control chip 22.

The sampling switch array 15 is composed of a plurality of sampling switches (not shown), each having an output terminal connected to the data lines DL, and driven by a sampling signal from the data shift register 14. The sampling switches sequentially sample the video signal from the control chip 22 in response to the sampling signal and supply the data signal to the data lines DL.

As such, the image display unit 12, the data shift register 14, the sampling switching array 15, and the gate shift register 16 included in the liquid crystal panel 10 are formed in the same process as polysilicon is adopted. In this case, when the thin film transistors included in the liquid crystal panel 10 are composed only of NMOS or PMOS thin film transistors, that is, thin film transistors of the same type channel, the manufacturing cost can be reduced compared to the case of the CMOS thin film transistors. This is because the CMOS thin film transistors include both the P channel and the N channel, so that the driving voltage is wide and the circuit is easy to integrate, but the manufacturing process is high and the reliability is low due to the large number of processes. Therefore, the liquid crystal panel 10 has been developed in the direction of using only PMOS or NMOS thin film transistors having a relatively low manufacturing cost by reducing the number of processes.

The control circuit (not shown) included in the control chip 22 transmits the video data supplied from the outside to the data driving IC (not shown), as well as the data shift register 14 and the gate shift register 16. Provide the driving control signals required. The data driving IC (not shown) converts the video data input from the control circuit (not shown) into a video signal which is an analog signal and supplies it to the sampling switch array 15 through the FPC film 18.

The level shifter array 24 increases the swing width of the drive control signals (clock signal or the like) input from the control circuit and supplies the swing shift registers 16 to the data shift register 14 and the gate shift register 16. For example, the level shifter array 24 outputs a clock signal generated by a control circuit having a swing voltage of 10 V or less, and level shifted to have a swing width of 10 V or more, including a negative voltage. This is because a pulse having a swing voltage of 10V or more must be supplied to drive the thin film transistor formed on the liquid crystal panel 10.

In other words, when the liquid crystal panel 10 includes a PMOS thin film transistor, a driving pulse for driving the PMOS thin film transistors included in the sampling switch array 15 and the pixel region 12 is a swing of 10V or more in the negative direction. A pulse with a width is needed. In order to supply such driving pulses, pulses having a swing width of 10 V or more in the negative direction as clock signals should be supplied to the gate and data shift registers 14 and 16. However, when the external circuits are implemented as a single chip, such as the control chip 22, a clock signal having a swing width of less than 10V is easily generated, but it is difficult to generate more voltage or negative voltage. In other words, it is difficult to secure device characteristics for generating a voltage having a swing width of 10V or more or a negative voltage, which makes it difficult to manufacture an IC single chip. Accordingly, in the related art, a level shifter array 24 for level shifting a driving pulse of 10V to have a swing width of 10V or more including a negative voltage had to be implemented as a separate chip and mounted on the PCB 20. . In this case, there is a disadvantage in that it is difficult to compact the external circuit mounted on the PCB 20. In addition, since a clock signal having a swing width of 10V or more including positive and negative voltages must be supplied to the data shift register 14 and the gate shift register 16 of the liquid crystal panel 10 from the external circuit, power consumption is high. There is this.

Accordingly, an object of the present invention is to provide a shift register incorporating a level shifter using only thin film transistors of the same type channel.

Another object of the present invention is to provide a shift register incorporating a level shifter capable of lowering the lowest voltage level of an input signal by employing only thin film transistors of the same type channel.

Another object of the present invention is to provide a scan driver including a shift register incorporating a level shifter.

Another object of the present invention is to provide a data driver including a shift register incorporating a level shifter.

It is still another object of the present invention to provide a liquid crystal display including a shift register incorporating a level shifter.

1 is a block diagram schematically showing the configuration of a liquid crystal display device employing a conventional polysilicon.

FIG. 2 is a block diagram showing the configuration of the shift register shown in FIG. 1; FIG.

3 is an input / output waveform diagram of the shift register shown in FIG. 2;

4 is a block diagram illustrating a shift register having a level shifter according to an embodiment of the present invention.

5A to 5C are input and output waveform diagrams of the shift register shown in FIG.

6 is a detailed circuit diagram of a shift register having a level shifter according to the first embodiment of the present invention.

7 is an input / output waveform diagram of the shift register shown in FIG. 6;

8 is a detailed circuit diagram of a shift register having a level shifter according to a second embodiment of the present invention.

9 is an input / output waveform diagram of the shift register shown in FIG. 8;

10 is a detailed circuit diagram of a shift register having a level shifter according to a third embodiment of the present invention.

FIG. 11 is a block diagram schematically illustrating a configuration of a polysilicon liquid crystal display including a shift register having a level shifter according to an exemplary embodiment of the present invention. FIG.

<Description of Main Parts of Drawing>

ST1 to STn: Stage LS1 to LSn: Level Shifter

10, 30: liquid crystal panel 12, 39: image display unit

14, 51: data shift register 15, 35: sampling switch array

16, 53: gate shift register

18, 44: flexible printed circuit (FPC) film 20: printed circuit board (PCB)

22, 42: control chip 24, 33, 34, 38: level shifter array

31, 32, 36: shift stage array

50: first control unit 52: second control unit

54: output buffer 58: third control

60: output unit

In order to achieve the above object, a shift register with a built-in level shifter according to the present invention comprises a plurality of stages that are sequentially connected and output a shift pulse sequentially by shifting a start pulse input through an input terminal; And a plurality of level shifters for outputting down one of the voltage levels of the shift pulses supplied from each of the stages.

The scan driver according to the present invention is a scan driver for supplying scan pulses to scan lines of a display panel, and includes a plurality of stages sequentially outputting shift pulses by shifting start pulses that are cascaded and input through an input terminal. And a shift register including a plurality of level shifters for level shifting the voltage level of the shift pulses supplied from each of the stages and outputting the shift pulses to the scan pulses.

A data driver for supplying a video signal to data lines of a display panel, the data driver comprising: a sampling switch array for sampling and outputting a video signal in response to an input sampling signal; A plurality of stages that are connected in a cascaded manner and shift start pulses input through an input terminal to sequentially output shift pulses, and a plurality of stages that level shift the voltage levels of the shift pulses supplied from each of the stages and output them as sampling signals. And a shift register including level shifters.

A liquid crystal display device according to the present invention comprises: a liquid crystal panel comprising a liquid crystal cell matrix for displaying an image; A scan driver for supplying scan pulses to scan lines of the liquid crystal panel; A data driver for supplying a video signal to data lines of the liquid crystal panel; The scan driver level shifts the voltage levels of the shift pulses supplied from each of the first stages and the plurality of first stages that are cascaded and shifted by a start pulse input through an input terminal, and sequentially output the shift pulses. A first shift register including a plurality of first level shifters for outputting a scan pulse; The data driver includes a sampling switch array for sampling and outputting a video signal in response to an input sampling signal, and a plurality of second stages that sequentially output a shift pulse by shifting start pulses that are connected in cascade and input through an input terminal. And a second shift register including a plurality of second level shifters for level shifting the voltage level of the shift pulses supplied from each of the second stages and outputting the sample signal as a sampling signal.

Here, the shift register is characterized by consisting only of thin film transistors of the same type channel.

In particular, the shift register is characterized by consisting of only the thin film transistors of the P channel.

The level shifter may be configured to output a result of lowering the lowest voltage level of the shift pulse to a negative voltage.

Each of the first and second stages may include an output buffer unit for selecting and outputting any one of a first clock signal and a first supply voltage according to voltages of first and second nodes; A first control unit controlling the first node according to a start pulse; And a second controller configured to control the second node according to the start pulse and the second clock signal.

The first control unit includes a first transistor having a conductive path between the start pulse and the first node and a control electrode controlling the conductive path according to the start pulse.

The first control unit further includes a second transistor having a conductive path between the output terminal of the first transistor and the first node and a control electrode controlling the conductive path according to a fourth clock signal. do.

The first control unit further includes a third transistor having a conductive path between the first node and the first supply voltage input line and a control electrode controlling the conductive path according to the voltage of the second node. It is done.

The second control unit includes: a fourth transistor having a conductive path between a second supply voltage input line and the second node and a control electrode controlling the conductive path according to the third clock signal; And a fifth transistor having a conductive path between the second node and the first supply voltage input line and a control electrode for controlling the conductive path according to the start pulse.

The output buffer unit includes a sixth transistor having a conductive path between the first clock signal input line and an output line of the stage and a control electrode controlling the conductive path according to the voltage of the first node; And a seventh transistor having a conductive path between the output line of the stage and the first supply voltage input line and a control electrode for controlling the conductive path according to the voltage of the second node.

The output buffer unit may further include a first capacitor connected between a control electrode of the sixth transistor and an output line of the stage to bootstrap the voltage of the control electrode.

Each of the level shifters includes an output unit for selecting and outputting any one of a second supply voltage and a third supply voltage according to the voltage of the third node; And a controller for controlling the third node according to the first node and the second clock signal.

The control unit includes an eighth transistor having a conductive path between the third node and an output line of the level shifter and a control electrode controlling the conductive path according to the second clock signal; And a ninth transistor having a conductive path between the third supply voltage input line and the third node and a control electrode for controlling the conductive path according to the voltage of the first node.

The output unit includes a tenth transistor having a conductive path between the third supply voltage input line and an output line of the level shifter, and a control electrode controlling the conductive path according to the voltage of the third node; And an eleventh transistor having a conductive path between the output line of the level shifter and the first supply voltage input line and a control electrode for controlling the conductive path according to the second clock signal.

The level shifter may include a conductive path between the output line and the first supply voltage input and prevent the output voltage of the output line of the level shifter from being distorted by external noise, and the conductive path may be connected to the voltage of the second node. And a twelfth transistor having a control electrode controlled according to the present invention.

The level shifter includes a conductive path between the third node and the level shifter to prevent the output voltage of the level shifter output line from being distorted by the leakage current of the tenth transistor when the third node is floated. And a thirteenth transistor having a control electrode for controlling the conductive path according to the voltage of the second node.

The level shifter prevents the tenth transistor from being turned on by the ninth transistor turned on according to the voltage of the first node in a period in which the start pulse is input, thereby distorting the output voltage of the level shifter output line. And a fourteenth transistor having a conductive path between the output line of the level shifter and the first supply voltage input line and a control electrode for controlling the conductive path according to the fourth clock signal. do.

The level shifter may include a conductive path between the third supply voltage input line and the input line of the ninth transistor so as to prevent the output voltage of the level shifter output line from being distorted due to the leakage current of the ninth transistor. And a fifteenth transistor having a control electrode for controlling the conductive passage in accordance with the third supply voltage.

The output unit may further include a second capacitor connected between the control electrode of the tenth transistor and the output line of the level shifter to bootstrap the voltage of the control electrode.

The first to third supply voltages are characterized in that the voltage level is small in the order of the third, second, first.

The first to fourth clock signals are clock signals delayed by one clock in order of first, second, third, and fourth, and the fourth clock signals are clock signals having an in phase with the start pulse. It features.

The third control unit may include: an eighth transistor having a conductive path between the third node and an output line of the level shifter, and a control electrode controlling the conductive path according to the second clock signal; A ninth transistor having a conductive path between the third supply voltage input line and the third node and a control electrode controlling the conductive path according to the voltage of the first node; The output unit includes: a tenth transistor having a conductive path between the third supply voltage input line and an output line of the level shifter, and a control electrode controlling the conductive path according to the voltage of the third node; An eleventh transistor having a conductive path between the output line of the level shifter and the first supply voltage input line and a control electrode for controlling the conductive path according to the second clock signal; The leveled down shift pulse output through the output lines of the level shifter is partially overlapped with the leveled down shift pulse of the previous level shifter.

The thin film transistor included in the liquid crystal panel, the scan driver and the data driver uses polysilicon as a semiconductor layer, and the scan driver and the data driver are embedded in the liquid crystal panel.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 to 11.

4 is a block diagram illustrating a shift register incorporating a level shifter according to an exemplary embodiment of the present invention.

The shift register incorporating the level shifter shown in FIG. 4 includes a shift stage array 32 composed of n stages ST1 to STn connected to a start pulse input line and stages ST1 to STn. And a level shifter array 34 composed of level shifters LS1 to LSn respectively connected to an output terminal of the.

In the shift stage array 32, the start pulse SP is input to the first stage ST1, and the output signal of the previous stage is input to the second to nth stages ST2 to STn. The stages ST1 to STn receive three clock signals among the first to fourth clock signals C1 to C4 which are sequentially delayed as shown in FIG. 5A. The stages ST1 to STn sequentially output the shift signals S01, SO2, ... as shown in FIG. 5B by shifting the start pulse SP using the three clock signals received. . In this case, the stages ST1 to STn have shift signals SO1 having a swing voltage of 10V or less by using the clock signals C1 to C4 inputted with a swing voltage of 10V or less and the start pulse SP. Will output SO2, ...).

Each of the level shifters LS1 to LSn receives the other one of the four clock signals C1 to C4. The level shifters LS1 to LSn level shift the shift signals SO1, SO2,... Output from the stages ST1 to STn to have a swing voltage of 10 V or more as shown in FIG. 5C. The signals L01, L02, ... are outputted. In particular, the level shifters LS1 to LSn level down the lowest voltages of the shift signals SO1, SO2,... Output from the stages ST1 to STn to a negative voltage to output the level shifters LS1 to LSn.

The signals (L01, LO2, ....) output from the shift register with the level shifter are connected to the scan (gate) lines in the scan (gate) driver which sequentially drives the scan (gate) lines of the display panel. It is used as a scan pulse to be supplied. In addition, the signals L01, LO2, .... outputted from the shift register with a level shifter are supplied to a sampling switch in a data driver for sampling and supplying a video signal to data lines of a display panel. Used as

FIG. 6 shows a detailed circuit configuration of the first and second stages ST1 and ST2 and the first and second level shifters LS1 and LS2 shown in FIG. 4.

The first stage ST1 illustrated in FIG. 6 includes a first control unit 50 for controlling the Q node according to the start pulse SP and the fourth clock signal CL4, and the third clock signal CL3 and the start pulse. Selecting and outputting one of the first clock signal C1 and the first supply voltage VSS according to the voltage of the Q node and the QB node, and the second control unit 52 that controls the QB node according to (SP). A buffer unit 54 is provided.

The first controller 50 controls the sixth PMOS transistor T6 of the buffer unit 54 through the Q node so that the first clock signal C1 is supplied to the output signal SO1 through the output line. To this end, the first controller 50 may include a first PMOS transistor T1, a first PMOS transistor T1, a fourth clock signal C4 input line connected to the start pulse SP input line in a diode form, and A second PMOS transistor T2 connected between the Q nodes is provided.

The second controller 52 controls the seventh PMOS transistor T7 of the buffer unit 54 through the QB node so that the first supply voltage VSS is supplied to the output signal SO1 through the output line. To this end, the second controller 52 may include a fourth PMOS transistor T4 and a fourth PMOS transistor connected between the second supply voltage VDD input line, the third clock signal C3 input line, and the QB node. And a fifth PMOS transistor T5 connected between T4 and the start pulse SP input line and the first supply voltage VSS input line.

The buffer unit 54 selects the first clock signal C1 according to the voltage of the Q node and supplies the sixth PMOS transistor T6 to the output line and the first supply voltage VSS according to the voltage of the QB node. And a seventh PMOS transistor T7 to select and supply the output line.

In addition, the first controller 50 is connected between the Q node and the QB node and the first supply voltage VSS input line to control the Q node in dual operation with the seventh PMOS transistor T7. ) Is further provided.

In addition, the first stage ST1 includes the first capacitor CQ connected between the gate terminal and the source terminal of the sixth PMOS transistor T6, that is, between the Q node and the output line, and the seventh PMOS transistor T7. A second capacitor CQB is further provided between the gate terminal and the source terminal, that is, between the QB node and the first supply voltage VSS input line.

The first level shifter LS1 includes a third control unit 58 for controlling the QL node according to the state of the Q node and the second clock signal C2, and a negative value according to the voltages of the QL node and the second clock signal C2. And an output unit 60 for selecting and outputting any one of the polarity voltage VNEG and the first supply voltage VSS.

The third controller 58 causes the negative voltage VNEG to be supplied to the output line of the first level shifter LS1 through the Q node according to the states of the Q node and the second clock signal C2. To this end, the third controller 58 includes an eighth PMOS transistor T8 connected between the QL node, the second clock signal C2 input line, and the output line, the negative voltage VNEG supply line, and the Q node; A ninth PMOS transistor T9 connected between the QL nodes is provided.

The output unit 60 selects the negative supply voltage VNEG according to the voltage of the QL node and supplies it to the output line. The output unit 60 supplies a first supply voltage according to the second clock signal C2. And an eleventh PMOS transistor T11 that selects and supplies VSS to an output line.

The first level shifter LS1 is connected to the twelfth PMOS transistor T12 connected between the output line, the QB node of the first stage ST1, and the first supply voltage VSS input line to prevent distortion of the output line. ) Is further provided. The first level shifter LS1 further includes a third capacitor CQL connected between the gate terminal and the source terminal of the tenth PMOS transistor T10, that is, between the QL node and the output line.

As shown in FIG. 7, the first to fourth clock signals C1 to C4 having a form in which the phase delay is sequentially delayed by one clock as shown in FIG. 7 are supplied to the first stage ST1 and the level shifter LS1 having such a configuration. do. Here, the fourth clock signal C4 has a phase synchronized with the start pulse SP. The first to fourth clock signals C1 to C4 including the start pulse SP are supplied in the negative polarity type having a swing voltage of 10V or less. Here, the potential of 10V is assumed to be low and the potential of 0V is assumed to be high. The operation of the first stage ST1 and the level shifter LS1 will be described with reference to the driving waveform as follows.

When the start pulse SP and the fourth clock signal C4 become high simultaneously in the T1 period, the first and second PMOS transistors T1 and T2 are turned on to charge the Q node with a voltage of about 2 V. . As a result, the sixth and ninth PMOS transistors T6 and T9 having the gate terminal connected to the Q node are gradually turned on. In addition, the fifth PMOS transistor T5 is turned on by the high state start pulse SP so that a voltage of 10 V from the first supply voltage VSS input line is charged to the QB node. Accordingly, the third and seventh PMOS transistors T3 and T7 having gate terminals connected to the QB node are turned off. As a result, a voltage of 10 V of the first clock signal C1 maintaining the low state through the turned-on sixth PMOS transistor T6 is supplied to the output line of the first stage ST1 so that the output line is low (10 V). ) Is charged. Also, since the negative voltage VNEG -8V is charged to the QL node through the turned-on ninth PMOS transistor T9, the tenth PMOS transistor T10 is weakly turned on, but the QB node is high. The twelfth PMOS transistor T12 is turned on so that a voltage of 10V is charged in the output line of the first level shifter LS1.

In the T2 period, when the start pulse SP and the fourth clock signal C4 go low and the first clock signal C1 goes high, the internal capacitor Cgs formed between the gate and the source of the sixth PMOS transistor Due to the influence of the first capacitor CQ, a bootstrapping phenomenon occurs, and the Q node is charged to a voltage of about -7V, thereby being surely high. This bootstrapping phenomenon is possible because all of the first to third PMOS transistors T1 to T3 are turned off and the Q node is in a floating state. Accordingly, the sixth PMOS transistor T6 is reliably turned on so that the high voltage (0V) of the first clock signal C1 is quickly charged to the output line of the first stage ST1, and the output line is 0V. Goes high. In addition, the ninth PMOS transistor T9 is reliably turned on, and a negative voltage VNEG of −8 V is applied to the output line of the first level shifter LS1 via the tenth PMOS transistor T10 that is turned on. Allow it to charge quickly. In this case, the bootstrapping occurs on the QL node due to the parasitic capacitor Cgs and the third capacitor CQL formed in the tenth PMOS transistor T10, so that the QL node rises to about -18V. The negative voltage VNEG is quickly charged to the output line of the level shifter LS1.

When the first clock signal C1 becomes low in the T3 period and the second clock signal C2 becomes high, the voltage of the Q node drops back to about 2V and passes through the turned-on sixth PMOS transistor T6. The low voltage 10V of the first clock signal C1 is charged to the output line of the first stage ST1. In addition, the eleventh PMOS transistor T11 is turned on by the second clock signal C2 in the high state, and a voltage of about 10 V, which is the first supply voltage VSS, is applied to the output line of the first level shifter LS1. Is charged. In this case, since the eighth PMOS transistor T8 is turned on by the second clock signal C2 in the high state, the QL node is charged with a voltage of about 7.2 V, so that the tenth PMOS transistor T10 is turned off. do.

When the third clock signal C3 becomes high in the T4 period, the fourth PMOS transistor T4 is turned on so that 0 V, the second supply voltage VDD, is charged to the QB node. PMOS transistors T3, T7, and T12 are turned on. The voltage of about 2V charged to the Q node via the turned-on third PMOS transistor T3 is changed to 10V, and the output line of the first stage ST1 via the turned-on seventh PMOS transistor T7 is turned on. Will maintain 10V. The output line of the first level shifter LS1 is maintained at 10V by the turned-on twelfth PMOS transistor T12. In this case, the second capacitor CQB prevents the voltage of the QB node from being distorted by the leakage currents of the third and seventh PMOS transistors T3 and T7.

When the fourth clock signal C4 becomes high in the T5 period, the second PMOS transistor T2 is turned on. However, since the first and fifth PMOS transistors T1 and T5 maintain the turn-off state, the QB node maintains 0V. Accordingly, since the third, seventh, and twelfth PMOS transistors T3, T7, and T12 are continuously turned on, the output line of the first stage ST1 and the output line of the first level shifter LS1 are 10V. Keep it.

The second stage ST2 and the second level shifter LS2 have the same configuration as the first stage ST1 and the level shifter LS1 described above. However, the second stage ST2 and the second level shifter LS2 are clock signals having a phase difference by one clock with respect to the clock signals used in the first stage ST1 and the level shifter LS1. It operates as described above using the output signal of ST1. Accordingly, the second stage ST2 and the second level shifter LS2 are shifted by one clock signal S02 and the level shifted signal LO2 in comparison with the first stage ST1 and the level shifter LS1. Will print

8 illustrates a shifter register incorporating a level shifter according to another embodiment of the present invention, and shows a detailed circuit of the first stage ST1 and the first level shifter LS1.

The first stage ST1 illustrated in FIG. 8 has the same configuration as the first stage ST1 illustrated in FIG. 6.

The first level shifter LS1 is a thirteenth PMOS transistor to prevent distortion of the output signal LS1 due to leakage current of the tenth PMOS transistor T10 in comparison with the first level shifter LS1 illustrated in FIG. 6. And a fourteenth PMOS transistor T14 for preventing distortion of the output signal LS1 due to precharging the QL node. For this purpose, the thirteenth PMOS transistor T13 is connected between the QL node, the QB node, and the output line of the first level shifter LS1, and the fourteenth PMOS transistor T14 is an output line of the first level shifter LS1. And a gate terminal of the second PMOS transistor T2 and the first supply voltage VSS input line.

An operation process of the first stage ST1 and the first shift register LS1 having such a configuration will be described below with reference to the driving waveform shown in FIG. 9.

When the start pulse SP and the fourth clock signal C4 become high at the same time in the T1 period, the first and second PMOS transistors T1 and T2 are turned on so that the Q node is charged with a voltage of about 2V. . As a result, the sixth and ninth PMOS transistors T6 and T9 having the gate terminal connected to the Q node are gradually turned on. In addition, the fifth PMOS transistor T5 is turned on by the high state start pulse SP so that a voltage of 10 V from the first supply voltage VSS input line is charged to the QB node. Accordingly, the third and seventh PMOS transistors T3 and T7 having gate terminals connected to the QB node are turned off. As a result, a voltage of 10 V of the first clock signal C1 maintaining the low state through the turned-on sixth PMOS transistor T6 is supplied to the output line of the shift register 56 so that the output line is low (10 V). Is charged. Here, the negative voltage VNEG -8V is precharged to the QL node through the ninth PMOS transistor T9 gradually turned on so that a voltage of -8V flows into the output line of the first level shifter LS1 to output the output signal. The case where LO1 is distorted occurs. The fourteenth PMOS transistor T14 prevents the output signal LO1 of the first level shifter LS1 from being distorted in the T1 period. For this purpose, the gate terminal of the fourteenth PMOS transistor T14 is connected to the gate terminal of the second PMOS transistor T2, and each of the source terminal and the drain terminal is an output line and a first supply voltage of the first level shifter LS1. (VSS) is connected to the input line. Although the fourteenth PMOS transistor T14 is turned on by the fourth clock signal C4 in the high state and the QL node is precharged in the T1 period, the first level shifter is turned on. Keep the output line of (LS1) at 10V.

Next, in the period T2, when the start pulse SP and the fourth clock signal C4 go low and the first clock signal C1 goes high, the gate and the source of the sixth PMOS transistor T6 are formed. Bootstrapping occurs under the influence of the internal capacitor Cgs and the first capacitor CQ, and the Q node is charged to a voltage of about -7V, thereby becoming a high state. Accordingly, the sixth PMOS transistor T6 is reliably turned on so that the high voltage (0V) of the first clock signal C1 is quickly charged to the output line of the first stage ST1, and the output line is 0V. Goes high. In addition, the ninth PMOS transistor T9 is reliably turned on, and a negative voltage VNEG of −8 V is applied to the output line of the first level shifter LS1 via the tenth PMOS transistor T10 that is turned on. Allow to charge In this case, the bootstrapping occurs on the QL node due to the parasitic capacitor Cgs and the second capacitor CQL formed in the tenth PMOS transistor T10, so that the high state in which the QL node rises to about -18V is obtained. The negative voltage VNEG of -8V is quickly charged to the output line of the first level shifter LS1.

When the first clock signal C1 becomes low in the T3 period and the second clock signal C2 becomes high, the voltage of the Q node drops back to about 2V and passes through the turned-on sixth PMOS transistor T6. The low voltage 10V of the first clock signal C1 is charged to the output line of the first stage ST1. In addition, the eleventh PMOS transistor T11 is turned on by the second clock signal C2 in the high state, and a voltage of about 10 V, which is the first supply voltage VSS, is applied to the output line of the first level shifter LS1. Is charged. In this case, since the eighth PMOS transistor T8 is turned on by the second clock signal C2 in the high state, the QL node is charged with a voltage of about 7.2V, so the tenth PMOS transistor T10 is turned off. do.

When the third clock signal C3 becomes high in the T4 period, the fourth PMOS transistor T4 is turned on so that the 0 V, the second supply voltage VDD, is charged to the QB node, thereby causing the third, seventh, and twelfth PMOS. Transistors T3, T7, and T12 are turned on. The voltage of about 2V charged to the Q node via the turned-on third PMOS transistor T3 is discharged to 10V and the output of the first stage ST1 via the turned-on seventh PMOS transistor T7. The line will maintain 10V. The output line of the first level shifter LS1 is maintained at 10V by the turned-on twelfth PMOS transistor T12. Here, as the ninth PMOS transistor T9 is turned off, the QL node is in a floating state. In this case, due to the leakage current of the tenth PMOS transistor T10, the QL node gradually changes from the voltage of about 7V to the high state, that is, toward -8V. Accordingly, a case where the tenth PMOS transistor T10 is gradually turned on and the voltage on the output line of the first level shifter LS1 is distorted. The thirteenth PMOS transistor T13 prevents the output signal LO1 of the first level shifter LS1 from being distorted in the T4 period. To this end, the thirteenth PMOS transistor T13 has a gate terminal connected to the QB node, and a source terminal and a drain terminal respectively connected to the output line of the QL node and the first level shifter LS1. The thirteenth PMOS transistor T13 is turned on by the high state of the QB node by the fourth PMOS transistor T4 turned on. Accordingly, the QL node is electrically connected to the first level shifter LS1 so that no floating section is generated. In addition, since the voltage of the low state 10V on the output line of the first level shifter LS1 is supplied to the QL node, the tenth PMOS transistor T10 remains turned off, so that the output line of the first level shifter LS1 is maintained. Maintains a low state of 10V.

When the fourth clock signal becomes high in the T5 period, the second PMOS transistor T2 is turned on. However, since the first and fifth PMOS transistors T2 and T5 remain turned off, the QB node maintains 0V. Accordingly, since the third, seventh, and twelfth PMOS transistors T3, T7, and T12 remain turned on, the output line of the first stage ST1 and the output line of the first level shifter LS1 are 10V. Keep it.

FIG. 10 is a diagram illustrating a shift register according to another embodiment of the present invention. In particular, a detailed circuit of the first stage ST1 and the first level shifter LS1 is illustrated.

The first stage ST1 illustrated in FIG. 10 has the same configuration as the first stage ST1 illustrated in FIG. 8.

When the PMOS threshold voltage is lower than that of the first level shifter LS1 illustrated in FIG. 8, the voltage of the QL node is distorted by the leakage current of the ninth PMOS transistor T10. And a fifteenth PMOS transistor T15 for preventing the output signal LO1 from being distorted. For this purpose, the fifteenth PMOS transistor T15 is diode-connected between the negative voltage VNEG input line and the source terminal of the tenth PMOS transistor T10.

An operation process of the first stage ST1 and the first level shifter LS1 having such a configuration will be described below with reference to the driving waveform shown in FIG. 9.

When the start pulse SP and the fourth clock signal C4 become high simultaneously in the T1 period, the first and second PMOS transistors T1 and T2 are turned on to charge the Q node with a voltage of about 2 V. . As a result, the sixth and ninth PMOS transistors T6 and T9 having gate terminals connected to the Q nodes are gradually turned on. In addition, the fifth PMOS transistor T5 is turned on by the start pulse SP in a high state, and a voltage of 10 V from the first supply voltage VSS input line is charged to the QB node. Accordingly, the third and seventh PMOS transistors T3 and T7 having gate terminals connected to the QB node are turned off. As a result, a voltage of 10 V of the first clock signal C1 maintaining the low state through the turned-on sixth PMOS transistor T6 is supplied to the output line of the first stage ST1 so that the output line is low (10 V). ) Is charged. The fourteenth PMOS transistor T14 is turned on by the fourth clock signal C4 in the high state so that the tenth PMOS transistor T10 is turned on due to precharging of the QL node. Keep the output line at 10V.

In the T2 period, when the start pulse SP and the fourth clock signal C4 go low and the first clock signal C1 goes high, the internal capacitor Cgs formed between the gate and the source of the sixth PMOS transistor Due to the influence of the first capacitor CQ, a bootstrapping phenomenon occurs, and the Q node is charged to a voltage of about -7V, thereby being surely high. Accordingly, the sixth PMOS transistor T6 is reliably turned on so that the high voltage (0V) of the first clock signal C1 is quickly charged to the output line of the shift register 60, thereby The output line goes high at 0V. In addition, the ninth PMOS transistor T9 is reliably turned on, and a negative voltage VNEG of −8 V is applied to the output line of the first level shifter LS1 via the tenth PMOS transistor T10 that is turned on. Allow to charge

On the other hand, the voltage of the QL node has a large dependency on the threshold voltage Vth of the PMOS transistor. Accordingly, the high voltage charged in the output line of the first level shifter LS1 may be distorted due to the difference in the threshold voltage Vth. In detail, when the Q node rises to about -7V due to the bootstrapping phenomenon, the bootstrapping phenomenon is also caused by the parasitic capacitor Cgs and the third capacitor CQL of the ninth PMOS transistor T9 turned on. Occurs and the voltage rises to about -18V. Here, when the threshold voltage Vth of the PMOS transistor is -3V, the ninth PMOS transistor T9 is turned off under the condition of Vgs = 1V and Vds = -10V, so that the voltage of -18V applied to the QL node is held. Therefore, the voltage of −8 V supplied to the output line of the first level shifter LS1 through the turned-on tenth PMOS transistor T10 may be maintained without distortion. On the other hand, when the threshold voltage Vth of the PMOS transistor is -1V, the -18V voltage applied to the QL node is discharged toward -8V by the leakage current of the ninth PMOS transistor T9, so that the first level shifter LS1 is discharged. Voltage distortion occurs at the voltage on the output line of the transistor to about -6.9V. In order to block the leakage current of the ninth PMOS transistor T9, a fifteenth PMOS transistor T15 is further inserted in the form of a diode between the negative voltage VNEG input line and the ninth PMOS transistor T9.

When the first clock signal C1 becomes low in the T3 period and the second clock signal C2 becomes high, the voltage of the Q node drops back to about 2V and passes through the turned-on sixth PMOS transistor T6. The low voltage 10V of the first clock signal C1 is charged to the output line of the first stage ST1. In addition, the eighth PMOS transistor T8 is turned on by the second clock signal C2 in the high state, and a voltage of about 7.2V is charged to the QL node, thereby turning off the tenth PMOS transistor T10. . At the same time, the eleventh PMOS transistor T11 is turned on by the second clock signal C2 in the high state, and a voltage of about 10 V, which is the first supply voltage VSS, is applied to the output line of the first level shifter LS1. Is charged.

When the third clock signal C3 becomes high in the T4 period, the fourth PMOS transistor T4 is turned on so that the 0 V, the second supply voltage VDD, is charged to the QB node. PMOS transistors T3, T7, and T13 are turned on. The voltage of about 2V charged to the Q node via the turned-on third PMOS transistor T3 is discharged to 10V, and the output line of the shift register 60 via the turned-on seventh PMOS transistor T7. Will maintain 10V. In addition, the first level shifter LS1 output line maintains the low state voltage 10V by the turned-on thirteenth PMOS transistor T13.

When the fourth clock signal becomes high in the T5 period, the second PMOS transistor T2 is turned on. However, since the first and fifth PMOS transistors T2 and T5 remain turned off, the QB node maintains 0V. Therefore, since the third, seventh, and twelfth PMOS transistors T3, T7, and T12 remain turned on, the output lines of the first stage ST1 and the first level shifter LS1 are low (10V). Keep).

As described above, the shift register incorporating the level shifter according to the present invention outputs a shift signal having a swing voltage of 10 V or more by using a clock signal having a swing voltage of 10 V or less and a start pulse. In particular, the shift register incorporating the level shifter according to the present invention can lower the lowest voltage in the negative direction using only PMOS transistors. The shift register incorporating such a level shifter is applied to an EL (Electro Luminesence) display or a gate (scan) driver and a data driver of the liquid crystal display shown in FIG.

Here, when a shift register with a level shifter is applied to a data driver, a faster circuit operation is required. However, when the polling time characteristic of the level shifter LS is not good, the second clock signal C2 is applied to the eighth and eleventh PMOS transistors T8 and T11 included in the level shifter LS in order to drive the overlap. Instead, the third clock signal C3 is input. In detail, when the second clock signal C2 is input to the eighth and eleventh PMOS transistors T8 and T11 as described above, the eighth and the fifth clock signals are generated by the second clock signal C2 in the high state in the T3 period. 11 PMOS transistors T8 and T11 are turned on to charge the output line of the level shifter LS to a low state of 10V. On the other hand, when the third clock signal C3 is input to the eighth and eleventh PMOS transistors T8 and T11, the eighth and eleventh PMOS transistors may be formed by the second clock signal C3 in a low state in the T3 period. T8 and T11 are turned off so that the output line of the level shifter remains high at -8 V. Then, the eighth and eleventh PMOS transistors T8 are driven by the third clock signal C3 being high in the T4 period. T11 is turned on to charge the output line of the level shifter LS to a low state of 10V. Accordingly, the level shifter is kept high for the periods T3 and T4. Here, the output waveform in the T3 period, which cannot be used due to poor polling characteristics, is not used because it overlaps the output waveform of the previous stage and the level shifter LS, and the output waveform in the T4 period in which the stable high state is maintained is the sampling signal. Used as

11 schematically illustrates a configuration of a polysilicon liquid crystal display according to an exemplary embodiment of the present invention. 4 includes a liquid crystal panel 30 in which an image display unit 39, a data shift register 51, a gate shift register 53, and a sampling switch array 35 are formed, and a control circuit and a data drive IC. The PCB 40 in which the integrated control chip 42 is mounted is provided, and the FPC film 44 electrically connecting the liquid crystal panel 30 and the PCB 40 to each other is provided.

The image display unit 39, the data shift register 51, the sampling switch array 35, and the gate shift register 53 included in the liquid crystal panel 30 are formed in the same process. In particular, the thin film transistors included in the liquid crystal panel 30 may be composed of only NMOS or PMOS thin film transistors, thereby reducing manufacturing costs by reducing the number of processes and improving reliability than those of the CMOS thin film transistors.

In the image display unit 39, liquid crystal cells LC are arranged in a matrix to display an image. Each of the liquid crystal cells LC includes a thin film transistor TFT using polysilicon as a switching element connected to an intersection of the gate line GL and the data line DL. As the thin film transistor TFT uses polysilicon 100 times faster than amorphous silicon, the liquid crystal cells LC are driven in a point-sequential manner. The gate lines GL are supplied with scan pulses through the gate shift register 53. The data lines DL receive a video signal through the sampling switch array 35.

The gate shift register 53 has a shift stage array 36 composed of a plurality of stages as described above, and a level shifter array composed of level shifters connected between the stages and the gate lines GL. 38).

The stages of the shift stage array 36 shift the start pulse SP from the control chip 42 to sequentially supply the shift pulses to the level shifters.

The level shifters of the level shifter array 38 supply the shift pulses from the stage by increasing their swing voltages as scan pulses to each of the gate lines GL. For example, the level shifter array 38 shifts a shift signal input with a swing voltage of 10 V or less from the shift stage array 36 to a scan pulse by level shifting the shift signal to have a swing width of 10 V or more including a negative voltage. Output

The data shift register 51 is composed of a shift stage array 31 composed of a plurality of stages as described above, and level shifters connected between each of the stages and sampling switches of the sampling switch array 35. A level shifter array 33 is provided.

The stages of the shift stage array 31 shift the start pulse SP from the control chip 42 to sequentially supply the shift pulses to the level shifters.

The level shifters of the level shifter array 33 supply the shift pulse from the stage by increasing its swing voltage as a sampling signal to each of the sampling switches. For example, the level shifter array 33 level shifts a shift signal input from the shift stage array 31 with a swing voltage of 10 V or less to have a swing width of 10 V or more, including a negative voltage, as a sampling signal. Output

The sampling switch array 35 is composed of a plurality of sampling switches (not shown), each having an output terminal connected to the data lines DL and driven by a sampling signal input from the data shift register 51. The sampling switches sequentially sample the video signal input from the control chip 42 in response to the sampling signal and supply the data signal to the data lines DL.

The control circuit (not shown) included in the control chip 42 transmits the video data supplied from the outside to the data driving IC, as well as the data shift register 51 and the gate shift register through the FPC film 44. The drive control signals necessary for the 53 are provided. Here, the clock signals supplied from the control chip 42 to the data shift register 51 and the gate shift register 53 have a swing voltage of 10V or less, thereby reducing power consumption. The data driving IC (not shown) converts the video data input from the control circuit into an analog signal and supplies it to the sampling switch array 35 through the FPC film 44.

As described above, the shift register incorporating the level shifter according to the present invention can incorporate the level shifter using only thin film transistors of the same type using polysilicon. In particular, the shift register incorporating the level shifter according to the present invention may output the shift signal by leveling down the lowest voltage level of the input signal in the negative direction using only thin film transistors of the same type using polysilicon. Accordingly, the power consumption can be reduced by reducing the swing width of the clock signals and the start pulses supplied to the shift register.

The shift register with a built-in level shifter according to the present invention is applied to a gate (scan) driver and a data driver of a display panel of an EL display device or a liquid crystal display device using polysilicon. Can be embedded in the display panel. When the shift register with the level shifter is embedded in the display panel, the swing width of the clock signals and start pulses supplied to the display panel can be reduced, thereby reducing power consumption.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (93)

A plurality of stages that are cascadely connected and sequentially output a shift pulse by shifting a start pulse input through an input terminal; And a plurality of level shifters for level shifting and outputting a voltage level of a shift pulse supplied from each of the stages. The method of claim 1, And said stages and level shifters comprise only thin film transistors of the same type channel. The method of claim 2, And said stages and level shifters comprise only a thin film transistor of a P channel. The method of claim 1, The level shifter And a shift register having a level shifter, wherein the minimum voltage level of the shift pulse is lowered to a negative voltage and output. The method of claim 1, Each of the stages An output buffer unit for selecting and outputting any one of a first clock signal and a first supply voltage according to voltages of the first and second nodes; A first control unit controlling the first node according to a start pulse; And a second controller configured to control the second node according to the start pulse and the second clock signal. The method of claim 5, The first control unit And a first transistor having a conductive path between the start pulse and the first node and a control electrode for controlling the conductive path according to the start pulse. The method of claim 6, The first control unit And a second transistor having a conductive path between the output terminal of the first transistor and the first node and a control electrode for controlling the conductive path according to a third clock signal. One shift register. The method of claim 7, wherein The first control unit And a third transistor having a conductive path between the first node and the first supply voltage input line and a control electrode for controlling the conductive path according to the voltage of the second node. Built-in shift register. The method of claim 8, The second control unit A fourth transistor having a conductive path between a second supply voltage input line and the second node and a control electrode for controlling the conductive path according to the second clock signal; And a fifth transistor having a conductive path between the second node and the first supply voltage input line and a control electrode for controlling the conductive path according to the start pulse. . The method of claim 9, The output buffer unit A sixth transistor having a conductive path between the first clock signal input line and an output line of the stage, and a control electrode controlling the conductive path according to the voltage of the first node; And a seventh transistor having a conductive path between the output line of the stage and the first supply voltage input line and a control electrode for controlling the conductive path according to the voltage of the second node. Built-in shift register. The method of claim 10, The output buffer unit And a first capacitor connected between the control electrode of the sixth transistor and the output line of the stage, for bootstrapping the voltage of the control electrode. The method of claim 10, Each of the level shifters An output unit for selecting and outputting any one of a first supply voltage and a third supply voltage according to the voltage of the third node; And a third controller configured to control the third node according to the first node and the fourth clock signal. The method of claim 12, The third control unit An eighth transistor having a conductive path between the third node and an output line of the level shifter, and a control electrode controlling the conductive path according to the fourth clock signal; And a ninth transistor having a conductive path between the third supply voltage input line and the third node and a control electrode for controlling the conductive path according to the voltage of the first node. One shift register. The method of claim 13, The output unit A tenth transistor having a conductive path between the third supply voltage input line and an output line of the level shifter and a control electrode controlling the conductive path according to the voltage of the third node; And an eleventh transistor having a conductive path between the output line of the level shifter and the first supply voltage input line and a control electrode for controlling the conductive path according to the fourth clock signal. Built-in shift register. The method of claim 14, The level shifter In order to prevent the output voltage of the output line of the level shifter from being distorted by external noise, the conductive path between the output line and the first supply voltage input and the conductive path are controlled according to the voltage of the second node. A shifter register with a level shifter, further comprising a twelfth transistor having a control electrode. The method of claim 15, The level shifter In order to prevent the output voltage of the level shifter output line from being distorted by the leakage current of the tenth transistor when the third node is floated, the conductive passage between the third node and the level shifter and the conductive passage are And a thirteenth transistor having a control electrode for controlling in accordance with the voltage of the second node. The method of claim 16, The level shifter In order to prevent the output voltage of the level shifter output line from being distorted, the tenth transistor is turned on by the ninth transistor turned on according to the voltage of the first node in the period in which the start pulse is input. And a fourteenth transistor having a conductive path between an output line of the shifter and the first supply voltage input line and a control electrode for controlling the conductive path according to the third clock signal. Built-in shift register. The method of claim 17, The level shifter In order to prevent the output voltage of the level shifter output line from being distorted due to the leakage current of the ninth transistor, the conductive passage between the third supply voltage input line and the input line of the ninth transistor and A shift register with a level shifter, further comprising a fifteenth transistor having a control electrode controlled according to a supply voltage. The method of claim 17, The output unit And a second capacitor connected between the control electrode of the tenth transistor and the output line of the level shifter and for bootstrapping the voltage of the control electrode. The method of claim 12, And said first to third supply voltages have a lower voltage level in order of third, second, and first. The method of claim 12, The first to fourth clock signals are clock signals that are phase-delayed by one clock in order of first, fourth, second, and third, And the third clock signal is a clock signal having a phase in phase with the start pulse. The method of claim 21, The third control unit, An eighth transistor having a conductive path between the third node and an output line of the level shifter, and a control electrode controlling the conductive path according to the second clock signal; A ninth transistor having a conductive path between the third supply voltage input line and the third node and a control electrode controlling the conductive path according to the voltage of the first node; The output unit, A tenth transistor having a conductive path between the third supply voltage input line and an output line of the level shifter and a control electrode controlling the conductive path according to the voltage of the third node; And an eleventh transistor having a conductive path between the output line of the level shifter and the first supply voltage input line and a control electrode for controlling the conductive path according to the second clock signal. Built-in shift register. The method of claim 22, And an output pulse from the level shifter partially overlaps with an output pulse of a previous level shifter. In the scan driver for supplying the scan pulse to the scan lines of the display panel, A plurality of stages that are cascadely connected and sequentially output a shift pulse by shifting a start pulse input through an input terminal; And a shift register including a plurality of level shifters for level shifting the voltage level of the shift pulses supplied from each of the stages and outputting the shift pulses to the scan pulses. The method of claim 24, The shift register is configured as only thin film transistors of the same type channel. The method of claim 25, The shift register is configured as only a thin film transistor of the P channel. The method of claim 24, The level shifter And down the minimum voltage level of the shift pulse to a negative voltage and outputting the negative voltage. The method of claim 24, Each of the stages An output buffer unit for selecting and outputting any one of a first clock signal and a first supply voltage according to voltages of the first and second nodes; A first control unit controlling the first node according to a start pulse; And a second controller configured to control the second node according to the start pulse and the second clock signal. The method of claim 28, The first control unit And a first transistor having a conductive path between the start pulse and the first node and a control electrode for controlling the conductive path according to the start pulse. The method of claim 29, The first control unit And a second transistor having a conductive path between the output terminal of the first transistor and the first node and a control electrode for controlling the conductive path according to a third clock signal. The method of claim 30, The first control unit And a third transistor having a conductive path between the first node and the first supply voltage input line and a control electrode for controlling the conductive path according to the voltage of the second node. The method of claim 31, wherein The second control unit A fourth transistor having a conductive path between a second supply voltage input line and the second node and a control electrode for controlling the conductive path according to the second clock signal; And a fifth transistor having a conductive path between the second node and the first supply voltage input line and a control electrode for controlling the conductive path according to the start pulse. The method of claim 32, The output buffer unit A sixth transistor having a conductive path between the first clock signal input line and an output line of the stage, and a control electrode controlling the conductive path according to the voltage of the first node; And a seventh transistor having a conductive path between the output line of the stage and the first supply voltage input line and a control electrode for controlling the conductive path according to the voltage of the second node. The method of claim 33, wherein The output buffer unit And a first capacitor connected between the control electrode of the sixth transistor and the output line of the stage and for bootstrapping the voltage of the control electrode. The method of claim 33, wherein Each of the level shifters An output unit for selecting and outputting any one of a first supply voltage and a third supply voltage according to the voltage of the third node; And a third controller for controlling the third node according to the first node and the fourth clock signal. 36. The method of claim 35 wherein The third control unit An eighth transistor having a conductive path between the third node and an output line of the level shifter, and a control electrode controlling the conductive path according to the fourth clock signal; And a ninth transistor having a conductive path between the third supply voltage input line and the third node and a control electrode for controlling the conductive path according to the voltage of the first node. The method of claim 36, The output unit A tenth transistor having a conductive path between the third supply voltage input line and an output line of the level shifter and a control electrode controlling the conductive path according to the voltage of the third node; And an eleventh transistor having a conductive path between the output line of the level shifter and the first supply voltage input line and a control electrode for controlling the conductive path according to the fourth clock signal. The method of claim 37, The level shifter In order to prevent the output voltage of the output line of the level shifter from being distorted by external noise, the conductive path between the output line and the first supply voltage input and the conductive path are controlled according to the voltage of the second node. And a twelfth transistor having a control electrode. The method of claim 38, The level shifter In order to prevent the output voltage of the level shifter output line from being distorted by the leakage current of the tenth transistor when the third node is floated, the conductive passage between the third node and the level shifter and the conductive passage are And a thirteenth transistor having a control electrode controlled according to the voltage of the second node. The method of claim 39, The level shifter In order to prevent the output voltage of the level shifter output line from being distorted, the tenth transistor is turned on by the ninth transistor turned on according to the voltage of the first node in the period in which the start pulse is input. And a fourteenth transistor having a conductive path between an output line of the shifter and the first supply voltage input line and a control electrode for controlling the conductive path according to the third clock signal. The method of claim 40, The level shifter In order to prevent the output voltage of the level shifter output line from being distorted due to the leakage current of the ninth transistor, the conductive passage between the third supply voltage input line and the input line of the ninth transistor and And a fifteenth transistor having a control electrode controlled according to a supply voltage. The method of claim 37, The output unit And a second capacitor connected between the control electrode of the tenth transistor and the output line of the level shifter and for bootstrapping the voltage of the control electrode. 36. The method of claim 35 wherein The first to third supply voltages are scan drivers, characterized in that the voltage level is small in the order of the third, second, first. 36. The method of claim 35 wherein The first to fourth clock signals are clock signals that are phase-delayed by one clock in order of first, fourth, second, and third, And the third clock signal is a clock signal having an in phase with the start pulse. The method of claim 44, The third control unit, An eighth transistor having a conductive path between the third node and an output line of the level shifter, and a control electrode controlling the conductive path according to the second clock signal; A ninth transistor having a conductive path between the third supply voltage input line and the third node and a control electrode controlling the conductive path according to the voltage of the first node; The output unit, A tenth transistor having a conductive path between the third supply voltage input line and an output line of the level shifter and a control electrode controlling the conductive path according to the voltage of the third node; And an eleventh transistor having a conductive path between the output line of the level shifter and the first supply voltage input line and a control electrode for controlling the conductive path according to the second clock signal. The method of claim 45, And the output pulse from the level shifter partially overlaps with the output pulse of the previous level shifter. A data driver for supplying a video signal to data lines of a display panel, A sampling switch array for sampling and outputting the video signal in response to an input sampling signal; A plurality of stages that are cascadely connected and sequentially output a shift pulse by shifting a start pulse input through an input terminal; And a shift register including a plurality of level shifters for level shifting the voltage level of the shift pulses supplied from each of the stages and outputting the sample signal as the sampling signal. The method of claim 47, The shift register is configured as only thin film transistors of the same type channel. 49. The method of claim 48 wherein And the shift register is composed of only P-channel thin film transistors. The method of claim 47, The level shifter And lowering the lowest voltage level of the shift pulse to a negative voltage and outputting the negative voltage. The method of claim 47, Each of the stages An output buffer unit for selecting and outputting any one of a first clock signal and a first supply voltage according to voltages of the first and second nodes; A first control unit controlling the first node according to a start pulse; And a second controller for controlling the second node according to the start pulse and the second clock signal. The method of claim 51, wherein The first control unit And a first transistor having a conductive path between the start pulse and the first node and a control electrode for controlling the conductive path according to the start pulse. The method of claim 52, wherein The first control unit And a second transistor having a conductive path between an output terminal of the first transistor and the first node and a control electrode for controlling the conductive path according to a third clock signal. The method of claim 53, wherein The first control unit And a third transistor having a conductive path between the first node and the first supply voltage input line and a control electrode for controlling the conductive path according to the voltage of the second node. The method of claim 54, wherein The second control unit A fourth transistor having a conductive path between a second supply voltage input line and the second node and a control electrode for controlling the conductive path according to the second clock signal; And a fifth transistor having a conductive path between the second node and the first supply voltage input line and a control electrode for controlling the conductive path according to the start pulse. The method of claim 55, The output buffer unit A sixth transistor having a conductive path between the first clock signal input line and an output line of the stage, and a control electrode controlling the conductive path according to the voltage of the first node; And a seventh transistor having a conductive path between the output line of the stage and the first supply voltage input line and a control electrode for controlling the conductive path according to the voltage of the second node. The method of claim 56, wherein The output buffer unit And a first capacitor connected between the control electrode of the sixth transistor and the output line of the stage to bootstrap the voltage of the control electrode. The method of claim 56, wherein Each of the level shifters An output unit for selecting and outputting any one of a first supply voltage and a third supply voltage according to the voltage of the third node; And a third controller for controlling the third node according to the first node and the fourth clock signal. The method of claim 58, The third control unit An eighth transistor having a conductive path between the third node and an output line of the level shifter, and a control electrode controlling the conductive path according to the fourth clock signal; And a ninth transistor having a conductive path between the third supply voltage input line and the third node and a control electrode for controlling the conductive path according to the voltage of the first node. The method of claim 59, The output unit A tenth transistor having a conductive path between the third supply voltage input line and an output line of the level shifter and a control electrode controlling the conductive path according to the voltage of the third node; And an eleventh transistor having a conductive path between the output line of the level shifter and the first supply voltage input line and a control electrode for controlling the conductive path according to the fourth clock signal. The method of claim 60, The level shifter In order to prevent the output voltage of the output line of the level shifter from being distorted by external noise, the conductive path between the output line and the first supply voltage input and the conductive path are controlled according to the voltage of the second node. And a twelfth transistor having a control electrode. 62. The method of claim 61, The level shifter In order to prevent the output voltage of the level shifter output line from being distorted by the leakage current of the tenth transistor when the third node is floated, the conductive passage between the third node and the level shifter and the conductive passage are And a thirteenth transistor having a control electrode for controlling in accordance with the voltage of the second node. 63. The method of claim 62, The level shifter In order to prevent the output voltage of the level shifter output line from being distorted, the tenth transistor is turned on by the ninth transistor turned on according to the voltage of the first node in the period in which the start pulse is input. And a fourteenth transistor having a conductive path between an output line of the shifter and the first supply voltage input line and a control electrode for controlling the conductive path according to the third clock signal. The method of claim 63, wherein The level shifter In order to prevent the output voltage of the level shifter output line from being distorted due to the leakage current of the ninth transistor, the conductive passage between the third supply voltage input line and the input line of the ninth transistor and And a fifteenth transistor having a control electrode controlled according to a supply voltage. The method of claim 59, The output unit And a second capacitor connected between the control electrode of the tenth transistor and the output line of the level shifter and for bootstrapping the voltage of the control electrode. The method of claim 58, The first to the third supply voltage is a data driver, characterized in that the voltage level is small in the order of the third, second, first. The method of claim 58, The first to fourth clock signals are clock signals that are phase-delayed by one clock in order of first, fourth, second, and third, And the third clock signal is a clock signal having an in phase with the start pulse. The method of claim 67 wherein The third control unit, An eighth transistor having a conductive path between the third node and an output line of the level shifter, and a control electrode controlling the conductive path according to the second clock signal; A ninth transistor having a conductive path between the third supply voltage input line and the third node and a control electrode controlling the conductive path according to the voltage of the first node; The output unit, A tenth transistor having a conductive path between the third supply voltage input line and an output line of the level shifter and a control electrode controlling the conductive path according to the voltage of the third node; And an eleventh transistor having a conductive path between the output line of the level shifter and the first supply voltage input line and a control electrode for controlling the conductive path according to the second clock signal. The method of claim 68, wherein And the output pulse from the level shifter partially overlaps with the output pulse of the previous level shifter. A liquid crystal panel comprising a liquid crystal cell matrix for displaying an image; A scan driver for supplying scan pulses to scan lines of the liquid crystal panel; A data driver for supplying a video signal to data lines of the liquid crystal panel; The scan driver, The scan is performed by level shifting the voltage levels of the shift pulses supplied from each of the first stages and the plurality of first stages that are sequentially connected and shift the start pulses input through the input terminal, and sequentially output the shift pulses. A first shift register comprising a plurality of first level shifters outputting in pulses; The data driver, A sampling switch array for sampling and outputting the video signal in response to an input sampling signal; The sampling is performed by level shifting the voltage levels of the shift pulses supplied from the second stages and the plurality of second stages sequentially connected to the start pulses input through the input terminal to sequentially output the shift pulses. And a second shift register including a plurality of second level shifters for outputting a signal. The method of claim 70, And the first and second shift registers are composed of thin film transistors of the same type channel only. The method of claim 71 wherein And the first and second shift registers are composed of only P-channel thin film transistors. The method of claim 70, The first and second level shifters And lowering the lowest voltage level of the shift pulse to a negative voltage and outputting the negative voltage. The method of claim 70, Each of the first and second stages An output buffer unit for selecting and outputting any one of a first clock signal and a first supply voltage according to voltages of the first and second nodes; A first control unit controlling the first node according to a start pulse; And a second controller configured to control the second node according to the start pulse and the second clock signal. The method of claim 74, wherein The first control unit And a first transistor having a conductive path between the start pulse and the first node and a control electrode for controlling the conductive path according to the start pulse. 76. The method of claim 75 wherein The first control unit And a second transistor having a conductive path between the output terminal of the first transistor and the first node and a control electrode for controlling the conductive path according to a third clock signal. 77. The method of claim 76, The first control unit And a third transistor having a conductive path between the first node and the first supply voltage input line and a control electrode for controlling the conductive path according to the voltage of the second node. . 78. The method of claim 77 wherein The second control unit A fourth transistor having a conductive path between a second supply voltage input line and the second node and a control electrode for controlling the conductive path according to the second clock signal; And a fifth transistor having a conductive path between the second node and the first supply voltage input line and a control electrode for controlling the conductive path according to the start pulse. The method of claim 78, The output buffer unit A sixth transistor having a conductive path between the first clock signal input line and an output line of the stage, and a control electrode controlling the conductive path according to the voltage of the first node; And a seventh transistor having a conductive path between the output line of the stage and the first supply voltage input line and a control electrode for controlling the conductive path according to the voltage of the second node. . 80. The method of claim 79 wherein The output buffer unit And a first capacitor connected between the control electrode of the sixth transistor and the output line of the stage and for bootstrapping the voltage of the control electrode. 81. The method of claim 80, Each of the level shifters An output unit for selecting and outputting any one of a second supply voltage and a third supply voltage according to the voltage of the third node; And a third controller for controlling the third node according to the first node and the fourth clock signal. 82. The method of claim 81 wherein The third control unit An eighth transistor having a conductive path between the third node and an output line of the level shifter, and a control electrode controlling the conductive path according to the fourth clock signal; And a ninth transistor having a conductive path between the third supply voltage input line and the third node and a control electrode for controlling the conductive path according to the voltage of the first node. 83. The method of claim 82, The output unit A tenth transistor having a conductive path between the third supply voltage input line and an output line of the level shifter and a control electrode controlling the conductive path according to the voltage of the third node; And an eleventh transistor having a conductive path between the output line of the level shifter and the first supply voltage input line and a control electrode for controlling the conductive path according to the fourth clock signal. . 84. The method of claim 83 wherein The level shifter In order to prevent the output voltage of the output line of the level shifter from being distorted by external noise, the conductive path between the output line and the first supply voltage input and the conductive path are controlled according to the voltage of the second node. And a twelfth transistor having a control electrode. 87. The method of claim 84, The level shifter In order to prevent the output voltage of the level shifter output line from being distorted by the leakage current of the tenth transistor when the third node is floated, the conductive passage between the third node and the level shifter and the conductive passage are And a thirteenth transistor having a control electrode controlled according to the voltage of the second node. 86. The method of claim 85, The level shifter In order to prevent the output voltage of the level shifter output line from being distorted, the tenth transistor is turned on by the ninth transistor turned on according to the voltage of the first node in the period in which the start pulse is input. And a fourteenth transistor having a conductive path between an output line of the shifter and the first supply voltage input line and a control electrode for controlling the conductive path according to the third clock signal. . 87. The method of claim 86, The level shifter In order to prevent the output voltage of the level shifter output line from being distorted due to the leakage current of the ninth transistor, the conductive passage between the third supply voltage input line and the input line of the ninth transistor and And a fifteenth transistor having a control electrode controlled according to a supply voltage. 84. The method of claim 83 wherein The output unit And a second capacitor connected between the control electrode of the tenth transistor and the output line of the level shifter and for bootstrapping the voltage of the control electrode. 82. The method of claim 81 wherein And the first to third supply voltages have a smaller voltage level in order of third, second, and first. 82. The method of claim 81 wherein The first to fourth clock signals are clock signals that are phase-delayed by one clock in order of first, fourth, second, and third, And the third clock signal is a clock signal having an in phase with the start pulse. 92. The method of claim 90, The third control unit, An eighth transistor having a conductive path between the third node and an output line of the level shifter, and a control electrode controlling the conductive path according to the second clock signal; A ninth transistor having a conductive path between the third supply voltage input line and the third node and a control electrode controlling the conductive path according to the voltage of the first node; The output unit, A tenth transistor having a conductive path between the third supply voltage input line and an output line of the level shifter and a control electrode controlling the conductive path according to the voltage of the third node; And an eleventh transistor having a conductive path between the output line of the level shifter and the first supply voltage input line and a control electrode for controlling the conductive path according to the second clock signal. . 92. The method of claim 91 wherein And the output pulse from the level shifter partially overlaps with the output pulse of the previous level shifter. The method of claim 70, The thin film transistor included in the liquid crystal panel, the scan driver and the data driver uses polysilicon as a semiconductor layer, The scan driver and the data driver are built in the liquid crystal panel.