KR100600087B1 - Level shifter and shift register with built-in the same - Google Patents

Abstract

The present invention provides a level shifter and a shift register incorporating the level shifter which can reduce power consumption. The level shifter controls the voltages of the first and second nodes using the first and second supply voltages according to the input signal and the first control signal, and between the input line of the second supply voltage and the first node. A first transistor for controlling a first conductive path according to the input signal, a second transistor for controlling a second conductive path between the first node and the second node according to the first control signal, and the second node; A control unit including a third transistor configured to control a third conductive path between the input lines of the first supply voltage according to the first control signal; A fourth transistor for controlling a fourth conductive path between the input line of the second supply voltage and the second node according to the voltage of the first node, and a fifth conductivity between the input line and the output terminal of the second supply voltage A fifth transistor for controlling a path according to the voltage of the second node, a sixth transistor for controlling a sixth conductive path between the output terminal and an input line of the first supply voltage according to a second control signal, and the first And an output buffer including a first capacitor connected between the node and the second node, and a second capacitor connected between the second node and the output terminal.

Description

LEVEL SHIFTER AND SHIFT REGISTER WITH BUILT-IN THE SAME}             

1 is a block diagram schematically showing the configuration of a liquid crystal display device employing a conventional polysilicon.

FIG. 2 is a block diagram showing the configuration of the shift register shown in FIG. 1; FIG.

3 is an input / output waveform diagram of the shift register shown in FIG. 2;

4 is a block diagram showing a configuration of a liquid crystal display device including a level shifter according to the present invention.

5 is a block diagram showing the configuration of a shift register incorporating the level shifter shown in FIG.

6A to 6C are input and output waveform diagrams of the shift register shown in FIG.

7 is a detailed circuit diagram of a shift register having the level shifter shown in FIG.

FIG. 8 is an input / output waveform diagram of the shift register shown in FIG. 7. FIG.

9 is a detailed circuit diagram of a shift register having a level shifter according to an embodiment of the present invention.

10 is an input / output waveform diagram of the shift register shown in FIG. 9;

11 is a detailed circuit diagram of a shift register having a level shifter according to another embodiment of the present invention.

<Description of Main Parts of Drawing>

ST1 to STn: Stage LS1 to LSn: Level Shifter

10, 30: liquid crystal panel 12, 39: image display unit

14, 51: data shift register 15: sampling switch array

16, 53: gate shift register 18, 44: flexible printed circuit (FPC) film

20, 40: printed circuit board (PCB) 22, 42: control chip

34, 38: level shifter array 32, 36: shift stage array

50, 60: first control unit 52, 62: second control unit

54, 64: buffer section 56, 66: third control section

58, 68, 78: output section

The present invention relates to a level shifter, and more particularly, to a level shifter capable of reducing power consumption and a shift register having the same.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, the gate lines and the data lines are arranged to cross each other, and the liquid crystal cells are positioned in an area where the gate lines and the data lines cross each other. The liquid crystal panel is provided with pixel electrodes and a common electrode for applying an electric field to each of the liquid crystal cells. Each of the pixel electrodes is connected to any one of the data lines via source and drain terminals of a thin film transistor which is a switching element. The gate terminal of the thin film transistor is connected to any one of the gate lines.

The driving circuit includes a gate driver for driving the gate lines and a data driver for driving the data lines. The gate driver sequentially supplies scan signals to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel by one line. The data driver supplies a video signal to each of the data lines whenever a gate signal is supplied to any one of the gate lines. Accordingly, the liquid crystal display displays an image by adjusting light transmittance by an electric field applied between the pixel electrode and the common electrode according to the video signal for each liquid crystal cell.

The thin film transistor used in the liquid crystal display device is classified into an amorphous silicon type and a polysilicon type depending on whether amorphous silicon and poly silicon are used as semiconductor layers.

The amorphous silicon type thin film transistor has an advantage that the characteristics of the amorphous silicon film are relatively good, so that the characteristics are stable, but it is difficult to apply when the pixel density is improved due to the relatively low charge mobility. In addition, in the case of using an amorphous silicon type thin film transistor, peripheral driving circuits such as the gate driver and the data driver have to be manufactured separately and mounted in the liquid crystal panel, which has a disadvantage in that the manufacturing cost of the liquid crystal display device is high.

On the other hand, as the polysilicon thin film transistor has a high charge mobility, there is no difficulty in increasing the pixel density and the peripheral driving circuits can be embedded in the liquid crystal panel, thereby reducing the manufacturing cost. Accordingly, liquid crystal displays using polysilicon thin film transistors have emerged.

1 schematically illustrates a configuration of a liquid crystal display using a conventional polysilicon thin film transistor.

The liquid crystal display of FIG. 1 is a control in which the liquid crystal panel 10 in which the image display unit 12, the data and gate shift registers 14 and 16, and the sampling switch array 15 are formed, and the timing controller and the data drive IC are integrated. A printed circuit board (PCB) 20 having a chip 22 and a level shifter array 24 mounted thereon, and a flexible printed circuit (FPC) film 18 electrically connecting the liquid crystal panel 10 and the PCB 20 to each other. It is provided.

The image display unit 12 displays an image through a liquid crystal cell (LC) matrix. Each of the liquid crystal cells LC includes a thin film transistor TFT using polysilicon as a switching element connected to an intersection of the gate line GL and the data line DL. As polysilicon is 100 times faster than amorphous silicon, since the response speed of the TFT is faster, the liquid crystal cells LC are usually driven in a point-sequential manner. The data lines DL are supplied with a video signal from the sampling switch array 15 driven by the data shift register 14. The gate lines GL are supplied with scan pulses from the gate shift register 16.

The data shift register 14 is composed of a plurality of stages each having an output terminal connected to a sampling switch of the sampling switch array 15. The multiple stages are cascaded as shown in FIG. 2 to sequentially supply sampling signals to the sampling switches by shifting the source start pulse from the control chip 22.

In detail, the plurality of stages ST1 to STn shown in FIG. 2 are cascaded to the source start pulse SP input line and are connected to three clock signal supply lines among the four-phase clock signal C1 to C4 supply lines. Each is connected. The four-phase clock signals C1 to C4 are supplied in a phase delayed form by one clock in sequence as shown in FIG. 3. Each of the stages ST1 to STn shifts the start pulse SP by one clock by using three clock signals among the clock signals C1 to C4. The signals SO1 to SOn respectively output from the stages ST1 to STn of the shift register are supplied as sampling signals and also as start pulses of the next stage.

The gate shift register 16 includes a plurality of stages each having an output terminal connected to each of the gate lines GL. A plurality of stages are connected to the start pulse SP input line as shown in FIG. 2 to supply the scan pulses to the gate lines GL sequentially by shifting the start pulse from the control chip 22. .

The sampling switch array 15 is composed of a plurality of sampling switches (not shown), each having an output terminal connected to the data lines DL and driven by a sampling signal from the data shift register 14. The sampling switches sequentially sample the video signal from the control chip 22 in response to the sampling signal and supply the data signal to the data lines DL.

Thus, the image display unit 12, the data shift register 14, the sampling switching array 15, and the gate shift register 16 included in the liquid crystal panel 10 are formed in the same process as polysilicon is adopted. In this case, when the thin film transistors included in the liquid crystal panel 10 are composed of NMOS or PMOS thin film transistors, that is, thin film transistors of the same type channel, the number of processes is reduced compared to that of CMOS thin film transistors, thereby reducing manufacturing costs. do. This is because CMOS thin film transistors include both P-channel and N-channel, so that the driving voltage is wide and the circuit is easy to integrate. However, the manufacturing process is high and the reliability is low due to the large number of processes. Therefore, the liquid crystal panel 10 has been developed in the direction of using only PMOS or NMOS thin film transistors having a relatively low manufacturing cost by reducing the number of processes.

The timing controller (not shown) included in the control chip 22 transmits the video data supplied from the outside to the data driving IC (not shown), and the data shift register 14 and the gate shift register 16. Provide the necessary control signals. The data driver IC converts video data input from a timing controller (not shown) into a video signal, which is an analog signal, and supplies the converted video data to the sampling switch array 15 through the FPC film 18.

The level shifter array 24 increases the swing width of control signals (clock signals, etc.) input from a timing controller (not shown) of the control chip 22 to the data shift register 14 and the gate shift register 16. Supply. For example, the level shifter array 24 generates a clock signal generated by a timing controller (not shown) having a swing voltage of 10 V or less, and level shifted to have a swing width of 10 V or more, including a negative voltage. This is because a pulse having a swing voltage of 10V or more must be supplied to drive the thin film transistor formed in the liquid crystal panel 10.

In other words, when the liquid crystal panel 10 is composed of PMOS thin film transistors, the driving pulses for driving the PMOS thin film transistors included in the sampling switch array 15 and the image display part 12 are swings of 10 V or more in the negative polarity direction. A pulse with a width is needed. In order to supply such a driving pulse, the gate and data shift registers 14 and 16 should be supplied with pulses having a swing width of 10 V or more in the negative direction as clock signals. However, when the external circuits are implemented in a single chip such as the control chip 22, a clock signal having a swing width of less than 10V is easily generated, but it is difficult to generate more voltage or negative voltage. In other words, it is difficult to secure device characteristics for generating a voltage having a swing width of 10V or more or a negative voltage, which makes it difficult to manufacture an IC single chip. Accordingly, in the related art, a level shifter array 24 for level shifting a driving pulse of 10V to have a swing width of 10V or more including a negative voltage had to be implemented as a separate chip and mounted on the PCB 20. . In this case, there is a disadvantage in that it is difficult to compact the external circuit mounted on the PCB 20. In addition, since a clock signal having a swing width of 10V or more including positive and negative voltages must be supplied to the data shift register 14 and the gate shift register 16 of the liquid crystal panel 10 from the external circuit, the power consumption is high. There is this.

Accordingly, it is an object of the present invention to provide a level shifter which can be incorporated in a shift register using only thin film transistors of the same type channel and a shift register having the same.

Another object of the present invention is to provide a level shifter capable of reducing power consumption and a shift register having the same.

In order to achieve the above object, the level shifter according to the present invention uses the first and second supply voltages VSS and VNEG according to the input signal S0 and the first control signal C4. A first transistor that controls voltages of QL1 and QL2 and controls a first conductive path between the input line of the second supply voltage VNEG and the first node QL1 according to the input signal SO. T8, a second transistor T9 for controlling a second conductive path between the first node QL1 and the second node QL2 according to the first control signal C4, and the second node ( A control part including a third transistor (T10) for controlling a third conductive path between QL2) and an input line of the first supply voltage (VSS) according to the first control signal (C4); A fourth transistor T11 and the second supply controlling the fourth conductive path between the input line of the second supply voltage VNEG and the second node QL2 according to the voltage of the first node QL1. A fifth transistor T12 for controlling a fifth conductive path between the input line of the voltage VNEG and the output terminal according to the voltage of the second node, and between the output terminal and the input line of the first supply voltage VSS. A sixth transistor C13 for controlling a sixth conductive path of the second conductive signal according to the second control signal C2, a first capacitor CL1 connected between the first node QL1, and a second node QL2, and And an output buffer section including a second capacitor connected between a second node QL2 and the output terminal.
The level shifter according to the present invention is a level shifter for level-shifting an input signal S0 and outputting the first and second supply voltages VSS and VNEG according to the input signal S0 and the first control signal C4. ) To control the voltages of the first and second nodes QL1 and QL2, and the first conductive path between the input line of the second supply voltage VNEG and the first node QL1. A second transistor for controlling a second conductive path between the first transistor T8, the first node QL1, and the second node QL2 controlled according to SO, according to the first control signal C4. And a third transistor T10 for controlling a third conductive path between the second node QL2 and an input line of the first supply voltage VSS according to the first control signal C4. A control unit including; A fourth transistor T11 and the second supply controlling the fourth conductive path between the input line of the second supply voltage VNEG and the second node QL2 according to the voltage of the first node QL1. A fifth transistor T12 for controlling a fifth conductive path between the input line of the voltage VNEG and the output terminal according to the voltage of the second node, and between the output terminal and the input line of the first supply voltage VSS. The seventh conductive path between the sixth transistor C13 and the input line of the second supply voltage VNEG and the second node QL2 that controls the sixth conductive path of the second control signal C2 according to the second control signal C2. A seventh transistor T20 controlled according to an output voltage of the fourth transistor T11, a first capacitor CL1 connected between the first node QL1 and an output terminal of the fourth transistor T11, And a second capacitor connected between the second node QL2 and the output terminal. The rain.
The shift register according to the present invention includes a buffer unit 64 for outputting a shift pulse using a first control signal C1 and a first supply voltage according to voltages of the first and second nodes, a start pulse, and the second node. The first control unit 60 controls the voltage of the first node Q in accordance with the voltage and the first supply voltage and the second supply voltage in accordance with the start pulse and the second control signal C3. A plurality of stages including a second control unit 62 for controlling the voltage of the second node QB to shift the start pulse input through the input terminal to sequentially output the shift pulse; A third controller 66 for controlling voltages of the third and fourth nodes using a third supply voltage and the first supply voltage according to the shift pulse and the third control signal output from the buffer unit, and the third Using the at least two capacitors connected between the node and the output line of the level shifter with the fourth node therebetween to cause the third and fourth node voltages to be bootstrapping in at least two stages and to bootstrapping in at least two stages. And a level shifter including an output buffer unit 68 for selectively outputting the first and third supply voltages according to the voltages of the third and fourth nodes and the fourth control signal.
Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

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First, prior to the detailed description of the exemplary embodiment of the present invention, a liquid crystal display and a shift register incorporating a level shifter applied thereto will be described with reference to FIGS. 4 to 8. Patent Application No. 2002-65541, which is hereby incorporated by reference.

4 illustrates a liquid crystal display device to which a shift register incorporating a level shifter according to the present invention is applied.

The liquid crystal display shown in FIG. 4 includes a liquid crystal panel 30 in which an image display unit 39, a data shift register 51, a gate shift register 53, and a sampling switch array 35 are formed, a timing controller and a data drive. The PCB 40 in which the control chip 42 in which IC was integrated is mounted, and the FPC film 44 which electrically connects the liquid crystal panel 30 and the PCB 40 is provided.

The image display unit 39, the data shift register 51, the sampling switch array 35, and the gate shift register 53 included in the liquid crystal panel 30 are formed in the same process. In particular, the thin film transistors included in the liquid crystal panel 30 include only thin film transistors of the same type, that is, NMOS or PMOS thin film transistors. It becomes possible.

In the image display unit 39, liquid crystal cells LC are arranged in a matrix to display an image. Each of the liquid crystal cells LC includes a thin film transistor TFT using polysilicon as a switching element connected to an intersection of the gate line GL and the data line DL. As the TFT uses polysilicon 100 times faster than amorphous silicon, the liquid crystal cells LC are driven in a dot-sequential manner. The gate lines GL are supplied with scan pulses through the gate shift register 53. The data lines DL are supplied with an analog video signal through the sampling switch array 35.

The gate shift register 53 has a shift stage array 36 composed of a plurality of stages and a level shifter array 38 composed of level shifters connected between each of the stages and the gate lines GL. do.

The stages of the shift stage array 36 shift the start pulse SP from the control chip 42 to sequentially supply the shift pulses to the level shifters.

The level shifters of the level shifter array 38 supply the shift pulses from the stage by increasing their swing voltages as scan pulses to each of the gate lines GL. For example, the level shifter array 38 shifts a shift signal input with a swing voltage of 10 V or less from the shift stage array 36 to a scan pulse by level shifting the shift signal to have a swing width of 10 V or more including a negative voltage. Output

The data shift register 51 includes a shift stage array 32 composed of a plurality of stages, and a level shifter array composed of level shifters connected between each of the stages and sampling switches of the sampling switch array 35. 34).

The stages of the shift stage array 32 shift the start pulse SP from the control chip 42 to sequentially supply the shift pulses to the level shifters.

The level shifters of the level shifter array 34 increase the swing voltage of the stage by supplying a shift signal from each of the sampling switches to the sampling switches. For example, the level shifter array 34 shifts the shift signal input with the swing voltage of 10 V or less from the shift stage array 32 to the sampling signal by level shifting the shift signal to have a swing width of 10 V or more including the negative voltage. Output

The sampling switch array 35 is composed of a plurality of sampling switches (not shown), each having an output terminal connected to the data lines DL and driven by a sampling signal input from the data shift register 51. The sampling switches sequentially sample the analog video signal input from the control chip 42 in response to the sampling signal and supply it to the data line DL.

The timing controller (not shown) included in the control chip 42 transmits the video data supplied from the outside to the data driving IC, and the data shift register 51 and the gate shift register through the FPC film 44. Provide control signals necessary for 53. Here, the clock signals supplied from the control chip 42 to the data shift register 51 and the gate shift register 53 have a swing voltage of 10V or less, thereby reducing power consumption. The data driver IC converts video data input from a timing controller (not shown) into an analog signal and supplies the analog data to the sampling switch array 35 through the FPC film 44.

FIG. 5 shows the configuration of the data and gate shift registers 51 and 53 shown in FIG.

The data shift register 51 or the gate shift register 53 shown in FIG. 5 includes shift stage arrays 32 and 36 composed of n stages ST1 to STn connected to the start pulse SP input line. And level shifter arrays 34 and 38 composed of level shifters LS1 to LSn connected to output terminals of the stages ST1 to STn, respectively.

In the shift stage arrays 32 and 36, the start pulse SP is input to the first stage ST1, and the output signal of the previous stage is input to the second to nth stages ST2 to STn. These stages ST1 to STn receive three clock signals among the first to fourth clock signals C1 to C4 which are sequentially delayed in phase as shown in FIG. 6A. The stages ST1 to STn sequentially output the shift signals S01, SO2, ... as shown in FIG. 6B by shifting the start pulse SP by using the input three clock signals. . In this case, the stages ST1 to STn have shift signals SO1 having a swing voltage of 10V or less using the clock signals C1 to C4 inputted with a swing voltage of 10V or less and the start pulse SP. Will output SO2, ...).

Each of the level shifters LS1 to LSn receives two clock signals among the four clock signals C1 to C4. These level shifters LS1 to LSn level shift the shift signals SO1, SO2,... Output from the stages ST1 to STn to have an output having a swing voltage of 10V or more as shown in FIG. 6C. The signals L01, L02, ... are outputted. In particular, the level shifters LS1 to LSn level down the lowest voltages of the shift signals SO1, SO2,... Output from the stages ST1 to STn to a negative voltage to output the level shifters LS1 to LSn.

FIG. 7 illustrates a detailed circuit configuration of the first stage ST1 and the first level shifter LS1 shown in FIG. 4.

The first stage ST1 illustrated in FIG. 7 includes a first control unit 50 that controls the Q node according to the start pulse SP and the fourth clock signal C4, and the third clock signal C3 and the start pulse. Selecting and outputting one of the first clock signal C1 and the first supply voltage VSS according to the voltage of the Q node and the QB node and the second control unit 52 that controls the QB node according to (SP) A buffer unit 54 is provided.

The first controller 50 controls the sixth PMOS transistor T6r of the buffer unit 54 through the Q node so that the first clock signal C1 is output through the output line of the first stage ST1. To be supplied. To this end, the first controller 50 may include a first PMOS transistor T1r, a first PMOS transistor T1r, and a fourth clock signal C4 input line diode-connected to the start pulse SP input line. And a second PMOS transistor T2r connected between the Q nodes. In addition, the first controller 50 is connected between the Q node and the QB node and the first supply voltage VSS input line to control the Q node in dual operation with the seventh PMOS transistor T7r (T3r). ) Is further provided.

The second controller 52 controls the seventh PMOS transistor T7r of the buffer unit 54 through the QB node so that the first supply voltage VSS is supplied to the output signal SO1 through the output line. To this end, the second controller 52 may include a fourth PMOS transistor T4r and a fourth PMOS transistor connected between the second supply voltage VDD input line, the third clock signal C3 input line, and the QB node. And a fifth PMOS transistor T5r connected between the T4r and the start pulse SP input line and the first supply voltage VSS input line.

The buffer unit 54 selects the first clock signal C1 according to the voltage of the Q node and supplies the sixth PMOS transistor T6r to the output line and the first supply voltage VSS according to the voltage of the QB node. And a seventh PMOS transistor T7r that selects and supplies the output line.

The first stage ST1 includes the first capacitor CQ connected between the gate terminal and the source terminal of the sixth PMOS transistor T6r, that is, between the Q node and the output line, and the seventh PMOS transistor T7r. And a second capacitor CQB connected between the gate terminal and the source terminal, that is, between the QB node and the first supply voltage VSS input line.

The first level shifter LS1 includes a third control unit 58 that controls the QL node according to the states of the Q node and the second clock signal C2, and a negative value according to the voltages of the QL node and the second clock signal C2. An output unit 60 for selecting and outputting any one of the polarity voltage VNEG and the first supply voltage VSS is provided.

The third controller 56 causes the negative voltage VNEG to be supplied to the output line of the first level shifter LS1 through the Q node according to the states of the Q node and the second clock signal C2. To this end, the third controller 56 includes an eighth PMOS transistor T8r connected between the QL node and the second clock signal C2 input line and the output line, a negative voltage VNEG supply line, and a Q node; A ninth PMOS transistor T9r connected between the QL nodes is provided.

The output unit 58 selects the negative supply voltage VNEG according to the voltage of the QL node and supplies it to the output line, and the first supply voltage according to the second clock signal C2. And an eleventh PMOS transistor T11r for selecting and supplying VSS to an output line.

The first level shifter LS1 further includes twelfth to fifteenth PMOS transistors T12r, T13r, T14r, and T15r to prevent distortion of the output signal LO1.

Here, the twelfth PMOS transistor T12r is connected between the output line of the first level shifter LS1, the QB node of the first stage ST1, and the first supply voltage VSS input line, and the thirteenth PMOS transistor ( T13r is connected between the QL node, the QB node, and the output line of the first level shifter LS1, and the fourteenth PMOS transistor T14r is connected to the output line of the first level shifter LS1 and the second PMOS transistor T2r. Is connected between the gate terminal of and a first supply voltage (VSS) input line. The fifteenth PMOS transistor T15r is diode-connected between the negative voltage VNEG input line and the source terminal of the ninth PMOS transistor T9r.

The first level shifter LS1 further includes a third capacitor CQL connected between the gate terminal and the source terminal of the tenth PMOS transistor T10r, that is, between the QL node and the output line.

As shown in FIG. 8, the first to fourth clock signals C1 to C4 having a phase delayed by one clock in sequence are shown in the first stage ST1 and the first level shifter LS1 having such a configuration. Is supplied. Here, the fourth clock signal C4 has a phase synchronized with the start pulse SP. The first to fourth clock signals C1 to C4 including the start pulse SP are supplied in a negative type having a swing voltage of 10 V or less. For convenience of explanation, a description will be given on the assumption that the potential of 10V is low and the potential of 0V is high. The operation of the first stage ST1 and the level shifter LS1 will be described with reference to the driving waveform as follows.

When the start pulse SP and the fourth clock signal C4 become high at the same time in the t1 period, the first and second PMOS transistors T1r and T2r are turned on so that the Q node has the first high state H1. The voltage is charged. Accordingly, the sixth and ninth PMOS transistors T6r and T9r having gate terminals connected to the Q nodes are gradually turned on. At this time, the fifth PMOS transistor T5r is turned on by the high state start pulse SP so that the low state (10V) voltage from the first supply voltage VSS input line is charged to the QB node. As a result, the third and seventh PMOS transistors T3r and T7r having gate terminals connected to the QB node are turned off. As a result, since the low state voltage 10V of the first clock signal C1 is charged to the output line of the first stage ST1 through the turned-on sixth PMOS transistor T6r, the first stage ST1 is low. The output signal SO1 of the state is output. In addition, as a diode, through a fifteenth PMOS transistor T15r turned on by a negative voltage VNEG of −8V and a ninth PMOS transistor T9r turned on by a Q node in a first high state H1. Since the negative voltage VNEG is precharged to the QL node, the tenth PMOS transistor T10r is weakly turned on. At the same time, since the fourteenth PMOS transistor T14r is turned on by the fourth clock signal C4 in the high state, the output of the first level shifter LS1 even if the tenth PMOS transistor T10r is weakly turned on. Since the line is charged with the first supply voltage Vss, the first level shifter LS1 outputs the output signal LO1 in a low state.

In the t2 period, when the start pulse SP and the fourth clock signal C4 go low and the first clock signal C1 goes high, the first and second PMOS transistors T1r and T2r are turned off. The sixth PMOS transistor T6r is turned on. Accordingly, the Q node in the floating state is in the high state of the first clock signal C1 under the influence of the internal capacitor Cgs and the first capacitor CQ formed between the gate and the source of the sixth PMOS transistor T6r. Bootstrapping due to voltage occurs and becomes a second high state H2 higher than the first high state H1. As a result, the sixth PMOS transistor T6r is reliably turned on so that the high voltage 0V of the first clock signal C1 is quickly charged to the output line of the stage ST1, so that the first stage ST1 is turned on. Outputs an output signal in a high state. In addition, the QL node is connected to the QL node by the fifteenth PMOS transistor T15r turned on by the negative voltage VNEG and the ninth PMOS transistor T9r that is turned on in accordance with the bootstrapped Q node. VNEG) is charged to reliably turn on the tenth PMOS transistor T10r. In this case, the QL node is also bootstrapping under the influence of the internal capacitor Cgs and the third capacitor CQL formed between the gate and the source of the tenth PMOS transistor T10r like the Q node, thereby providing the tenth PMOS transistor T10r. You can turn it on more reliably. Accordingly, since the negative voltage VNEG is charged to the output line of the first level shifter LS1 through the tenth PMOS transistor T10r that is surely turned on, the first level shifter LS1 outputs a high output signal. Will output (LO1).

When the first clock signal C1 becomes low and the second clock signal C2 becomes high in the t3 period, the voltage of the Q node transitions back to the first high state H1 and the sixth PMOS transistor T6r. As the low level voltage 10V of the first clock signal C1 is charged to the output line of the first stage ST1 as the turn-on state is maintained, the first stage ST1 is the output signal SO1 of the low state. ) Will be printed. In addition, since the eighth PMOS transistor T8r is turned on by the second clock signal C2 in the high state and the voltage of the QL node is discharged, the tenth PMOS transistor T10r is turned off. At the same time, since the eleventh PMOS transistor T11r is turned on by the second clock signal C2 in the high state, the first supply voltage VSS is charged to the output line of the first level shifter LS1 and thus the first level. The shifter LS1 outputs an output signal LO1 in a low state.

When the third clock signal C3 becomes high in the t4 period, the fourth PMOS transistor T4r is turned on to charge the QB node with the high voltage 0V, which is the second supply voltage VDD, to the third node. The seventh, twelfth, and thirteenth PMOS transistors T3r, T7r, T12r, and T13r are turned on at the same time. The low high voltage charged to the Q node via the turned-on third PMOS transistor T3r is discharged to the low state so that the sixth PMOS transistor T6r is turned off and the turned-on seventh PMOS transistor ( Since the first supply voltage VSS is charged to the output line of the first stage ST1 via T7r, the first stage ST1 outputs the output signal SO1 having a low state. In this case, the second capacitor CQB prevents the voltage of the QB node from being distorted by the leakage currents of the third and seventh PMOS transistors T3r and T7r. In addition, since the first supply voltage VSS is supplied to the first level shifter LS1 output line through the turned-on twelfth PMOS transistor T12r, the first level shifter LS1 is in the low state output signal LO1. Will print In this case, the thirteenth PMOS transistor T13r turned on by the high QB node prevents the QL node from floating by the ninth PMOS transistor T9r turned off. Accordingly, in the thirteenth PMOS transistor T13r, the output signal LO1 of the low state on the output line of the first level shifter LS1 is distorted by the leakage current in the turned-off tenth PMOS transistor T10r. It can be prevented.

When the fourth clock signal C4 becomes high in the t5 period, the second and fourteenth PMOS transistors T2r and T14r are turned on, and the first and fifth PMOS transistors T2r and T5r are turned off. The QB node will remain at its previous high state. Accordingly, as in the above-described t4 period, the third, seventh, twelfth, and thirteenth PMOS transistors T3r, T7r, T12r, and T13r are continuously turned on, so that the first stage ST1 and the first level shifter are maintained. The output signals SO1 and LO1 of the LS1 remain low.

As described above, the shift register having the above-described level shifter outputs a shift signal having a swing voltage of 10V or more using clock signals C1 to C4 and a start pulse SP having a swing voltage of 10V or less.

However, in the shift register incorporating the level shifter illustrated in FIG. 7, the voltages of the Q node in the first high state H1 and the second and fourth clock signals in the high state in the t1 and t3 periods of the level shifter LS1. The tenth and fourteenth PMOS transistors T10r and T14r or the tenth and eleventh PMOS transistors T10r and T11r of the level shifter LS1 are turned on at the same time by (C2 and C4). Accordingly, as the current path is formed through the tenth and fourteenth PMOS transistors T10r and T14r or the tenth and eleventh PMOS transistors T10r and T11r that are turned on in the periods t1 and t3, a static current is generated. ), And the constant current consumes power in the level shifter LS1.

In particular, the channel widths of the tenth, eleventh, and fourteenth PMOS transistors T10r, T11r, and T14r may include the falling time and the rising time of the output signal of the shift register, that is, the level shifter LS1 output signal LO1. Rising Time, Waveform Distortion and Power Consumption. Accordingly, in order to prevent distortion of the output signal LO1 of the level shifter LS1, the channel widths of the tenth, eleventh, and fourteenth PMOS transistors T10r, T11r, and T14r must be large. As a result, since the channel widths of the tenth, eleventh, and fourteenth PMOS transistors T10r, T11r, and T14r forming the constant current path must be large, the amount of constant current increases, and power consumption of the level shifter LS1 is further increased. Will increase.

In order to reduce power consumption due to the constant current in the level shifter, the shift register incorporating the level shifter according to the present invention outputs the output signal SO of the stage ST instead of the voltage of the Q node as shown in FIG. It is supplied as an input signal. Hereinafter, a shift register incorporating a level shifter according to an embodiment of the present invention capable of reducing power consumption will be described in detail with reference to FIGS. 9 to 11.

FIG. 9 illustrates a detailed circuit configuration of a shift register incorporating a level shifter according to an exemplary embodiment of the present invention, and illustrates one stage ST and a level shifter LS of the shift register circuit.

The stage ST shown in FIG. 9 has the same configuration as the first stage ST1 shown in FIG. 7. In other words, the stage ST shown in FIG. 9 includes a first PMOS transistor T1, a first PMOS transistor T1, and a fourth clock signal C4, which are diode-connected to the start pulse SP input line. A first PMOS transistor T2 connected between the input line and the Q node, and a third PMOS transistor T3 connected between the Q node and the QB node and the first supply voltage VSS input line. A controller 60; Fourth PMOS transistor T4 connected between the second supply voltage VDD input line, the third clock signal C3 input line, and the QB node, and the fourth PMOS transistor T4 and the start pulse SP input line. And a second controller 62 having a fifth PMOS transistor T5 connected between the first supply voltage VSS input line; The sixth PMOS transistor T6 selects and supplies the first clock signal C1 to the output line according to the voltage of the Q node, and selects and supplies the first supply voltage VSS to the output line according to the voltage of the QB node. The buffer unit 64 includes a seventh PMOS transistor T7. The stage ST includes the first capacitor CQ connected between the gate terminal and the source terminal of the sixth PMOS transistor T6, that is, between the Q node and the output line P of the stage ST, and the seventh stage. A second capacitor CQB is further provided between the gate terminal and the source terminal of the PMOS transistor T7, that is, between the QB node and the first supply voltage VSS input line.

The level shifter LS controls the QL1 node and the QL2 node according to the output signal SO of the stage ST output line P and the fourth clock signal C4 (or the output signal of the previous stage). 66 and select one of the negative voltage VNEG and the first supply voltage VSS according to the voltage of the QL1 node and the second clock signal C2 (or the output signal of the next stage). An output buffer section 68 is provided.

The third controller 66 charges and discharges the QL1 and QL2 nodes according to the output voltage SO of the stage ST output line P and the fourth clock signal C4 (or the output signal of the previous stage). The buffer unit 68 outputs the negative voltage VNEG or the first supply voltage VSS. To this end, the third controller 66 includes an eighth PMOS transistor T8 connected between the negative voltage VNEG supply line and the output line P and the QL1 node of the stage ST, the QL1 node and the fourth node. Input the ninth PMOS transistor T9 connected between the clock signal C4 (or the output signal of the previous stage) input line and the QL2 node, and the QL2 node and the fourth clock signal C4 (or the output signal of the previous stage). And a tenth PMOS transistor T10 connected between the line and the first supply voltage VSS.

The output buffer 68 uses the two-stage bootstrapping according to the voltage of the QL1 node to supply the negative supply voltage VNEG to the level shifter LS output line, and the eleventh and twelfth PMOS transistors T11 and T12. And a thirteenth PMOS transistor T13 as the output line of the level shifter LS with the first supply voltage VSS according to the second clock signal C2 (or the output signal of the next stage). In particular, the output buffer unit 68 may include a third capacitor CL1 connected between the gate terminal and the source terminal of the eleventh PMOS transistor T11, that is, between the QL1 node and the QL2 node in order to use two-stage bootstrapping; And a fourth capacitor CL2 connected between the QL2 node and the source terminal of the twelfth PMOS transistor T12.

The level shifter LS further includes fourteenth to eighteenth PMOS transistors T14 to T18 to prevent distortion of the output signal LO.

Specifically, the fourteenth and fifteenth PMOS transistors T14 and T15 control the QL1 node and the QL2 node in response to the second clock signal C2 (or the output signal of the next stage). For this purpose, a fourteenth PMOS transistor T14 is connected between a QL1 node and a second clock signal C2 (or an output signal of a next stage) input line and a QL2 node, and the fifteenth PMOS transistor T15 is a QL2 node. And a second clock signal C2 (or an output signal of a next stage) input line and a first supply voltage VSS input line.

The sixteenth and seventeenth PMOS transistors T16 and T17 control the QL1 node and the QL2 node in response to the voltage of the QB node. For this purpose, a sixteenth PMOS transistor T16 is connected between a QL1 node, a QB node and a QL2 node, and a seventeenth PMOS transistor T17 is connected between a QL2 node, a QB node and a first supply voltage VSS input line. do.

An eighteenth PMOS transistor T18 is connected between the output line and the QB node and the first supply voltage VSS input line to discharge the level shifter LS output line.

In addition, the nineteenth PMOS transistor T19 is diode-connected between the negative voltage VNEG input line and the source terminal of the eighth PMOS transistor T8 to prevent leakage current of the eighth transistor T8. .

As shown in FIG. 10, the stages ST and the level shifters LS having such a configuration are supplied with the first to fourth clock signals C1 to C4 having a phase delayed by one clock. Here, the fourth clock signal C4 has a phase synchronized with the start pulse SP. The first to fourth clock signals C1 to C4 including the start pulse SP are supplied in a negative type having a swing voltage of 10 V or less. In particular, it is assumed here that the potential of 10 V is low and the potential of 0 V is high. The operation of the stage ST and the level shifter LS with reference to the driving waveform is as follows.

When the start pulse SP and the fourth clock signal C4 become low at the same time in the t1 period, the first and second PMOS transistors T1 and T2 of the stage ST are turned on so that the Q node has a first high state. The voltage of state H1 is charged. As a result, the sixth PMOS transistor T6 having the gate terminal connected to the Q node is gradually turned on. The fifth PMOS transistor T5 is turned on by the high start pulse SP to charge the QB node with the low state (10V) voltage from the first supply voltage VSS input line. Accordingly, the third PMOS transistor T3 and the seventh PMOS transistor T7 having the gate terminal connected to the QB node are turned off. As a result, since the low state voltage 10V of the first clock signal C1 is charged to the output line P of the stage ST through the turned-on sixth PMOS transistor T6, the stage ST is in a high state. The output signal SO is outputted.

The eighth PMOS transistor T8 is turned off by the high state output signal SO of the stage ST, and the eighth PMOS transistor T8 is turned off by the fourth clock signal C4 (or the output signal of the previous stage) of the low state. The ninth and tenth PMOS transistors T9 and T10 are turned on so that the QL1 node and the QL2 node are charged with a high state (10 V) from the first supply voltage VSS input line. Accordingly, since the eleventh and twelfth PMOS transistors T11 and T12 are turned off, the output signal of the level shifter LS maintains the previous state (ie, the high state).

When the start pulse SP goes high, the fourth clock signal C4 goes low, and the first clock signal C1 goes high in the period t2, the first PMOS transistor T1 is turned off and the first PMOS transistor T1 is turned off. The 2 PMOS transistor T2 is turned on so that the Q node is in a floating state, and the sixth PMOS transistor T6 is maintained in a turned on state. In this case, the Q node in the floating state is the voltage of the high state of the first clock signal C1 due to the influence of the internal capacitor Cgs and the first capacitor CQ formed between the gate and the source of the sixth PMOS transistor T6. Bootstrapping occurs due to the second high state H2 that is higher than the first high state H1. As a result, the sixth PMOS transistor T6 is reliably turned on so that the high state voltage 0V of the first clock signal C1 is quickly charged to the output line P of the stage ST, so that the stage ST Outputs a good low state output signal SO.

The eighth PMOS transistor T8 is turned on by the low state output signal SO of the stage ST. Accordingly, the nineteenth PMOS transistor T19 turned on by the negative polarity voltage VNEG in the low state and the eighth PMOS transistor T8 turned on by the low state output signal SO of the stage ST. The 11 th PMOS transistor T11 is turned on because the negative voltage VNEG of the low state is charged to the QL1 node through the. Subsequently, since the negative voltage VNEG of the low state input through the turned-on nineteenth PMOS transistor T19 through the turned-on eleventh PMOS transistor T11 is input to the QL2 node, the twelfth PMOS transistor T12 is input. ) Is turned on. In this case, the QL1 node and the QL2 node are in the floating state by the turned-off ninth, tenth, fifteenth, and seventeenth PMOS transistors T9, T10, T15, and T17, and the third and fourth capacitors connected in series. The bootstrapping phenomenon caused by (CL1, CL2) results in a higher high state.

Specifically, the negative input input to the QL2 node through the eleventh PMOS transistor T11 is influenced by the internal capacitor Cgs and the third capacitor CL1 formed between the gate and the source of the eleventh PMOS transistor T11. Since the bootstrapping phenomenon due to the polarity voltage VNEG occurs, the eleventh PMOS transistor T11 is surely turned on. In addition, since the current flowing into the QL2 node is increased through the eleventh PMOS transistor T11 that is turned on, the twelfth PMOS transistor T12 is turned on at a high speed so that the negative voltage VNEG rapidly increases the level shifter LS. Is charged to the output line. In addition, since bootstrapping occurs due to the influence of the internal capacitor Cgs and the fourth capacitor CL2 formed between the gate and the source of the twelfth PMOS transistor T12, the twelfth PMOS transistor T12 is reliably turned on. -Turn it on. Thus, the output line of the level shifter LS is turned high through the twelfth PMOS transistor T12 that is reliably turned on at high speed by two-stage bootstrapping using the third and fourth capacitors CL1 and CL2 connected in series. The negative voltage VNEG of is quickly charged. As a result, since the rising time and the falling time of the output signal LO of the level shifter LS are small, the output buffer 68 is operated at high speed. In addition, the output buffer unit 68 uses the two-stage bootstrapping phenomenon even if a voltage loss occurs at an internal node due to a high threshold voltage Vth of the eleventh and twelfth PMOS transistors T11 and T12. ) Can be operated at high speed. Therefore, the output signal LO of the level shifter LS has a signal waveform in a good low state.

In the t3 period, the second clock signal C2 goes low and the first clock signal C1 goes high. The voltage of the Q node in the floating state is dropped to the first high state H1 by the first clock signal C1 in the high state, and the sixth PMOS transistor T6 maintains the turn-on state. Accordingly, since the first clock signal C1 of the high state is charged to the output line P of the stage ST via the turned-on sixth PMOS transistor T6, the stage ST is the output signal of the high state. Will output (SO). The eighth PMOS transistor T8 is turned off by the high state output signal SO of the stage ST. In this case, the voltages of the QL1 node and the QL2 node are discharged through the 14th and 15th PMOS transistors T14 and T15 turned on by the second clock signal C2 (or the output signal of the next stage) in the low state. Therefore, the eleventh and twelfth PMOS transistors T11 and T12 are turned off. In addition, a first supply in a low state to the output line of the level shifter LS through the thirteenth PMOS transistor T13 turned on by the second clock signal C2 in the low state (or an output signal of the next stage). Since the voltage VSS is charged, the level shifter LS outputs the high output signal LO.

When the third clock signal C3 becomes low in the t4 period, the fourth PMOS transistor T4 is turned on to charge the QB node with the high voltage 0V, which is the second supply voltage VDD. Accordingly, the sixth PMOS transistor T6 is turned on by turning on the third PMOS transistor T3 to discharge the Q node voltage having the first high state H1 to the low state in the period t3. Since the first supply voltage VSS is charged to the output line of the stage ST through the seventh PMOS transistor T7 turned on by the QB node in the low state, the stage ST output signal ( SO) will be output. The eighth PMOS transistor T8 is turned off by the high state output signal SO of the stage ST. In this case, the QL1 node and the QL2 node remain high by the first supply voltage VSS supplied through the sixteenth and seventeenth PMOS transistors T16 and T17 turned on by the voltage of the QB node in the low state. Thus, the eleventh and twelfth PMOS transistors T11 and T12 are turned off. In addition, since the output line of the level shifter LS is charged to the output line of the level shifter LS through the eighteenth PMOS transistor T18 turned on by the voltage of the QB node in the low state, the level shifter LS is charged. The output signal LO of the high state is output.

When the fourth clock signal C4 is low in the t5 period and the third clock signal C4 is in the high state, the fourth PMOS transistor T4 is turned off and the QB node maintains the low state in the t4 period. do. Accordingly, since the Q-node low state is maintained by the turned-on third PMOS transistor T3, the sixth PMOS transistor T6 is continuously turned on and the first through the turned-on seventh PMOS transistor T7. Since the supply voltage VSS is charged to the output line of the stage ST, the stage ST outputs the output signal SO in a high state. The eighth PMOS transistor T8 is turned off by the high state output signal SO of the stage ST. In this case, since the ninth and tenth PMOS transistors T9 and T10 are turned on by the fourth clock signal C4 (or the output signal of the previous stage) in the low state, the QL1 is applied by the first supply voltage VSS. Since the node and the QL2 node are kept low, the eleventh and twelfth PMOS transistors T11 and T12 are turned on. In addition, since the output line of the level shifter LS is charged to the output line of the level shifter LS through the eighteenth PMOS transistor T18 turned on by the voltage of the QB node in the low state, the level shifter LS is charged. The output signal LO of the high state is output.

As described above, in the shift register incorporating the level shifter according to the first exemplary embodiment of the present invention, an eighth controlling the output buffer unit 68 of the level shifter LS using the output signal SO of the stage ST is performed. The PMOS transistor T8 is driven. Accordingly, the eighth PMOS transistor T8 is turned on only in a section in which the output signal SO of the stage ST is in a high state, and is turned off in the remaining sections, and thus is a constant current consumed through the output buffer unit 68. Can be reduced. In particular, the output buffer unit 68 of the level shifter LS is two-stage bootstrapping using the third and fourth capacitors CL1 and CL2 connected in series, even when the threshold voltage Vth of the PMOS transistor is high. Thus, a good output signal LO can be output.

11 illustrates a detailed circuit configuration of a shift register incorporating a level shifter according to a second embodiment of the present invention.

The shift register shown in FIG. 11 is a twentieth PMOS transistor for separating the third and fourth capacitors CL1 and CL2 from the level shifter LS output buffer unit 78 as compared with the shift register shown in FIG. 9. The same components are provided except that T20) is added. Here, the twentieth PMOS transistor T20 is to prevent the bootstrapping voltage from falling due to the influence of each other by separating the third and fourth capacitors CL1 and CL2.
That is, the shift register shown in FIG. 11 includes the first control unit 60, the second control unit 62, the buffer unit 64, and the third control unit 66 as in FIG. 9.
Accordingly, in the following, the period during which the output buffer section 78 of the level shifter LS shown in FIG. 11 outputs a good high state output signal LO using two-stage bootstrapping, that is, shown in FIG. Only the operation process of the shift register in the specified t2 period will be described.

When the start pulse SP goes high, the fourth clock signal C4 goes low, and the first clock signal C1 goes high in the period t2, the first PMOS transistor T1 is turned off and the first PMOS transistor T1 is turned off. The 2 PMOS transistor T2 is turned on so that the Q node is in a floating state, and the sixth PMOS transistor T6 is maintained in a turned on state. In this case, the Q node in the floating state is the voltage of the high state of the first clock signal C1 due to the influence of the internal capacitor Cgs and the first capacitor CQ formed between the gate and the source of the sixth PMOS transistor T6. Bootstrapping occurs due to the second high state H2 that is higher than the first high state H1. As a result, the sixth PMOS transistor T6 is reliably turned on so that the high state voltage 0V of the first clock signal C1 is quickly charged to the output line P of the stage ST, so that the stage ST Outputs a good low state output signal SO.

The eighth PMOS transistor T8 is turned on by the low state output signal SO of the stage ST. Accordingly, the nineteenth PMOS transistor T19 turned on by the negative polarity voltage VNEG in the low state and the eighth PMOS transistor T8 turned on by the low state output signal SO of the stage ST. The 11 th PMOS transistor T11 is turned on because the negative voltage VNEG of the low state is charged to the QL1 node through the. Subsequently, a low negative voltage VNEG input through the turned-on eleventh PMOS transistor T11 through the turned-on eleventh PMOS transistor T11 is applied to the gate electrode of the twentieth PMOS transistor T20. Since the 20 th PMOS transistor T20 is turned on. The twelfth PMOS transistor T12 is turned on because the negative voltage VNEG of the low state is input to the QL2 node via the turned-on twentieth PMOS transistor T20. In this case, the QL1 node and the QL2 node are in a floating state by the turned-off ninth, tenth, fifteenth and seventeenth PMOS transistors T9, T10, T15, and T17, and the third and fourth capacitors CL1. , A bootstrapping phenomenon caused by CL2) results in a higher high state.

Specifically, the negative input input to the QL2 node through the eleventh PMOS transistor T11 is influenced by the internal capacitor Cgs and the third capacitor CL1 formed between the gate and the source of the eleventh PMOS transistor T11. Since the bootstrapping phenomenon due to the polarity voltage VNEG occurs, the eleventh PMOS transistor T11 is surely turned on. Further, since the current flowing into the gate electrode of the twentieth PMOS transistor T20 is increased through the eleventh PMOS transistor T11 turned on, the twentieth PMOS transistor T20 is also turned on. In addition, since the current flowing into the QL2 node is increased by the twentieth PMOS transistor T20 which is certainly turned on, the twelfth PMOS transistor T12 is turned on at a high speed so that the negative voltage VNEG is rapidly increased. Is charged to the output line. In addition, since bootstrapping occurs due to the influence of the internal capacitor Cgs and the fourth capacitor CL2 formed between the gate and the source of the twelfth PMOS transistor T12, the twelfth PMOS transistor T12 is reliably turned on. -Turn it on. A high state is provided at the output line of the level shifter LS through the twelfth PMOS transistor T12 that is reliably turned on at high speed by two-stage bootstrapping using the third and fourth capacitors CL1 and CL2 separated from each other. The negative voltage VNEG of is quickly charged. As a result, since the rising time and the falling time of the output signal LO of the level shifter LS are small, the output buffer 68 is operated at high speed. In addition, the output buffer unit 78 uses the two-stage bootstrapping phenomenon even if a voltage loss occurs at an internal node due to high threshold voltages Vth of the eleventh and twelfth PMOS transistors T11 and T12. ) Can be operated at high speed. Therefore, the output signal LO of the level shifter LS has a good high signal waveform.

As described above, in the shift register incorporating the level shifter according to the second exemplary embodiment of the present invention, the eighth control unit 78 controls the output buffer unit 78 of the level shifter LS using the output signal SO of the stage ST. The PMOS transistor T8 is driven. Accordingly, the eighth PMOS transistor T8 is turned on only in the section in which the output signal SO of the stage ST is turned low and turned off in the remaining section, so that the constant current is consumed through the output buffer unit 78. Can be reduced. In particular, the output buffer unit 78 of the level shifter LS is a two-stage bootstrapping using the third and fourth capacitors CL1 and CL2, and is driven at a high speed even when the threshold voltage Vth of the PMOS transistor is high. The signal LO can be output. Also, since the third and fourth capacitors CL1 and CL2 for bootstrapping are separated from each other through the twentieth PMOS transistor T20, the output buffer unit 78 of the level shifter LS has two capacitors CL1 and CL2. It is possible to drive at high speed without affecting the liver.

The shift register with a built-in level shifter according to the present invention is applied not only to a liquid crystal display device using polysilicon but also to a gate (scan) driver and a data driver of an EL display device. It can be built into the panel.

As described above, the shift register incorporating the level shifter according to the present invention can reduce the constant current consumed through the output buffer by controlling the output buffer of the level shifter using the output signal of the stage. Accordingly, according to the shift register incorporating the level shifter according to the present invention, power consumption can be reduced.

In addition, the shift register incorporating the level shifter according to the present invention can be driven at high speed even when the threshold voltage Vth of the transistor is high by two-stage bootstrapping using two capacitors connected in series to output a good output signal.

In addition, the shift register incorporating the level shifter according to the present invention can be driven at high speed without the influence between the capacitors by separating the two capacitors for two-stage bootstrapping using a transistor.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (32)

delete delete delete delete Controlling the voltages of the first and second nodes using the first and second supply voltages according to the input signal and the first control signal, the first conductive path between the input line of the second supply voltage and the first node. A first transistor for controlling a voltage according to the input signal, a second transistor for controlling a second conductive path between the first node and a second node according to the first control signal, and the second node and the first supply. A control unit including a third transistor configured to control a third conductive path between input lines of a voltage according to the first control signal; A fourth transistor for controlling a fourth conductive path between the input line of the second supply voltage and the second node according to the voltage of the first node, and a fifth conductivity between the input line and the output terminal of the second supply voltage A fifth transistor for controlling a path according to the voltage of the second node, a sixth transistor for controlling a sixth conductive path between the output terminal and an input line of the first supply voltage according to a second control signal, and the first And an output buffer including a first capacitor connected between the node and the second node, and a second capacitor connected between the second node and the output terminal. In the level shifter for level shifting the output signal, Controlling the voltages of the first and second nodes using first and second supply voltages according to the input signal and the first control signal, and a first conductivity between the input line of the second supply voltage and the first node. A first transistor for controlling a path according to the input signal, a second transistor for controlling a second conductive path between the first node and a second node according to the first control signal, and the second node and the first node A control unit including a third transistor configured to control a third conductive path between input lines of a supply voltage according to the first control signal; A fourth transistor for controlling a fourth conductive path between the input line of the second supply voltage and the second node according to the voltage of the first node, and a fifth conductivity between the input line and the output terminal of the second supply voltage A fifth transistor for controlling a path according to the voltage of the second node, a sixth transistor for controlling a sixth conductive path between the output terminal and an input line of the first supply voltage according to a second control signal, and the second A seventh transistor for controlling a seventh conductive path between an input line of a supply voltage and the second node according to an output voltage of the fourth transistor, a first connected between the first node and an output terminal of the fourth transistor And an output buffer section including a capacitor and a second capacitor connected between the second node and the output terminal. delete The method according to claim 5 or 6, And the transistors of the control unit and the output buffer unit are transistors of the same channel type. The method according to claim 5 or 6, The output buffer unit And selectively outputting the first supply voltage equal to the first voltage of the input signal and the second supply voltage different from the second voltage of the input signal. The method according to claim 5 or 6, The first control signal has the second voltage before the input signal is changed from the first voltage to the second voltage, and the second control signal is the input signal from the second voltage to the first voltage. And having said second voltage after being converted. A buffer unit configured to output a shift pulse using a first control signal and a first supply voltage according to voltages of the first and second nodes, and to control a voltage of the first node according to a start pulse and a voltage of the second node. A first controller and a second controller configured to control the voltage of the second node by using the first supply voltage and the second supply voltage according to the start pulse and the second control signal. A plurality of stages for shifting the start pulse to sequentially output the shift pulse; A third controller for controlling voltages of the third and fourth nodes using a third supply voltage and the first supply voltage according to the shift pulse output from the buffer unit and a third control signal, and the third node and the The third and fourth node voltages are bootstrapped in at least two stages using at least two capacitors connected between the output lines of the level shifter with the fourth node interposed therebetween, and the third bootstraped in the at least two stages. And a level shifter including an output buffer unit for selectively outputting the first and third supply voltages according to a voltage of a fourth node and a fourth control signal. The method of claim 11, The first control unit A first transistor having a conductive passage between the start pulse and the first node, and a control electrode controlling the conductive passage according to the start pulse; A second transistor having a conductive passage between an output terminal of the first transistor and the first node, and a control electrode controlling the conductive passage according to a third control signal; And a third transistor having a conductive passage between the first node and the input line of the first supply voltage and a control electrode for controlling the conductive passage according to the voltage of the second node. Built-in shift register. The method of claim 12, The second control unit A fourth transistor having a conductive passage between the second supply voltage input line and the second node and a control electrode controlling the conductive passage according to the second control signal; And a fifth transistor having a conductive passage between the second node and the first supply voltage input line and a control electrode for controlling the conductive passage according to the start pulse. . The method of claim 13, The buffer unit A sixth transistor having a conductive path between the first control signal input line and an output line of the stage, and a control electrode controlling the conductive path according to the voltage of the first node; And a seventh transistor having a conductive passage between the output line of the stage and the first supply voltage input line and a control electrode for controlling the conductive passage according to the voltage of the second node. Built-in shift register. The method of claim 14, The buffer unit And a capacitor connected between the control electrode of the sixth transistor and the output line of the stage, for further bootstrapping the voltage of the control electrode. The method of claim 14, The stage is And a capacitor for preventing a voltage distortion of the second node due to the leakage current of the fifth transistor. The method of claim 14, The third control unit An eighth transistor having a conductive path between the input line of the third supply voltage and the third node and a control electrode controlling the conductive path according to an output signal of the stage; A ninth transistor having a conductive path between the third node and a fourth node and a control electrode for controlling the conductive path according to the third control signal; And a tenth transistor having a conductive path between the fourth node and the input line of the first supply voltage and a control electrode for controlling the conductive path according to the third control signal. One shift register. The method of claim 11, The output buffer unit An eleventh transistor having a conductive path between the third supply voltage input line and the fourth node and a control electrode controlling the conductive path according to the voltage of the third node; A twelfth transistor having a conductive path between the third supply voltage input line and an output line of the level shifter and a control electrode controlling the conductive path according to the voltage of the fourth node; And a thirteenth transistor having a conductive path between an output line of the level shifter and the first supply voltage input line and a control electrode for controlling the conductive path according to the fourth control signal. Shift register with built-in level shifter. The method of claim 18, The level shifter A fourteenth transistor configured to control a conductive path between the third and fourth nodes and the conductive path according to the fourth control signal; And a fifteenth transistor configured to control a conductive path between the fourth node and the first supply voltage input line and the conductive path according to the fourth control signal. . The method of claim 19, The level shifter is A sixteenth transistor configured to control a conductive path between the third and fourth nodes and the conductive path according to a voltage of the second node; A seventeenth transistor for controlling a conductive path between the fourth node and the first supply voltage input line and controlling the conductive path according to the second node voltage; And a conductive path between the output line of the level shifter and the first supply voltage input line and an eighteenth transistor for controlling the conductive path according to the voltage of the second node. One shift register. The method of claim 20, The level shifter And a nineteenth transistor diode-connected between the input line of the third supply voltage and the eighth transistor, further comprising a level shifter. delete The method of claim 21, The output buffer unit A first capacitor connected between the third node and a fourth node for bootstrapping the third node by the third supply voltage supplied to the fourth node through the eleventh transistor; And a second capacitor connected to the fourth node and the output line for bootstrapping the fourth node by the third supply voltage supplied to the output line through the twelfth transistor. Shift register with built-in level shifter. The method of claim 21, The output buffer unit A conductive path between the input line of the third supply voltage and the second node and the conductive path to the voltage of the eleventh transistor output terminal to electrically separate the output terminal of the eleventh transistor from the fourth node; A shift register with a level shifter, further comprising a twentieth transistor having a control electrode for controlling accordingly. The method of claim 24, The output buffer unit A first capacitor connected between the third node and an output terminal of the eleventh transistor for bootstrapping the third node by the third supply voltage supplied through the eleventh transistor to its output terminal; And a second capacitor connected to the third node and the output line for bootstrapping the fourth node by the third supply voltage supplied to the output line through the twelfth transistor. Shift register with built-in level shifter. The method of claim 11, And said stages and level shifters comprise only thin film transistors of the same type channel. The method of claim 11, And the first to third supply voltages have a relationship of a third supply voltage <second supply voltage <first supply voltage. The method of claim 27, And the third supply voltage is a negative voltage. delete The method of claim 11, And said stages and level shifters comprise only a thin film transistor of a P channel. The method of claim 11, The level shifter And shifting the lowest voltage level of the shift pulse to the third supply voltage to output the shifted voltage. The method of claim 11, And the shift register is applied to at least one of a scan driver for driving the scan lines of the display device and a data driver for driving the data lines of the display device.

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