KR100704016B1 - Data driver for liquid crystal display - Google Patents

Abstract

The present invention relates to a data driver among driving circuits for driving a liquid crystal display device, and more particularly to a data driver of a digital interface driving method.

A data driver of a liquid crystal display according to the present invention includes a shift register array for supplying a sampling signal, a latch array for latching and outputting video data in response to the sampling signal, and a corresponding data line according to an output signal of the latch array. And a transmission gate array for outputting an analog voltage to a corresponding data line according to an output signal of the decoder array.

Data drivers, polycrystalline thin film transistors, boot-strapping,

Description

DATA DRIVER FOR LIQUID CRYSTAL DISPLAY}             

1 is a block diagram showing a configuration of a general liquid crystal display device;

2 is a view showing a configuration example of a data driver according to the present invention;

3 is a view showing a configuration example of an inverter circuit necessary to implement a data latch composed of only a P-type thin film transistor according to the present invention;

4 is a timing diagram of FIG.

5A is a measurement result diagram showing a result of applying a signal to the circuit of FIG. 3;

5B is a level shifter measurement result showing a result of applying a lower Vss signal to the circuit of FIG.

6 is a circuit diagram of a switching inverter used in the latch circuit of the present invention;

7 is a view illustrating an example in which a latch is configured by complementarily connecting the switching inverters of FIG. 6;

8 is a circuit diagram of a decoder according to the present invention;

9 is a view showing a configuration example of a NAND gate circuit according to the present invention;

10 is a view showing another configuration example of a NAND gate circuit according to the present invention;

11 is a circuit diagram of a transmission gate according to the present invention;

12A is an exemplary diagram of a transfer gate composed of only P-type transistors;

12B is a circuit diagram of a general CMOS transfer gate,

13 is a circuit diagram of a transmission gate according to the present invention;

14 is a simulation result diagram showing the output characteristics of the D / A converter according to the present invention,

15 is a timing diagram of FIG. 2.

The present invention relates to a data driver among driving circuits for driving a liquid crystal display.

When implementing an active matrix liquid crystal display or an organic EL display, research is being conducted on integrating a display pixel panel and a driving circuit panel for driving the same.

The driving circuit integration technology currently being researched is mainly focused on embedding two circuits in a panel. First, design a shift resister that selects each line of the pixel array in the pixel panel; and second, the thin film transistor of the pixel pixel with the voltage (3.3V to 5V level) output from the chipset. (Thin Film Transistor: hereinafter referred to as TFT) A level shifter that promotes to a voltage for switching is designed and incorporated into a TFT. In order to design a driving circuit unit integrated in such a panel, a CMOS type using an N-type and a P-type polysilicon TFT is currently used, and a general CMOS logic is used.

However, CMOS type circuits require a large number of masks when making N-type and P-type transistors together, and an additional process is required to match the threshold voltages respectively. This is a major reason for lowering process yields and increasing process costs, and can also lead to reproducibility problems with poor operation reliability of the circuit. In general, N-type TFTs are known to exhibit severe degradation due to thermal damage due to hot carriers when driving devices, compared to P-types. Therefore, when designing a driving circuit part using a CMOS circuit using a polysilicon TFT, it is necessary to prevent deterioration caused by an N-type device, and for this purpose, an LDD process is added. As a result, an additional process is required to ensure the stability of the circuit driving, and since the LDD process itself is generally reported as a factor that significantly lowers the process yield, a circuit that does not use an N-type polysilicon thin film transistor is preferably used. Design is required.

Accordingly, an object of the present invention is to provide a data driver of a liquid crystal display device employing a latch array and a transfer gate array that can be implemented only with a P-type transistor.
Another object of the present invention is to provide a data driver of a digital interface driving method for receiving digital information from the outside and applying analog data to a panel array.

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A data driver of a liquid crystal display according to the present invention includes a shift register array for supplying a sampling signal, a latch array for latching and outputting video data in response to the sampling signal, and a corresponding data line according to an output signal of the latch array. And a transmission gate array configured to output an analog voltage to a corresponding data line according to an output signal of the decoder array.
Preferably, each latch of the latch array is configured by complementarily connecting inverters implemented with P-type transistors, and each decoder of the decoder array is implemented with a 4-bit NAND gate.
Preferably, the analog voltage is selectively obtained from a voltage source consisting of a resistor string.
More preferably, each of the transfer gates of the transfer gate array includes a capacitor connected to an output terminal of the decoder and a current path formed between the capacitor and the voltage source, and receiving a reset signal supplied from an external chipset as a gate. A second P-type transistor receiving a P-type transistor and an output signal of the capacitor as a gate, and having a source connected to the voltage source, wherein the second P-type transistor is applied to an input voltage from the voltage source; It is characterized in that to maintain the gate-source voltage of the constant.
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that the same components in the drawings are represented by the same reference numerals and symbols as much as possible even though they are shown in different drawings. In addition, in describing the present invention, when it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

1 is a block diagram showing a configuration of a liquid crystal display device to which the data driver of the present invention is applied, wherein the liquid crystal display device includes a liquid crystal panel 1 in which liquid crystal cells are arranged in a matrix, and a gate line of the liquid crystal panel 1. Gate driver 2 for driving the fields GL1 to GLn, data driver 3 for driving the data lines DL1 to DLm of the liquid crystal panel 1, and the gate driver 2 and the data driver ( The timing control part 4 for controlling 3) is provided.

2 is a diagram showing an example of the configuration of the data driver 3 according to the present invention.

Referring to FIG. 2, the data driver 3 includes a shift register 100, a data latch 200, and a digital / analog (D / A) converter 300. In addition, an output buffer (not shown) may be further provided to signal-buffer the output signals of the D / A converter 300 to each of the data lines.

The shift register 100 sequentially supplies sampling signals when information representing a data voltage is input as a digital value. The data voltage must be delivered to each pixel corresponding to one gate line. Since the actual data voltage values are sequentially introduced through the wiring line, a shift register is needed to distribute each pixel voltage to each latch. .

The data latch 200 includes a first latch 210 and a second latch 220, and latches and outputs video data in response to a sampling signal. The operation signals SWA1, SWA2, and SWA3 of the first latch 210 utilize the control signals SR.n, SR.n + 1, and SR.n + 2 of the shift register, and the second latch 220 The operation signals SWB1, SWB2, and SWB3 are provided through external drive circuits. In general, the CMOS latch circuit is connected to the switching inverter complementary to the stable output of the input voltage. In the present invention, only the P-type transistor is used to configure the operation corresponding to the CMOS circuit.

The basic inverter required to implement the data latch can be applied to the inverter circuit proposed in the application number 2002-63570 and the application number 2002-84147.
3 shows an example of the configuration of the inverter circuit required to implement a data latch consisting of only the P-type thin film transistor according to the present invention, Figure 4 is a timing diagram of FIG. In FIG. 3, T1 and T2 are transistors for outputting Vss and Vdd, and T3 and T4 are transistors for switching T1 and T2. When the input signal SW is low and the input signal IN is high, T2 and T4 are turned on, and T1 and T3 are turned off to output high (Vd) inverted with respect to the input signal low. Conversely, when the input signal SW is high and the input signal IN is low, T2 and T4 are turned off.
Meanwhile, T3 is turned off after lowering the voltage of node A between V3 and T4 to V _IN + Vth while maintaining the turn-on state in the saturation region. As such, when node A is lowered, T1 is turned on in the saturation region so that the voltage of the output node is lowered toward Vss. At this time, since node A is electrically floating, T1 is continuously turned on by boot-strapping. Therefore, the voltage of the output node can be continuously lowered and can reach Vss, resulting in low (Vss) inverted with respect to the input signal high.
FIG. 5A shows a measurement result of fabricating such an inverter circuit for input power sources Vdd (10V) and Vss (0V) and input signals (0 to 10V) using a P-type polycrystalline thin film transistor. In addition, if a level-shifted voltage is required for the input voltage, the level shifter may be implemented by setting the Vss value lower than the low voltage of the input signal. FIG. 5B shows the result of the level shifter measurement when the Vss value is set lower (-10V) in the inverter circuit of FIG. 3.

6 is a circuit diagram of a switching inverter used in the latch circuit of the present invention. The method of inverting the input signal IN is the same as the inverter mentioned above, but the output value is controlled using the input signal RS. When the RS signal is low, if the IN signal is low, the output is high. If the IN signal is high, the output terminal value is maintained. When the RS signal goes high, the inverter is operated by the IN and SW signals.

FIG. 7 illustrates an example in which a latch is configured by complementarily connecting the switching inverters of FIG. 6. The switch signal SW1 serves to turn on the gate that receives the external input IN signal into the latch circuit and also serves as the RS signal of FIG. 6 to control the output of the switching inverter. SW2 and SW3 each serve as the SW signal of FIG. 6 for operating the inverter. As a result, the inverted value of the IN signal can be stored using the latch circuit of FIG. 7 composed of only the P-type transistor.

The D / A converter 300 converts digital data input from the data latch 200 into an analog voltage. The D / A converter 300 includes a decoder 310 and a transmission gate T / G 320.

8 is a circuit diagram of the decoder 310, which is an example of a 4-bit decoder implemented using a 4-bit NAND gate. Each of the signals input to the NAND gate is 8 of D ₀ D ₁ D ₂ D ₃ D ₀ 'D ₁ ' D ₂ 'D ₃ ' and four of them are selected and applied to the ABCD input terminal. As a result, only one of the 16 NAND gates configured to receive four bits outputs low and the other 15 outputs high.

9 and 10 show a configuration example of a NAND gate circuit. NAND gate is a circuit that outputs low when all input signals are high. It is useful when implementing a decoder circuit that receives an n-bit signal and selects a desired output stage.

FIG. 9 is a circuit for performing NAND operation by receiving four input signals ABCD and four A'B'C'D 'signals having inverted forms as input signals. If any of the input signals ABCD is low, the output goes high. On the other hand, if the input signal ABCD = 1111 (at the same time A'B'C'D '= 0000), the circuit will operate the inverter, so the output goes low.

10 shows a circuit that receives only the input signal ABCD and performs a NAND operation. In the case of FIG. 9, four inversion signals are required, requiring a total of eight input signals. In FIG. 10, the inversion signal is not required. However, the NAND output is sent out using the CTL control signal. The circuit of FIG. 10 uses a CTL control signal instead of an inverted signal, thereby minimizing through-current during circuit operation.

In the case of FIG. 9, the remaining 15 combinations other than ABCD = 1111 may cause a power consumption problem because the leakage current always flows. However, in FIG. 10, the leakage current flows only when the CTL control signal is input. There is this.

11 is a circuit diagram of the transmission gate T / G 320. In FIG. 11, a switch for outputting an analog voltage is a transfer gate T / G, and a voltage output through the T / G is a data voltage input to the display pixel circuit. When such a transfer gate is composed of only P-type transistors, a simple form using only one transistor can be considered as shown in FIG. 12A.
However, there is a disadvantage in that the current driving capability is lower than that of the CMOS transfer gate illustrated in FIG. 12B. In the case of CMOS circuits, P-type and N-type transistors are used together, so that any value of the input voltage can be output with sufficient driving capability. However, when only the P-type is used, the current driving capability of the transistor is changed because Vgs changes according to the level of the input voltage. Therefore, if the load of the output stage (load) is large, the charging time may be long.
In order to solve the problem, the simplest solution is to increase the current driving capability by increasing the size of the transistor. However, even in this case, the current driving capability nonuniformity of the transistor according to Vin still remains a problem.

Alternatively, as shown in FIG. 13, the Vgs of the output transistor M2 is constantly adjusted with respect to the input voltage Vin of the transfer gate. Vin is applied to the source terminal of M2 and Vin + Vconst. Is applied to the gate terminal to design Vgs = Vconst. To do this, the decoder output TG2 is not directly applied to the gate terminal of M2 but is applied through the capacitor Cump. It also allows M1 to receive a Vin + Voffset (approximately 2V) voltage for Vin. Here, M1 plays the role of Vgs = Voffset to turn M2 off and the Vin + Voffset voltage can be easily obtained from a voltage source consisting of a resistor string. Therefore, when the decoder output TG2 is delivered, the voltage of the gate terminal of M2 becomes Vin + Voffset + Vswing while passing through the capacitor Cpump by the swing of the TG2 signal. If the swing width of the TG2 signal is less than 15V, then Vswing = -10V, resulting in Vin + Voffset + Vswing = Vin + 2-15 = Vin-13 (volt). Therefore, regardless of Vin, Vgs + -13V, and the transmission gate of the present invention has a uniform current driving capability.

14 is a diagram showing a simulation result of the output of the D / A converter 300 according to the present invention. In the figure, it can be seen that it has a uniform current carrying capability over the range of the output voltage (about 2V to 9V).

The operation of the data driver according to the present invention having the above-described configuration is as follows. FIG. 15 is a timing diagram of FIG. 2.

2 and 15, when information representing a data voltage is input as a digital value, the information is sequentially stored in the first latch 210 via the shift resist 100. When data is sequentially stored while being inverted and stored in the first latch 210, the output values of the first latch 210 are simultaneously input to the second latch 220. The digital information input to the second latch 220 is inverted and output as an output value of the second latch 220. At this time, the decoder 310 receives two signal values, input information and output information (inverted value of the input information). Received from In the decoder, the transfer gate transistor is turned on at a desired output terminal to output a desired analog voltage as a data line. The control signals for storing and processing data, that is, SWB1, SWB2, SWB3, enable signal EN, and transfer gate reset signal TRGS are signals supplied from an external chipset. In addition, while the data output from the second latch 220 is outputting analog data to the data line through the above process, the first latch 210 receives the next signal and sequentially samples the data. Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined not only by the scope of the following claims, but also by the equivalents of the claims.

As described above, the present invention may implement a data driver of a digital interface driving method for receiving digital information from the outside and applying analog data to a panel array.
In addition, by implementing the latch array and the transfer gate array of the data driver using only the P-type transistor, when the driving circuit is applied to the panel integration, it is possible to reduce the process cost of the integrated circuit and to improve the feeding of the panel. It can produce display panels.

In addition, according to the present invention, even though the P-type transistor is configured only, since unnecessary leakage-current can be minimized during circuit driving, low power consumption can be driven.

Claims (6)

A data driver for driving a liquid crystal display device, A shift register array for supplying a sampling signal; A latch array for latching and outputting video data in response to the sampling signal; A decoder array for selecting a corresponding data line according to an output signal of the latch array; And And a transmission gate array configured to output an analog voltage to a corresponding data line according to an output signal of the decoder array. The method of claim 1, wherein the latch array A first latch array configured to sequentially store video data in response to the sampling signal, and a second latch array configured to hold an output signal of the first latch array for a predetermined time in response to a control signal supplied from an external chipset, Each latch in the latch array A data driver of a liquid crystal display device, characterized in that it is configured by complementary connection of an inverter implemented with a P-type transistor. delete 2. The decoder of claim 1, wherein each decoder of the decoder array is A data driver of a liquid crystal display device comprising a P-type NAND gate. The method of claim 1, wherein the analog voltage is A data driver of a liquid crystal display device, characterized in that it is obtained selectively from a voltage source consisting of a resistor string. The method of claim 5, wherein each transmission gate of the transmission gate array is A capacitor connected to the output of the decoder, A first P-type transistor having a current path formed between the capacitor and the voltage source and receiving a reset signal supplied from an external chipset as a gate; A second P-type transistor receiving an output signal of the capacitor as a gate and having a source connected to the voltage source, And keeping the gate-source voltage of the second P-type transistor constant with respect to the input voltage from the voltage source.

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