KR102003439B1 - Gate shift register and display device using the same - Google Patents

Gate shift register and display device using the same Download PDF

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KR102003439B1
KR102003439B1 KR1020120148716A KR20120148716A KR102003439B1 KR 102003439 B1 KR102003439 B1 KR 102003439B1 KR 1020120148716 A KR1020120148716 A KR 1020120148716A KR 20120148716 A KR20120148716 A KR 20120148716A KR 102003439 B1 KR102003439 B1 KR 102003439B1
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signal
node
gate
potential
level
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KR1020120148716A
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Korean (ko)
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KR20140079106A (en
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유기택
강하석
김이영
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엘지디스플레이 주식회사
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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3674Details of drivers for scan electrodes
    • G09G3/3677Details of drivers for scan electrodes suitable for active matrices only
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/02Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264Details of driving circuits
    • G09G2310/0286Details of a shift registers arranged for use in a driving circuit
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01Modifications for accelerating switching
    • H03K19/017Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01721Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element

Abstract

The gate shift register according to the present invention includes a plurality of stages for receiving a plurality of gate shift clocks sequentially shifted in phase and generating two gate output signals at a time; Each of the stages connected to each other in a dependent manner includes a first Q node charged to a high level according to a first start signal and discharged to a low level according to a reset signal; A second Q node charged to a high level according to a second start signal and discharging to a low level according to the reset signal; A Q-bar node that is discharged to a low level according to the first start signal and charges to a high level according to the reset signal; A first pull-up switch for switching a current flow between an input terminal of an Nth clock of the gate shift clocks and a first output node in accordance with a potential of the first Q node; A second pull-up switch for switching a current flow between an input terminal of the (N + 1) -th clock of the gate shift clocks and the second output node in accordance with the potential of the second Q node; A first pull-down switch for switching a current flow between an input terminal of the low potential voltage and the first output node according to the potential of the Q-Bar node; And a second pull-down switch for switching the current flow between the input terminal of the low potential voltage and the second output node according to the potential of the Q-Bar node; The reset signal is selected as the (N + 3) -th clock of the gate shift clocks.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a gate shift register,

The present invention relates to a gate shift register and a display using the gate shift register.

Various flat panel displays (FPDs) have been developed and marketed to reduce weight and volume, which are disadvantages of cathode ray tubes (Cathode Ray Tube). The scan driving circuit of the flat panel display generally supplies scan pulses to the scan lines sequentially using a gate shift register.

The gate shift register of the scan driving circuit has stages including a plurality of thin film transistors (hereinafter referred to as "TFTs "). Stages are connected in a cascade to generate output sequentially.

Each of the stages includes a Q-node for controlling a pull-up transistor, and a Q-bar (QB) node for controlling a pull-down transistor. In addition, each of the stages includes switch circuits that charge and discharge the Q node and the QB node voltage in response to a start signal input from the front stage, a reset signal input from the rear stage, and a clock signal.

Display devices including such a scan driving circuit are rapidly becoming larger, and high resolution and high performance are required. Further, the display device is being developed in the direction of reducing the width of the bezel according to the recent trend to minimize the area of the border area where no image is displayed. As the display device becomes higher resolution and higher performance, the design area of the scan driver circuit increases, making it difficult to realize a narrow bezel. Therefore, it is a technical issue to change the design of the scan driver circuit to minimize the design area.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a gate shift register and a display device using the same that can reduce the design area of a scan driver circuit.

In order to accomplish the object of the present invention, a gate shift register according to an embodiment of the present invention includes a plurality of stages for receiving a plurality of gate shift clocks sequentially shifted in phase and generating two gate output signals, respectively; Each of the stages connected to each other in a dependent manner includes a first Q node charged to a high level according to a first start signal and discharged to a low level according to a reset signal; A second Q node charged to a high level according to a second start signal and discharging to a low level according to the reset signal; A Q-bar node that is discharged to a low level according to the first start signal and charges to a high level according to the reset signal; A first pull-up switch for switching a current flow between an input terminal of an Nth clock of the gate shift clocks and a first output node in accordance with a potential of the first Q node; A second pull-up switch for switching a current flow between an input terminal of the (N + 1) -th clock of the gate shift clocks and the second output node in accordance with the potential of the second Q node; A first pull-down switch for switching a current flow between an input terminal of the low potential voltage and the first output node according to the potential of the Q-Bar node; And a second pull-down switch for switching the current flow between the input terminal of the low potential voltage and the second output node according to the potential of the Q-Bar node; The reset signal is selected as the (N + 3) -th clock of the gate shift clocks.

The gate shift register according to an embodiment of the present invention includes a plurality of stages for receiving a plurality of gate shift clocks sequentially shifted in phase and generating two gate output signals, Each of the stages connected to each other in a dependent manner includes a first Q node charged to a high level according to a first start signal and discharged to a low level according to a reset signal; A second Q node charged to a high level according to a second start signal and discharging to a low level according to the reset signal; A Q-bar node that is discharged to a low level according to the first start signal and charges to a high level according to the reset signal; A first pull-up switch for switching a current flow between an input terminal of an Nth clock of the gate shift clocks and a first output node in accordance with a potential of the first Q node; A second pull-up switch for switching a current flow between an input terminal of the (N + 1) -th clock of the gate shift clocks and the second output node in accordance with the potential of the second Q node; A first pull-down switch for switching a current flow between an input terminal of the low potential voltage and the first output node according to the potential of the Q-Bar node; And a second pull-down switch for switching the current flow between the input terminal of the low potential voltage and the second output node according to the potential of the Q-Bar node; The first start signal and the second start signal are selected as the same signal.

According to another aspect of the present invention, there is provided a display device including: a display panel; And a gate shift register including a plurality of stages for receiving a plurality of gate shift clocks sequentially shifted in phase and generating and outputting two gate output signals to the gate lines of the display panel; Each of the stages connected to each other in a dependent manner includes a first Q node charged to a high level according to a first start signal and discharged to a low level according to a reset signal; A second Q node charged to a high level according to a second start signal and discharging to a low level according to the reset signal; A Q-bar node that is discharged to a low level according to the first start signal and charges to a high level according to the reset signal; A first pull-up switch for switching a current flow between an input terminal of an Nth clock of the gate shift clocks and a first output node in accordance with a potential of the first Q node; A second pull-up switch for switching a current flow between an input terminal of the (N + 1) -th clock of the gate shift clocks and the second output node in accordance with the potential of the second Q node; A first pull-down switch for switching a current flow between an input terminal of the low potential voltage and the first output node according to the potential of the Q-Bar node; And a second pull-down switch for switching the current flow between the input terminal of the low potential voltage and the second output node according to the potential of the Q-Bar node; The reset signal is selected as the (N + 3) -th clock of the gate shift clocks.

A display device according to an embodiment of the present invention includes a display panel; And a gate shift register including a plurality of stages for receiving a plurality of gate shift clocks sequentially shifted in phase and generating and outputting two gate output signals to the gate lines of the display panel; Each of the stages connected to each other in a dependent manner includes a first Q node charged to a high level according to a first start signal and discharged to a low level according to a reset signal; A second Q node charged to a high level according to a second start signal and discharging to a low level according to the reset signal; A Q-bar node that is discharged to a low level according to the first start signal and charges to a high level according to the reset signal; A first pull-up switch for switching a current flow between an input terminal of an Nth clock of the gate shift clocks and a first output node in accordance with a potential of the first Q node; A second pull-up switch for switching a current flow between an input terminal of the (N + 1) -th clock of the gate shift clocks and the second output node in accordance with the potential of the second Q node; A first pull-down switch for switching a current flow between an input terminal of the low potential voltage and the first output node according to the potential of the Q-Bar node; And a second pull-down switch for switching the current flow between the input terminal of the low potential voltage and the second output node according to the potential of the Q-Bar node; The first start signal and the second start signal are selected as the same signal.

The gate shift register according to the present invention and the display device using the gate shift register can reduce the number of times of supplying the reset signal and / or the start signal in the gate shift register, thereby minimizing the design area of the scan driver circuit and effectively implementing the narrow bezel .

1 is a block diagram schematically illustrating a gate shift register configuration according to an embodiment of the present invention;
2 is a circuit diagram showing a configuration of a stage 3a-2 of the stages shown in FIG.
Fig. 3 is a diagram showing the operation waveform of the 3a-2 stage shown in Fig. 2; Fig.
4 is a block diagram schematically illustrating a gate shift register configuration according to another embodiment of the present invention;
FIG. 5 is a circuit diagram showing the configuration of a stage 3a-2 of the stages shown in FIG. 4. FIG.
Fig. 6 is a diagram showing the operation waveform of the 3a-2 stage shown in Fig. 5; Fig.
7 is a block diagram schematically illustrating a gate shift register configuration according to another embodiment of the present invention;
8 is a circuit diagram showing a configuration of a stage 3a-2 of the stages shown in FIG. 7. FIG.
Fig. 9 is a diagram showing an operation waveform of the 3a-2 stage shown in Fig. 8; Fig.
10 is a block diagram schematically showing a display device according to an embodiment of the present invention;

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

The names of components used in the following description are selected in consideration of ease of specification, and may be different from actual product names.

1 schematically shows a gate shift register configuration according to an embodiment of the present invention. In one embodiment of the present invention, the same reset signal is supplied to two reset terminals of each stage to reduce a signal multiplier for supplying a reset signal. In particular, in one embodiment of the present invention, any one of the gate shift clocks is used as a reset signal.

Referring to FIG. 1, a gate shift register according to an embodiment of the present invention includes a plurality of stages STG1 to STGn, which are connected in a dependent manner.

Each of the stages STG1 to STGn has two output channels to generate two gate output signals. The gate output signal is applied to the scan lines of the display device as a scan pulse, and is transmitted as a start signal to the subsequent stage. In the following description, the "front stage" is located above the reference stage. For example, in the k-th stage (STGk) do. The "rear stage" is located below the reference stage. For example, in the k-th stage STGk, the rear stage indicates the (k + 1) th stage STGk + 1.

The operation of each of the stages STG1 to STGn is started in accordance with a start signal applied to the first and second start terminals VST1 and VST2 every frame. The odd-numbered gate output signals Vout11 to Vout (n-1) 1 of the front stage stages STG1 to STGn-1 are input to the first start terminal VST1 of each of the stages STG2 to STGn as a start signal, The even gate output signals V12 to V (n-1) 2 of the front stage stages STG1 to STGn-1 are input to the second start terminal VST2 of each of the stages STG2 to STGn as a start signal. On the other hand, first and second gate start pulses Vst1 and Vst2 are applied to the first and second start terminals VST1 and VST2 of the first stage STG1 from the outside (timing controller), respectively, as a start signal.

The operation of each of the stages STG1 to STGn is reset according to a reset signal commonly applied to the first and second reset terminals RST1 and RST2 every frame. One reset signal is applied to each of the stages STG1 to STGn. In particular, since the reset signal is selected as one of the gate shift clocks, it is effective to reduce the number of times for resetting each of the stages STG1 to STGn. In each of the stages STG1 to STGn, two gate shift clocks are sequentially input among i (i is a positive even-number) gate shift clocks which are overlapped by a predetermined time and sequentially delayed. It is preferable that the gate shift clocks are implemented in 6 phases or more in order to secure a sufficient charge time in high-speed operation of 240 Hz or more. Each of the stages STG1 to STGn generates a first gate output signal (Vouta1, a is a positive integer) in response to the first clock CLK1, CLK3, and CLK5 of the two input gate shift clocks, And generates the second gate output signal (Vouta2, a is a positive integer) in response to the second one of the two gate shift clocks (CLK2, CLK4, CLK6). Assuming that the first clocks CLK1, CLK3 and CLK5 are the Nth clock and the second clocks CLK2, CLK4 and CLK6 are the N + 1th clock in the respective stages STG1 to STGn, Th clocks CLK4, CLK6 and CLK2 are selected as the reset signal.

The six-phase gate shift clocks (CLK1 to CLK6) swing between the gate high voltage and the gate low voltage. The stages STG1 to STGn are supplied with AC drive voltages VDDE and VDDO having a phase difference of 180 degrees and swinging in opposite directions and a high potential voltage VDD and a low potential voltage VSS.

2 shows the configuration of the stage 3a-2 (a is a positive integer) stage (STG 3a-2) of the stages STG1 to STGn shown in FIG. 3 shows an operation waveform of the (3a-2) th stage STG (3a-2) shown in FIG. In the following description, 'high level' indicates a voltage level at which switches can be turned on, and 'low level' indicates a voltage level at which switches can be turned off. In the following description, each of the stages STG1 to STGn has two Q nodes QO and QE and two Q-Bar nodes QBO and QBE.

Referring to FIG. 2, the stage 3a-2 (a positive integer) stage STG 3a-2 includes a first output node NO1 for outputting the first gate output signal Vouta1, T6O that switches the current flow between the input terminal of the Nth clock CLK1 and the first output node NO1 according to the potential and the input node of the low potential voltage VSS and the first output node NO1 according to the potential of the QBO node, T10O for switching the current flow between the input terminal of the low potential voltage VSS and the first output node NO1 according to the potential of the QBE node and the second gate output signal Vouta2 for switching the current flow between the input terminal of the low- T6E that switches the current flow between the input terminal of the (N + 1) th clock CLK2 and the second output node NO2 according to the potential of the QE node, a second output node NO2 according to the potential of the QE node, T8E for switching the current flow between the input terminal of the voltage VSS and the second output node NO2, an input terminal of the low potential voltage VSS according to the potential of the QBO node, 2 and an output node comprising the T10E to switch the current flow between the (NO2).

T6O and T6E are pull-up switches, and T80, T10O, T8E and T10E are pull-down switches. The AC drive voltages VDDE and VDDO have opposite voltage levels and are inverted at regular intervals. When VDDO is input to the high level, VDDE is input to the low level, and conversely, when VDDO is input to the low level, VDDE is input to the high level. VDDO is applied to the QBO node, and VDDE is applied to the QBE node. T80 and T10O, and T8E and T10E selectively operate according to AC drive voltages (VDDE, VDDO) to prevent degradation. During the period when VDDO is input to the high level, T80 and T10E, which are switched according to the potential of the QBO node, function as pull-down switches, and T100 and T8E stop operating. During the period when VDDE is input to high level, T8E and T10O, which are switched according to the potential of the QBE node, function as pull-down switches, and T10E and T8O stop operation.

The QO node is charged to a high level according to the first start signal (Vst1 or the odd-numbered gate output signal of the previous stage), and then discharged to a low level according to a reset signal selected by the (N + 3) -th clock (CLK4). The QO node is boosted to a potential higher than the high level when the N-th clock CLK1 is input, and the first gate output signal Voutal is output to the high level at this time. The QE node is charged to a high level according to the second start signal (Vst2 or the output of the even-numbered gate of the previous stage), and then discharged to a low level according to a reset signal selected by the (N + 3) -th clock (CLK4). The QE node is boosted to a potential higher than the high level when the (N + 1) -th clock CLK2 is input, and the second gate output signal Vouta2 is output to the high level at this time. The QBO node (or QBE node) is discharged to a low level according to the first start signal, and then charged to a high level according to the reset signal (CLK4).

The potentials of the QO node and the QE node are controlled in accordance with the switching action of the plurality of switches. Switches that control the potential of the QO node include T5O, T7O, T9O, and T110. T5O switches the current flow between the input terminal of the high potential voltage (VDD) and the QO node according to the first start signal. T7O switches the current flow between the QO node and the input of the low potential voltage (VSS) according to the potential of the QBO node. T9O switches the current flow between the QO node and the input of the low-potential voltage (VSS) according to the potential of the QBE node. T11O switches the current flow between the QO node and the input terminal of the low potential voltage (VSS) according to the reset signal.

The switches controlling the potential of the QE node include T5E, T7E, T9E and T11E. T5E switches the current flow between the input terminal of the high potential voltage (VDD) and the QE node according to the second start signal. T7E switches the current flow between the QE node and the input of the low-potential voltage (VSS) according to the potential of the QBE node. T9E switches the current flow between the QE node and the input of the low potential voltage (VSS) according to the potential of the QBO node. T11E switches the current flow between the QE node and the input terminal of the low potential voltage (VSS) according to the reset signal.

The potentials of the QBO node and the QBE node are controlled according to the switching action of the plurality of switches. Switches that control the potential of the QBO node include T1O, T3O, T4O, and T130. T1O applies VDDO to the QBO node. T3O switches the current flow between the input of VDDO and the QBO node according to the reset signal. T4O switches the current flow between the QBO node and the input of the low-potential voltage (VSS) according to the potential of the QO node. T130 switches the current flow between the QBO node and the input of the low potential voltage (VSS) according to the first start signal.

Switches that control the potential of the QBE node include T1E, T3E, T4E, and T13E. T1E applies VDDE to the QBE node. The T3E switches the current flow between the input of the VDDE and the QBE node according to the reset signal. T4E switches the current flow between the QBE node and the input of the low potential voltage (VSS) according to the potential of the QE node. T13E switches the current flow between the QBE node and the input of the low potential voltage (VSS) according to the first start signal.

The operation of the (3a-2) th stage (STG 3a-2) will be described with reference to FIG. When the first start signal is input, the QO node is charged to the high level, and simultaneously the QBO node (or QBE node) is discharged to the low level, and then the QE node is charged to the high level when the second start signal is input. When the Nth clock CLK1 is input when the QO node is maintained at the high level, the potential of the QO node is boosted to a level higher than the high level, and the first gate output signal Vouta1 is output to the high level. The potential of the QO node is lowered to a high level when the Nth clock (CLK1) is turned off, and then maintained. When the (N + 1) -th clock CLK2 is input when the QE node is maintained at the high level, the potential of the QE node is boosted to a level higher than the high level, and the second gate output signal Vouta2 is high- . The potential of the QE node is lowered to a high level when the (N + 1) -th clock CLK2 is turned off, and then maintained. The potential of the QO node and the potential of the QE node are discharged from the high level to the low level when the reset signal selected by the (N + 3) -th clock (CLK4) is input. The QBO node (or QBE node) is charged from the low level to the high level when the reset signal selected by the (N + 3) -th clock CLK4 is input.

4 schematically shows a gate shift register configuration according to another embodiment of the present invention. 4 is different from FIG. 1 only in that the start signal input to the start terminal is different from the reset signal input to the reset terminal, and the rest are substantially the same.

In another embodiment of the present invention, the same reset signal is supplied to two reset terminals of each stage to reduce a signal multiplier for supplying a reset signal, and a same start signal is supplied to two start terminals of each stage Thereby reducing the signal multiplier for supplying the start signal. In particular, in another embodiment of the present invention, the odd-numbered gate output signal of the front stage is used as a start signal, and the even-numbered gate output signal of the rear stage is used as a reset signal. Hereinafter, differences from FIG. 1 will be mainly described.

Referring to FIG. 4, a gate shift register according to another embodiment of the present invention includes a plurality of stages STG1 to STGn, which are connected in a dependent manner.

Each of the stages STG1 to STGn has two output channels to generate two gate output signals. The gate output signal is applied to the scan lines of the display device as a scan pulse, and is transmitted as a start signal to the subsequent stage.

The operation of each of the stages STG1 to STGn is started in accordance with a start signal applied to the first and second start terminals VST1 and VST2 every frame. The odd-numbered gate output signals Vout11 to Vout (n-1) 1 of the front stage stages STG1 to STGn-1 are supplied to the first and second start terminals VST1 and VST2 of the stages STG2 to STGn, As a signal. On the other hand, a gate start pulse Vst is applied from the outside (timing controller) to the first and second start terminals VST1 and VST2 of the first stage STG1 as a start signal. In this embodiment, since the first start terminal VST1 and the second start terminal VST2 of each stage are commonly inputted with one start signal, it is effective to reduce the number of times that the start signal is supplied.

The operation of each of the stages STG1 to STGn is reset in response to a reset signal applied to the first and second reset terminals RST1 and RST2 every frame. One reset signal is applied to each of the stages STG1 to STGn. Since the reset signal is selected as the even-numbered gate output signal (Vout21 to dummy signal) of the succeeding stage (STG2 to dummy stage), it is effective to reduce the number of multipliers for supplying the reset signal. Each of the stages STG1 to STGn generates a first gate output signal (Vouta1, a is a positive integer) in response to the first clock CLK1, CLK3, and CLK5 of the two input gate shift clocks, The second gate output signal (Vouta2, a is a positive integer) in response to the second clock CLK2, CLK4, CLK6 of the two gate shift clocks.

5 shows the configuration of the stage 3a-2 (a is a positive integer) stage (STG 3a-2) of the stages STG1 to STGn shown in FIG. 6 shows an operation waveform of the (3a-2) th stage STG (3a-2) shown in FIG.

The stage 3a-2 (STG 3a-2) of FIG. 5 is different from the stage 2 of FIG. 2 in that one start signal Vst input to the first and second start terminals VST1 and VST2 And a reset signal commonly input to the first and second reset terminals RST1 and RST2 is selected as the even gate output signal of the subsequent stage The remaining configuration is substantially the same as that of Fig.

The operation of the stage 3a-2 (STG 3a-2) of FIG. 6 is the same as that of FIG. 3, except that the QO node and the QE node simultaneously and simultaneously respond to one start signal (Vst or gate output signal of the previous stage) The QB node and the QE node are charged to a high level and the QO node and the QE node are discharged to a low level and the QBO node (or QBE node) is charged to a high level according to a reset signal selected by the gate output signal of the rear stage, Is substantially the same as in Fig.

7 schematically shows a gate shift register configuration according to another embodiment of the present invention. Fig. 7 is a combination of Fig. 1 and Fig. In another embodiment of the present invention, the same reset signal is supplied to the two reset terminals of each stage to reduce the signal multiplier for supplying the reset signal, and the same start signal is applied to the two start terminals of each stage Thereby reducing the signal multiplier for supplying the start signal. In particular, in another embodiment of the present invention, the odd-numbered gate output signal of the front stage is used as a start signal, and any one of a plurality of gate shift clocks is used as a reset signal. Hereinafter, differences will be mainly described with reference to Figs. 1 and 4.

Referring to FIG. 7, a gate shift register according to another embodiment of the present invention includes a plurality of stages STG1 to STGn, which are connected in a dependent manner.

Each of the stages STG1 to STGn has two output channels to generate two gate output signals. The gate output signal is applied to the scan lines of the display device as a scan pulse, and is transmitted as a start signal to the subsequent stage.

The operation of each of the stages STG1 to STGn is started in accordance with a start signal applied to the first and second start terminals VST1 and VST2 every frame. The odd-numbered gate output signals Vout11 to Vout (n-1) of the front stage stages STG1 to STGn-1 are supplied to the first and second start terminals VST1 and VST2 of the stages STG2 to STGn, ) 1) are commonly input as a start signal. On the other hand, a gate start pulse Vst is applied from the outside (timing controller) to the first and second start terminals VST1 and VST2 of the first stage STG1 as a start signal. In this embodiment, since the first start terminal VST1 and the second start terminal VST2 of each stage are commonly inputted with one start signal, it is effective to reduce the number of times that the start signal is supplied.

The operation of each of the stages STG1 to STGn is reset according to a reset signal commonly applied to the first and second reset terminals RST1 and RST2 every frame. One reset signal is applied to each of the stages STG1 to STGn. In particular, since the reset signal is selected as one of the gate shift clocks as shown in FIG. 1, it is effective to reduce the number of times for resetting each of the stages STG1 to STGn. In each of the stages STG1 to STGn, two gate shift clocks are sequentially input among i (i is a positive even-number) gate shift clocks which are overlapped by a predetermined time and sequentially delayed. It is preferable that the gate shift clocks are implemented in 6 phases or more in order to secure a sufficient charge time in high-speed operation of 240 Hz or more. Each of the stages STG1 to STGn generates a first gate output signal (Vouta1, a is a positive integer) in response to the first clock CLK1, CLK3, and CLK5 of the two input gate shift clocks, And generates the second gate output signal (Vouta2, a is a positive integer) in response to the second one of the two gate shift clocks (CLK2, CLK4, CLK6). Assuming that the first clocks CLK1, CLK3 and CLK5 are the Nth clock and the second clocks CLK2, CLK4 and CLK6 are the N + 1th clock in the respective stages STG1 to STGn, Th clocks CLK4, CLK6 and CLK2 are selected as the reset signal.

FIG. 8 shows the structure of the stage 3a-2 (a is a positive integer) stage (STG 3a-2) of the stages STG1 to STGn shown in FIG. 9 shows an operation waveform of the (3a-2) th stage STG (3a-2) shown in FIG.

The stage 3a-2 (STG 3a-2) of FIG. 8 is a combination of the configuration of FIG. 2 and the configuration of FIG. The stage 3a-2 (STG 3a-2) of FIG. 8 includes one start signal Vst commonly input to the first and second start terminals VST1 and VST2, or an odd- T50 and T5E are controlled at the same time according to the clock signal CLK1 and one reset signal commonly input to the first and second reset terminals RST1 and RST2 is selected as the (N + 3) -th clock CLK4. The rest of the configuration is substantially the same as that described in Figs. 2 and 5.

The operation of the stage 3a-2 (STG 3a-2) of FIG. 9 is such that the QO node and the QE node are simultaneously charged to a high level in response to one start signal (Vst or the gate output signal of the previous stage) The QO node and the QE node are discharged to a low level and the QBO node (or QBE node) is charged to a high level according to a reset signal selected by the (N + 3) -th clock CLK4. The other remaining operations are substantially the same as those described in Figs. 3 and 6.

10 schematically shows a display device according to an embodiment of the present invention.

Referring to FIG. 10, the display device of the present invention includes a display panel 100, a data driving circuit, a scan driving circuit, a timing controller 110, and the like.

The display panel 100 includes data lines and scan lines which intersect with each other, and pixels arranged in a matrix form. The display panel 100 may be implemented as a display panel of any one of a liquid crystal display (LCD), an organic light emitting diode display (OLED), and an electrophoretic display (EPD).

The data driving circuit includes a plurality of source drive ICs 120. [ The source drive ICs 120 receive the digital video data RGB from the timing controller 110. The source driver ICs 120 convert the digital video data RGB to a gamma compensation voltage in response to a source timing control signal from the timing controller 110 to generate a data voltage, To the data lines of the display panel 100 as shown in FIG. The source drive ICs may be connected to the data lines of the display panel 100 by a COG (Chip On Glass) process or a TAB (Tape Automated Bonding) process.

The scan driver circuit includes a timing controller 110 and a level shifter 150 connected between the scan lines of the display panel 100 and a gate shift register 130.

The level shifter 150 outputs a TTL (Transistor-Transistor-Logic) logic level voltage of the six-phase gate shift clocks CLK1 to CLK6 input from the timing controller 110 to a gate high Level shift to voltage and gate low voltage.

The gate shift register 130 is composed of stages for shifting the start signal to the gate shift clocks CLK1 to CLK6 and sequentially generating a gate output signal as described above. And generates and outputs two gate output signals for each stage.

The scan driver circuit may be formed directly on the lower substrate of the display panel 100 using a GIP (Gate In Panel) method. In the GIP scheme, the level shifter 150 is mounted on the PCB 140, and the gate shift register 130 may be formed on the lower substrate of the display panel 100. The gate shift register 130 is formed in a region where the image is not displayed on the display panel 100 (i.e., the bezel region BZ). When the number of times of supplying the reset signal and / or the start signal in the gate shift register 130 is reduced by the method described with reference to FIGS. 1 to 9, the area of the gate shift register 130 is reduced accordingly, It is very effective in reducing

The timing controller 110 receives digital video data RGB from an external host computer through an interface such as a Low Voltage Differential Signaling (LVDS) interface or a Transition Minimized Differential Signaling (TMDS) interface. The timing controller 110 transmits digital video data (RGB) input from the host computer to the source drive ICs 120.

The timing controller 110 receives timing signals such as a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, a data enable signal DE and a main clock MCLK from the host computer through an LVDS or TMDS interface receiving circuit And receives a signal. The timing controller 110 generates timing control signals for controlling the operation timing of the data driving circuit and the scan driving circuit based on the timing signal from the host computer. The timing control signals include a scan timing control signal for controlling the operation timing of the scan drive circuit, a data timing control signal for controlling the operation timing of the source drive ICs 120 and the polarity of the data voltage.

The scan timing control signal includes gate start pulses, gate shift clocks (CLK1 to CLK6), gate output enable (GOE) signals (not shown), and the like. The gate start pulse includes a forward gate start pulse and a reverse gate start pulse. The gate start pulse is input to the gate shift register 130 to control the shift start timing. The gate shift clocks CLK1 to CLK6 are level-shifted through the level shifter 150 and then input to the gate shift register 130 and used as a clock signal for shifting the start signal. The gate output enable signal GOE controls the output timing of the gate shift register 130.

The data timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), and a source output enable signal (SOE) . The source start pulse SSP controls the shift start timing of the source drive ICs 120. The source sampling clock SSC is a clock signal that controls the sampling timing of data in the source drive ICs 120 based on the rising or falling edge. The polarity control signal POL controls the polarity of the data voltage output from the source drive ICs. If the data transfer interface between the timing controller 110 and the source drive ICs 120 is a mini LVDS interface, the source start pulse SSP and the source sampling clock SSC may be omitted.

As described above, the gate shift register according to the present invention and the display device using the gate shift register minimize the design area of the scan driver circuit by reducing the number of times of supplying the reset signal and / or the start signal in the gate shift register, Can be effectively implemented.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100: display panel 110: timing controller
120: Source drive IC 130: Gate shift register
140: PCB 150: Level shifter

Claims (12)

  1. A plurality of stages for receiving a plurality of gate shift clocks sequentially shifted in phase and generating a plurality of gate output signals in units of two;
    Each of the stages, which are connected to each other in a dependent manner,
    A first Q node charged to a high level according to a first start signal and discharged to a low level according to a reset signal;
    A second Q node charged to a high level according to a second start signal and discharging to a low level according to the reset signal;
    A Q-bar node that is discharged to a low level according to the first start signal and charges to a high level according to the reset signal;
    A first pull-up switch for switching a current flow between an input terminal of an Nth clock of the gate shift clocks and a first output node in accordance with a potential of the first Q node;
    A second pull-up switch for switching a current flow between an input terminal of the (N + 1) -th clock of the gate shift clocks and the second output node in accordance with the potential of the second Q node;
    A first pull-down switch for switching a current flow between an input terminal of the low potential voltage and the first output node according to the potential of the Q-Bar node; And
    And a second pull-down switch for switching the current flow between the input terminal of the low potential voltage and the second output node according to the potential of the Q-Bar node;
    The reset signal is commonly input to two reset terminals included in each stage, and the reset signal is supplied to the N < th > clock and the (N + 3) < th > And the clock signal is selected as a clock.
  2. The method according to claim 1,
    Wherein the first start signal and the second start signal are selected as the same signal and are selected as the odd-numbered gate output signal whose phase is earlier than the two gate output signals of the front stage.
  3. The method according to claim 1,
    Wherein the first start signal and the second start signal are selected as different signals and the first start signal is selected as the odd-numbered gate output signal whose phase is earlier than the two gate output signals of the previous stage, And the 2-start signal is selected as the even-numbered gate output signal that is out of phase with respect to the two gate output signals of the front-end stage.
  4. A plurality of stages for receiving a plurality of gate shift clocks sequentially shifted in phase and generating a plurality of gate output signals in units of two;
    Each of the stages, which are connected to each other in a dependent manner,
    A first Q node charged to a high level according to a first start signal and discharged to a low level according to a reset signal;
    A second Q node charged to a high level according to a second start signal and discharging to a low level according to the reset signal;
    A Q-bar node that is discharged to a low level according to the first start signal and charges to a high level according to the reset signal;
    A first pull-up switch for switching a current flow between an input terminal of an Nth clock of the gate shift clocks and a first output node in accordance with a potential of the first Q node;
    A second pull-up switch for switching a current flow between an input terminal of the (N + 1) -th clock of the gate shift clocks and the second output node in accordance with the potential of the second Q node;
    A first pull-down switch for switching a current flow between an input terminal of the low potential voltage and the first output node according to the potential of the Q-Bar node; And
    And a second pull-down switch for switching the current flow between the input terminal of the low potential voltage and the second output node according to the potential of the Q-Bar node;
    Wherein the first start signal and the second start signal are selected as the same signal and are selected as the odd-numbered gate output signal whose phase is earlier than the two gate output signals of the front stage.
  5. delete
  6. 5. The method of claim 4,
    Wherein the reset signal is commonly input to two reset terminals included in each stage and the reset signal is selected as an even gate output signal of a later phase out of the two gate output signals of the subsequent stage Gate shift register.
  7. Display panel; And
    And a gate shift register according to any one of claims 1 to 3 connected to gate lines of the display panel.
  8. delete
  9. delete
  10. Display panel; And
    And a gate shift register according to any one of claims 4 and 6, which is connected to the gate lines of the display panel.
  11. delete
  12. delete
KR1020120148716A 2012-12-18 2012-12-18 Gate shift register and display device using the same KR102003439B1 (en)

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Families Citing this family (19)

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Publication number Priority date Publication date Assignee Title
CN104299554B (en) * 2014-08-22 2017-07-18 京东方科技集团股份有限公司 Shift register, array base palte and display device
CN104464600B (en) * 2014-12-26 2017-02-01 合肥鑫晟光电科技有限公司 Shifting register unit, driving method of shifting register unit, shifting register circuit and display device
KR101693088B1 (en) 2014-12-31 2017-01-04 엘지디스플레이 주식회사 Display panel having a scan driver and method of operating the same
CN104616616B (en) * 2015-02-12 2017-12-15 京东方科技集团股份有限公司 Gate driving circuit and its driving method, array base palte, display device
CN104966496A (en) * 2015-04-15 2015-10-07 昆山龙腾光电有限公司 Gate drive circuit unit and gate drive circuit with gate drive circuit unit
CN104934009B (en) * 2015-07-09 2018-02-13 京东方科技集团股份有限公司 Shift register cell and driving method, shift-register circuit and display device
CN105161060B (en) * 2015-08-18 2017-12-15 深圳市华星光电技术有限公司 Scan drive circuit and the liquid crystal display device with the circuit
CN105096889B (en) 2015-08-28 2018-03-06 京东方科技集团股份有限公司 A kind of shift register, its driving method, gate driving circuit and display device
CN105741802B (en) * 2016-03-28 2018-01-30 京东方科技集团股份有限公司 Shift register cell and its driving method, gate driving circuit, display device
CN105845098B (en) * 2016-06-20 2019-02-12 京东方科技集团股份有限公司 Shift register cell and driving method, gate driving circuit and display device
CN106023943A (en) * 2016-08-02 2016-10-12 京东方科技集团股份有限公司 Shifting register and drive method thereof, grid drive circuit and display device
CN106098016B (en) * 2016-08-24 2018-10-23 武汉华星光电技术有限公司 Scan drive circuit and flat display apparatus with the circuit
CN106531053A (en) * 2017-01-06 2017-03-22 京东方科技集团股份有限公司 Shift register, gate driving circuit and display panel
CN106952606A (en) * 2017-05-18 2017-07-14 上海天马有机发光显示技术有限公司 A kind of shift register circuit unit, shift register circuit and display panel
CN109285504A (en) * 2017-07-20 2019-01-29 京东方科技集团股份有限公司 Shift register cell and its driving method, gate driving circuit
CN107316600A (en) * 2017-07-21 2017-11-03 京东方科技集团股份有限公司 Shift register cell and its driving method, gate driving circuit, display device
CN108231021A (en) * 2017-12-26 2018-06-29 惠科股份有限公司 Shift scratch circuit and display panel
CN108877627A (en) * 2018-07-13 2018-11-23 京东方科技集团股份有限公司 Shift register cell and driving method, gate driving circuit, display device
CN109920387A (en) * 2019-02-22 2019-06-21 合肥京东方卓印科技有限公司 Shift register cell and its driving method, gate driving circuit and its driving method and display device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101568249B1 (en) * 2007-12-31 2015-11-11 엘지디스플레이 주식회사 Shift register
KR101642992B1 (en) * 2009-12-30 2016-08-10 엘지디스플레이 주식회사 Shift register and display device using the same
KR101678214B1 (en) * 2010-03-11 2016-11-29 엘지디스플레이 주식회사 Shift register and display device using the same
KR101679855B1 (en) * 2010-05-07 2016-12-07 엘지디스플레이 주식회사 Gate shift register and display device using the same
KR101761414B1 (en) * 2010-11-24 2017-07-26 엘지디스플레이 주식회사 Gate shift register and display device using the same

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