KR20160083378A - Display device and gate driving circuit thereof - Google Patents

Abstract

The present invention relates to a display device and a gate driving circuit thereof. The gate driving circuit includes a shift register which a gate start pulse and a gate shift clock are inputted to and comprises subordinately connected flip-flops, buffers which supply the output signal of the flip-flop to gate lines, a first switch which responds to a first switch control signal and connects adjacent gate lines, a second switch which responds to a second switch control signal and connects the gate liens and the buffers, and a logical operation element which uses the gate start pulse, the gate shift clock, the output of the flip-flop, and an gate output enable signal to generate the first and the second switch control signal. So, the power consumption of the gate driving circuit can be reduced.

Description

DISPLAY DEVICE AND GATE DRIVE CIRCUIT THEREOF BACKGROUND OF THE INVENTION 1. Field of the Invention [0001]

The present invention relates to a display device and a gate driving circuit thereof.

An organic light emitting diode (OLED) display, a plasma display panel (PDP), an electrophoretic display device (EPD), a liquid crystal display (LCD) Various flat panel display devices have been developed. A liquid crystal display device displays an image by controlling an electric field applied to liquid crystal molecules in accordance with a data voltage. A thin film transistor (hereinafter referred to as "TFT") is formed for each pixel in an active matrix driving liquid crystal display device.

The liquid crystal display device includes a display panel, a data driving circuit for supplying a data signal to the data lines of the display panel, a gate driving circuit for supplying a gate signal (or a scan signal) to the gate lines (or scan lines) A control circuit for driving the driving circuits, a light source driving circuit for driving the light source of the backlight unit, and the like.

The gate driving circuit successively supplies the gate signal from the first gate line to the last gate line for one frame period in order to sequentially select the lines of the pixel array. Generally, the gate drive circuit includes a plurality of gate drive ICs (Integrated Circuits).

1 shows an example of a gate driving circuit. 2 shows a control signal and a gate signal for controlling the gate driving circuit.

1 and 2, the gate driving circuit includes a shift register, a level shifter (LS), and the like.

The shift register shifts a gate start pulse (GSP) every gate shift clock (GSC) timing by using a plurality of flip-flops (FF) which are connected in a dependent manner. The first flip-flop FF outputs an input, that is, a gate start pulse GSP at the rising edge timing of the first clock of the gate shift clock GSC. The second flip-flop FF outputs the input, that is, the output of the first flip-flop FF at the rising edge timing of the second clock of the gate shift clock GSC. Q1 is the output signal of the first flip-flop FF, and Q2 is the output signal of the second flip-flop FF. The output of the shift register is supplied to the level shifter LS through the AND gate (AND).

Each of the AND gates 11 generates an output by logically multiplying the inverted signals of the output signals Q1 and Q2 of the flip-flop Q and the gate output enable (GOE). The enable signal GOE which is the gate output is inverted by the inverter NOT and supplied to the first input terminal of the AND gate AND. The AND gate AND supplies the outputs Q1 and Q2 of the flip-flop FF to the level shifter LS when the gate output enable signal GOE is a low logic voltage (L) And outputs 0 (zero or low) when the gate output enable signal GOE is a high logic voltage (H).

The level shifter LS shifts the input voltage level to the operating voltage of the TFT of the pixel array. The output signal of the level shifter LS swings between the gate high voltage VGH and the gate low voltage VGL. The gate high voltage VGH is higher than the threshold voltage of the TFT and the gate low voltage VGL is higher than the threshold voltage of the TFT.

The output signal of the level shifter LS is supplied to the gate lines of the display panel through the buffer BUF. In Fig. 2, OUT1 and OUT2 are gate signals output from the gate driving circuit through the buffer BUT. The TFT is turned on according to the gate signal from the gate line to supply the data signal from the data line to the pixel electrode.

The gate driving circuit charges the gate line voltage from VGL to VGH at the rising edge of the gate signal to rise the gate signal as shown in FIG. The gate driving circuit discharges the gate line voltage from VGH to VGL at the falling edge of the gate signal as shown in FIG. Therefore, the gate driving circuit generates the voltage of the gate signal between VGH and VGL, so that power consumption is large. In Fig. 3, "GIC output voltage" is the drive voltage of the gate drive IC and is equal to the drive voltage of the buffer BUF. The driving voltage of the buffer BUF is generated between VGL and VGH.

If the current consumption of the VGH increases, the VHG voltage may drop due to the wiring resistance of the display panel. The voltage drop on the VHG lowers the amount of pixel charge on a particular line, resulting in line-shaped noise. The voltage drop of the VGH occurs mainly between neighboring gay drive ICs, causing a block dim in the lateral direction.

One horizontal period is a period in which data is written to one line of pixels in the display panel. 1 The horizontal period is inversely proportional to the number of lines in the display panel. The load on the gate line is proportional to the wiring resistance and parasitic capacitance of the gate line. 1 When the horizotal taim is shortened or the load of the gate line is increased, the slew rate of the gate signal is lowered. When the slew rate of the gate signal is lowered, the charge rate of the pixel is lowered, so the picture quality is lowered. The slew rate is defined as the maximum rate of change of the output voltage. A low slew rate means that the output voltage does not reach the target voltage within the desired time.

As shown in Fig. 4, when the resolution of the display device is increased or the load of the gate line is increased, the slew rate of the gate signal is lowered. In FIG. 4, reference numeral 11 denotes a gate signal having a high slew rate, and reference numeral 12 denotes a gate signal having a low slew rate. When the slew rate of the gate signal is lowered, the gate signal does not reach the target voltage (VGH) within one horizontal period. Therefore, when the slew rate of the gate signal is lowered, the gate voltage of the TFT is lowered, resulting in a decrease in the charge amount of the pixel.

The present invention provides a display device capable of lowering the power consumption of a gate driving circuit, increasing a slew rate, and reducing a voltage drop of a gate signal, and a gate driving circuit thereof.

A display device of the present invention includes: a display panel including pixels arranged in a matrix by an intersection structure of data lines and gate lines; And a gate driver for receiving a gate start pulse, a gate shift clock, and a gate output enable signal to generate a gate signal sequentially shifted and supplying the gate signal to the gate lines.

The gate driver may include a shift register having flip-flops to which the gate start pulse and the gate shift clock are input and to which the gate shift clock is connected, buffers for supplying the output signal of the flip flop to the gate lines, A second switch for connecting gate lines to the buffers in response to a second switch control signal, and a second switch for connecting the gate start pulse, the gate shift clock, the output of the flip flop And a logic operation element for generating the first and second switch control signals using the gate output enable signal.

In the display device of the present invention, the present invention generates a switch control signal for controlling the charge share in the gate driving circuit, and carries out charge sharing at the rising edge and the falling edge of the gate signal using the switch control signal. As a result, the present invention can lower the power consumption of the gate driving circuit, increase the slew rate of the gate signal, and reduce the voltage drop of the gate signal.

1 is a circuit diagram showing a conventional gate driving circuit.
2 is a waveform diagram showing control signals and gate signals of the gate driving circuit shown in FIG.
3 is a waveform diagram showing a driving voltage of the gate driving circuit shown in FIG.
4 is a graph showing the relationship between the slew rate of the gate signal and the resolution of the display device.
5 is a block diagram showing a display device according to an embodiment of the present invention.
6 is a diagram showing a charge share period of a gate signal and a driving period of a gate driver.
FIGS. 7 and 8 are views showing the operation principle of the gate driver according to the embodiment of the present invention.
9 is a waveform diagram showing the operation of the gate driver according to the first embodiment of the present invention.
10 is a circuit diagram showing a gate driver for generating a gate signal as shown in FIG.
11 is a waveform diagram showing the operation of the gate driver according to the second embodiment of the present invention.
12 is a circuit diagram showing a gate driver for generating a gate signal as shown in FIG.

The display device of the present invention can be implemented as a flat panel display device capable of color display such as a liquid crystal display (LCD), an organic light emitting diode display (OLED) display, and a plasma display panel (PDP).

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

Referring to Fig. 5, the display device of the present invention includes a display panel 100 on which a pixel array is formed, and a display panel drive circuit for writing data of an input image on the display panel 100. Fig. In FIG. 6, a back light unit and its driving unit are omitted.

The input image is displayed on the pixel array of the display panel 100. Pixels of the pixel array are arranged in a matrix form defined by the intersection structure of the data lines DL and the gate lines GL. Each of the pixels may include one or more TFTs that operate as a pixel electrode 10 to which a data voltage is supplied, a switching element and / or a driving element, and one or more capacitors Cst. The pixels may be connected to the common electrode 2. And supplies a common voltage Vcom to the common electrode 2 to the pixels.

The display panel drive circuit includes a data driver 102, a gate driver 103, and a timing controller 101.

The data driver 102 includes a plurality of source drive ICs. The source driver ICs convert the data of the input image received from the timing controller 101 into a positive / negative gamma compensation voltage to output positive / negative data signals. The data signals output from the source drive ICs are supplied to the data lines S1 to Sm. Each of the source driver ICs inverts the polarity of the data voltage to be supplied to the pixels under the control of the timing controller 101 and outputs them to the data lines S1 to Sm.

The gate driver 103 supplies gate signals to n (n is a positive integer) gate lines G1 to Gn under the control of the timing controller 101. [ The gate driver may include a plurality of gate driver ICs. The IC in which the gate driver 103 is integrated may be bonded to the display panel 100 by a TAB (Tape Automated Bonding) process and connected to the gate lines G1 to Gn. In addition, the gate driver 103 may be formed directly on the substrate surface of the display panel 100 in which the pixel array is formed by the GIP (Gate In Panel) process.

The gate driver 103 connects neighboring gate lines during a preset t1 period in each rising edge and falling edge of the gate signal to induce a charge share (CS) of the gate lines. The gate driver 103 supplies the gate signal to the gate line GL in a state in which the gate lines are separated from each other during a period t2 other than the period t1. The gate driver 103 repeats this operation to generate a gate signal and sequentially supplies the gate signal to the gate lines GL while shifting the gate signal.

A timing controller (TCON) 101 receives timing signals (Vsync, Hsync, DE, CLK) synchronized with input image data from a host system (HOST) 104. The timing controller 101 transmits the data of the input image received from the host system 110 to the data driver 102. The timing signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a main clock CLK. The timing controller 101 generates a source timing control signal SDC for controlling the operation timing of the data driver 102 and the gate driver 103 based on the timing signals Vsync, Hsync, DE and CLK, (GDC).

The source timing control signal SDC includes a source start pulse SSP, a source sampling clock SSC, a polarity control signal POL, and a source output enable signal Source Output Enable, SOE). The source start pulse SSP controls the start timing of the shift register built in the data driver 102. The source sampling clock SSC controls the sampling timing of the data. The polarity control signal POL controls the polarity of the data signal output from the data driver 102. The source output enable signal SOE controls the output timing of the data signal and the charge sharing timing.

The gate timing control signal GDC includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, and the like. The gate start pulse GSP controls the start timing of the shift register. The gate shift clock GSC controls the shift timing of the shift register. The gate output enable signal GOE defines the charge share timing and the gate high voltage output timing in each of the gate signals.

The host system 104 may be any one of a television system, a set top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system.

6 is a diagram showing the charge share period t1 of the gate signal and the drive period t2 of the gate driver 103. In FIG.

The charge sharing period t1 is a period during which the gate lines GL are charged or discharged with an average voltage when no output is generated in the buffer BUF of the gate driver 103 and the gate lines GL are shorted to each other to be. The driving period t2 of the gate driving unit 103 is a period during which the gate lines GL are discharged and charged or discharged with a voltage generated through the buffer BUF of the gate driving unit 103 .

6, the voltage of the gate lines is precharged to an intermediate potential between VGH and VGL, for example, (VGH-VGL) / 2 by using a charge share CS during the t1 period in the rising edge of the gate signal, . When the gate lines are connected to each other at the rising edge of the gate signal, the voltage of the gate lines is averaged by the charge sharing CS so that the voltage of the gate line increases rapidly to approximately (VGH-VGL) / 2. Next, the present invention rapidly increases the voltage of the gate line GL from (VGH-VGL) / 2 to VGH by connecting the gate line to the buffer BUF that outputs the VGH voltage during the rising period of the gate signal at the rising edge. Since the present invention drives the gate driver 103 only during the t2 period at the rising edge of the gate signal, the power consumption of the gate driver 103 can be greatly reduced. During the period t2, the swing width of the gate signal is only 1/2 of that of the prior art, so that the slew rate is high.

The present invention precharges the voltage of the gate lines up to the potential between VGH and VGL, for example (VGH-VGL) / 2, using the charge share CS during t1 at the polling edge of the gate signal as shown in FIG. When the gate lines are connected to each other at the polling edge of the gate signal, the voltages of the gate lines are averaged by the charge sharing CS, and the voltage of the gate line is rapidly lowered to about (VGH-VGL) / 2. The voltage of the gate line GL is rapidly lowered from (VGH-VGL) / 2 to VGL by connecting the gate line to the buffer (BUF) that outputs VGL during the t2 period at the polling edge of the signal. Since the present invention drives the gate driver 103 only during a period t2 in the falling edge of the gate signal, the power consumption of the gate driver 103 can be greatly reduced. During the period t2, the swing width of the gate signal is only 1/2 of that of the prior art, so that the slew rate is high.

FIGS. 7 and 8 are views showing the operation principle of the gate driver.

Referring to FIGS. 7 and 8, the gate driver 103 sequentially shifts gate signals using a shift register under the control of the timing controller 101.

The gate driver 103 turns on the first switch S1 during a period t1 at the rising edge of the gate signal under the control of the timing controller 101. [ In the rising edge of the gate signal, the gate lines GL are short-circuited to each other during the t1 section and rise to approximately (VGH-VGL) / 2. In the rising edge of the gate signal, the voltage of the gate line rises by charge sharing without the voltage supply of the gate driver 103. [ The gate driver 103 turns on the second switch S2 during a period t2 under the control of the timing controller 101 and supplies a voltage to the gate line GL through the second switch S2 to apply a voltage To VGH.

The gate driver 103 generates the first and second switch control signals defining the periods t1 and t2 using the logic operation element. The gate driver 103 turns on the first switch S1 during the t1 period on the falling edge of the gate signal under the control of the timing controller 101. [ At the polling edge of the gate signal, the gate lines GL are shorted to CS and VGH to VGH-VGL / 2 for a period t1. The voltage of the gate line at the polling edge of the gate signal is lowered by the charge sharing without the voltage supply of the gate driver 103. [ The gate driver 103 turns on the second switch S2 during the period t2 under the control of the timing controller 101 to discharge the voltage to the gate line GL through the second switch S2, To VGL.

The data driver 102 generates the switch control signals C1 and C2 defining the periods t1 and t2 to control the switches S1 and S2 as shown in FIGS.

9 is a waveform diagram showing the operation of the gate driver 103 according to the first embodiment of the present invention. 10 is a circuit diagram showing a gate driver 103 for generating a gate signal as shown in FIG.

9 and 10, the gate driver 103 includes a shift register, a level shifter LS, a NOT gate, an AND gate, a NOR gate, a buffer BUF, and the like .

The gate driver 103 receives GSP, GSC and GOE from the timing controller 101 and operates. The shift register includes a plurality of flip-flops (FFs) connected in a dependent manner. GSP and GSC are input to the shift register. GSP is generated once during one frame period and input to the first flip-flop (FF) of the shift register. The output signal of the front end flip-flop FF is input to the data input terminal of the remaining flip-flops FF. The GSC is generated by the number of lines of the display panel. One cycle of GSC is one horizontal period. The GSC is supplied to the clock terminals of all flip-flops and is also input to the NOT gate (NOT). The GOE is input to the AND gate (AND).

The shift register shifts the GSP every clock timing of the GSC using a plurality of flip-flops (FFs) that are connected in a dependent manner. The first flip-flop FF outputs the input, i.e., the GSP, at the rising edge timing of the first clock of the GSC. The second flip-flop FF outputs the output of the first flip-flop FF at the rising edge timing of the second clock of the GSC. The third flip-flop FF outputs the output of the second flip-flop FF at the rising edge timing of the third clock of the GSC. Q1 is the output signal of the first flip-flop FF, and Q2 is the output signal of the second flip-flop FF. Q3 is the output signal of the third flip-flop (FF). The outputs Q1, Q2 and Q3 of the shift register are input to the level shifter LS and also input to the AND gate AND.

The NOT gate (NOT) inverts the gate shift clock GSC and supplies it to the AND gate (AND).

The AND gate AND outputs a first switch control signal C1 that defines t1 at which the charge share CS is implemented. t1 is a period in which GOE = High AND GSC = Low AND (GSP or Q = high) as shown in FIG. Here, Hig is a high logic period and Low is a low logic period. AND is an AND operation. GSP or Q = high means when the gate output pulse (GSP) or the output output (Q1, Q2, Q3) of the flip-flop (FF) is high logic. The first AND gate (AND) ANDs GOE, / GSC, and GSP to output the first switch control signal (C1). / GSC denotes an inverted gate shift clock. The remaining AND gates (AND) perform a logical multiplication of GOE, / GSC, and Qn (n is a natural number) to output the first switch control signal C1. The output of the AND gate AND is input to the control terminal of the first switch S1 through the level shifter LS and is input to the adjacent NOR gate NOR.

The NOR gate (NOR) generates a second switch control signal C2 that defines the t2 period. The period t2 is the remaining period excluding the period t1. Therefore, the NOR gate (NOR) receives the output of the neighboring AND gate (AND), performs a NOR operation, and outputs the second switch control signal (C2). The output of the NOR gate (NOR) is input to the control terminal of the second switch (S2) through the level shifter (LS).

The level shifter LS shifts the input voltage level to the operating voltage of the TFT of the pixel array. The output signal of the level shifter LS swings between the gate high voltage VGH and the gate low voltage VGL. The gate high voltage VGH is higher than the threshold voltage of the TFT and the gate low voltage VGL is higher than the threshold voltage of the TFT.

On the other hand, the level shifter LS is connected to the input terminal of the shift register in the case of the GIP circuit. Therefore, the level shifter LS on the substrate of the display panel can be omitted in the GIP circuit.

The first switch S1 responds to the first switch control signal C1 and applies a charge share CS for the period t1 at the rising edge and the falling edge of the gate signals OUT1, OUT2 and OUT3, respectively. The first switch S1 connected to the first output terminal is supplied with VGH or the last output signal Carry of the front gate drive IC. The remaining first switches S1 connect the neighboring output terminals. The first switches S1 are simultaneously turned on in response to the first switch control signal C1 to short-circuit all the output terminals to implement a charge share CS. Since the output terminals of the gate driver 103 are connected to the gate lines GL, when the output terminals are short-circuited, the voltage of the gate lines GL is raised or lowered to an intermediate potential between VGH and VGL by charge sharing. During the period t1, the second switches S2 remain off.

The second switch S2 is supplied through the buffer BUF during the other excitation except the t1 period in the rising edge and the falling edge of the gate signals OUT1, OUT2 and OUT3 in response to the second switch control signal C2 VGH or VGL to the output terminals. The second switches S2 are sequentially turned on in synchronization with the outputs Q1, Q2 and Q3 of the shift register sequentially generated. Therefore, the gate signal maintains the VGH potential according to VGH input through the buffer BUF during the t2 period after the t1 period of the rising edge, and is input through the buffer BUF during the t2 period after the t1 period of the falling edge And maintains the VGL potential according to VGL. During the period t2, the first switches S1 remain off.

11 is a waveform diagram showing the operation of the gate driver 103 according to the second embodiment of the present invention. 12 is a circuit diagram showing a gate driver 103 for generating a gate signal as shown in FIG.

11 and 12, the gate driver 103 includes a shift register, a level shifter LS, a NOT gate NOT, a first AND gate AND1, a second AND gate AND2, an OR gate OR ), A third AND gate NOR gate (NOR), a buffer (BUF), and the like.

The gate driver 103 receives GSP, GSC and GOE from the timing controller 101 and operates. The shift register includes a plurality of flip-flops (FFs) connected in a dependent manner. GSP and GSC are input to the shift register. GSP is generated once during one frame period and input to the first flip-flop (FF) of the shift register. The output signal of the front end flip-flop FF is input to the data input terminal of the remaining flip-flops FF. The GSC is generated by the number of lines of the display panel. One cycle of GSC is one horizontal period. The GSC is supplied to the clock terminals of all flip-flops and is also input to the NOT gate (NOT). The GOE is input to the AND gate (AND).

The shift register shifts the GSP every clock timing of the GSC using a plurality of flip-flops (FFs) that are connected in a dependent manner. The first flip-flop FF outputs the input, i.e., the GSP, at the rising edge timing of the first clock of the GSC. The second flip-flop FF outputs the output of the first flip-flop FF at the rising edge timing of the second clock of the GSC. The third flip-flop FF outputs the output of the second flip-flop FF at the rising edge timing of the third clock of the GSC. Q1 is the output signal of the first flip-flop FF, and Q2 is the output signal of the second flip-flop FF. Q3 is the output signal of the third flip-flop (FF). The outputs Q1, Q2 and Q3 of the shift register are input to the level shifter LS and also input to the first and second AND gates AND1 and AND2.

The NOT gate NOT inverts the gate shift clock GSC and supplies it to the second AND gate AND2.

The first AND gate AND1 performs an AND operation between the GSC and the output Qn of n (n is a natural number) flip-flop FF to detect an interval of GSC = High AND Qn = High. The second AND gate AND2 performs an AND operation on the inverted GSC and the output Qn-1 of the (n-1) th flip-flop FF to detect a period in which GSC = Low AND Qn-1 = High. Qn-1 is the output of the (n-1) th flip-flop (FF).

The OR gate OR outputs a result of performing an OR operation on the output of the first AND gate AND1 and the output of the second AND gate AND2.

The third AND gate AND3 outputs a first switch control signal C1 defining t1 at which the charge share CS is implemented. The first third AND gate AND3 ANDs GOE and GSP to output the first switch control signal C1. The remaining third AND gate ANDs the output of the GOE with the output of the OR gate OR to output the first switch control signal C1. The output of the third AND gate AND3 is input to the control terminal of the first switch S1 through the level shifter LS and is input to the neighboring NOR gate NOR.

The NOR gate (NOR) generates a second switch control signal C2 that defines the t2 period. The period t2 is the remaining period excluding the period t1. Therefore, the NOR gate (NOR) receives the output of the neighboring third AND gate (AND3), performs NOR operation, and outputs the second switch control signal (C2). The output of the NOR gate (NOR) is input to the control terminal of the second switch (S2) through the level shifter (LS).

The level shifter LS shifts the input voltage level to the operating voltage of the TFT of the pixel array. The output signal of the level shifter LS swings between the gate high voltage VGH and the gate low voltage VGL. The gate high voltage VGH is higher than the threshold voltage of the TFT and the gate low voltage VGL is higher than the threshold voltage of the TFT.

On the other hand, the level shifter LS is connected to the input terminal of the shift register in the case of the GIP circuit. Therefore, the level shifter LS on the substrate of the display panel can be omitted in the GIP circuit.

The first switch S1 responds to the first switch control signal C1 and applies a charge share CS for the period t1 at the rising edge and the falling edge of the gate signals OUT1, OUT2 and OUT3, respectively. The first switch S1 connected to the first output terminal is supplied with the last output signal Carry of the VGH or the front gate drive IC. The remaining first switches S1 connect the neighboring output terminals. The first switches S1 are simultaneously turned on in response to the first switch control signal C1 to short-circuit all the output terminals to implement the charge share CS. Since the output terminals of the gate driver 103 are connected to the gate lines GL, when the output terminals are short-circuited, the voltage of the gate lines GL is raised or lowered to an intermediate potential between VGH and VGL by charge sharing. During the period t1, the second switches S2 remain off.

The second switch S2 is supplied through the buffer BUF during the other excitation except the t1 period in the rising edge and the falling edge of the gate signals OUT1, OUT2 and OUT3 in response to the second switch control signal C2 VGH or VGL to the output terminals. The second switches S2 are sequentially turned on in synchronization with the outputs Q1, Q2 and Q3 of the shift register sequentially generated. Therefore, the gate signal maintains the VGH potential according to VGH input through the buffer BUF during the t2 period after the t1 period of the rising edge, and is input through the buffer BUF during the t2 period after the t1 period of the falling edge And maintains the VGL potential according to VGL. During the period t2, the first switches S1 remain off.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100: display panel 102: data driver
103: Gate driver 101: Timing controller
104: Host system FF: Flip-flop of shift register
LS: Level shifter BUF: Buffer
NOT: NOT gate AND: AND gate
OR: OR gate NOR: NOR gate
S1: first switch S2: second switch

Claims (8)

A display panel having pixels arranged in a matrix form by an intersection structure of data lines and gate lines; And
And a gate driver for receiving a gate start pulse, a gate shift clock, and a gate output enable signal to generate a gate signal sequentially shifted and supplying the gate signal to the gate lines,
Wherein the gate driver comprises:
A shift register having flip-flops to which the gate start pulse and the gate shift clock are input and are connected in a dependent manner;
Buffers for supplying an output signal of the flip-flop to gate lines;
A first switch for connecting neighboring gate lines in response to a first switch control signal;
A second switch coupled to the buffers in response to a second switch control signal; And
And a logic operation element for generating the first and second switch control signals using the gate start pulse, the gate shift clock, the output of the flip-flop, and the gate output enable signal. The method according to claim 1,
Wherein the first switch control signal defines a first period within the edge period and the polling edge period of the gate signal,
Wherein the second switch control signal defines a second period except for the first period,
The first switch is turned on for a first period,
And the second switch is turned on during a second period. 3. The method of claim 2,
The logic operation element includes:
A NOT gate for inverting the gate shift clock;
An AND gate for performing an AND operation on an output of the NOT gate, an output of the gate start pulse or the flip-flop, and the gate output enable signal to generate the first switch control signal; And
And a NOR gate for receiving an output of neighboring AND gates and performing a NOR operation to generate the second switch control signal. 3. The method of claim 2,
The logic operation element includes:
A NOT gate for inverting the gate shift clock;
A first AND gate for performing an AND operation on the outputs of the gate shift clock and n (n is a natural number) flip-flops;
A second AND gate for performing an AND operation on the output of the NOT gate and the output of the (n-1) th flip-flop;
An OR gate for ORing the outputs of the first AND gate and the second AND gate;
A third AND gate for performing a logical multiplication of the gate output enable signal and the gate start pulse or a logical multiplication of the gate output enable signal and the OR gate output to generate the first switch control signal; And
And a NOR gate for receiving an output of neighboring AND gates and performing a NOR operation to generate the second switch control signal. A shift register having flip-flops to which a gate start pulse and a gate shift clock are input and are connected in a dependent manner;
Buffers for supplying an output signal of the flip-flop to gate lines;
A first switch for connecting neighboring gate lines in response to a first switch control signal;
A second switch coupled to the buffers in response to a second switch control signal; And
And a logic operation element for generating the first and second switch control signals using the gate start pulse, the gate shift clock, the output of the flip-flop, and the gate output enable signal. 6. The method of claim 5,
Wherein the first switch control signal defines a first period within the edge period and the polling edge period of the gate signal,
Wherein the second switch control signal defines a second period except for the first period,
The first switch is turned on for a first period,
And the second switch is turned on during a second period. The method according to claim 6,
The logic operation element includes:
A NOT gate for inverting the gate shift clock;
An AND gate for performing an AND operation on an output of the NOT gate, an output of the gate start pulse or the flip-flop, and the gate output enable signal to generate the first switch control signal; And
And a NOR gate for receiving an output of neighboring AND gates and performing a NOR operation to generate the second switch control signal. The method according to claim 6,
The logic operation element includes:
A NOT gate for inverting the gate shift clock;
A first AND gate for performing an AND operation on the outputs of the gate shift clock and n (n is a natural number) flip-flops;
A second AND gate for performing an AND operation on the output of the NOT gate and the output of the (n-1) th flip-flop;
An OR gate for ORing the outputs of the first AND gate and the second AND gate;
A third AND gate for performing a logical multiplication of the gate output enable signal and the gate start pulse or a logical multiplication of the gate output enable signal and the OR gate output to generate the first switch control signal; And
And a NOR gate for receiving an output of neighboring AND gates and performing a NOR operation to generate the second switch control signal.

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