KR20140076062A - Display device and driving method thereof - Google Patents

Abstract

The present invention relates to a display device. More specifically, the objective of the present invention to provide a display device and a method for driving the same, capable of gradually increasing the size of a gate high voltage (VGH) of scan signals which are sequentially outputted to gate lines from the gate lines that have a short distance to a gate drive IC and that are formed on a first side part toward the gate lines that have a long distance to the gate drive IC and that are formed on a second side part. To achieve the objective, the display device according to the present invention comprises: a panel having pixels which are formed in every cross section of gate lines and data lines; a gate drive IC to sequentially supply san signals to the gate lines; a data drive IC to supply data voltages to the data lines; a timing controller to control operations of the gate drive IC and the data drive IC; and a power supply unit to increase the size of VHG of the scan signals from the gate lines that have a short distance to the gate drive IC and that are formed on a first side part toward the gate lines that have a long distance to the gate drive IC and that are formed on a second side part.

Description

DISPLAY DEVICE AND DRIVING METHOD THEREOF [0002]

The present invention relates to a display device and a driving method thereof, and more particularly to a display device using a chip-on film in which a gate drive IC and a source drive IC are integrally formed on one film and a driving method thereof.

Flat panel displays (FPDs) are used in various types of electronic products including mobile phones, tablet PCs, and notebook computers. The flat panel display includes a liquid crystal display (LCD), a plasma display panel (PDP), and an organic electroluminescence display (OLED). Recently, an electrophoretic display device EPD: ELECTROPHORETIC DISPLAY) is also widely used.

FIG. 1 is a schematic view illustrating a conventional display device, and FIG. 2 is a diagram illustrating voltage drop of a scan signal generated in a conventional display device. Referring to FIG.

In a panel of a conventional general flat panel display (hereinafter simply referred to as a 'display device'), gate lines and data lines are formed to intersect with each other. Therefore, for example, when the source drive IC is in the upper non-display area, the gate connection ICs or the gate connection lines for connecting the gate lines to the gate-in panel (GIP) are connected to left and right non- Respectively.

However, in order to prevent the width of the non-display area from being increased by the gate connection lines formed on the left and right sides of the panel, recently, as shown in Fig. 1, the gate drive IC 20 There has been developed a display device in which a plurality of chip-on films 60, on which a data drive IC 30 is formed on one film 50, are connected to a non-display area above the panel 10.

In this display device, since the gate connection lines are not formed in the non-display area formed on the left and right sides of the panel 10, i.e., the bezel, the bezel can be formed to be at least narrow, A panel can be implemented.

That is, a chip on film 60 for driving a narrow panel has one source drive IC 30, one gate drive IC 20, and the source drive IC 30 And a single film 50 in which the gate drive IC 20 is embedded.

In the conventional display device as described above, the gate connection lines 11a connected to the gate drive IC 20 and the data lines 12 connected to the source drive IC 30 are overlapped At least one data line 12 is connected between two channels (gate connection line 11a) of the gate drive IC 20, as shown in the enlarged circle A in Fig. 1 .

The gate connection lines 11a and the data lines 12 are formed on the panel 10 in parallel with each other.

The gate lines 11 for inputting the scan signals to the pixels formed on the respective horizontal lines of the panel 10 are connected to the data lines (not shown) on the panel 10, 12).

Therefore, each of the gate connection lines 11a for transferring the scan signal output from the gate drive IC 20 to each of the gate lines 11b is in a state of being perpendicular to each of the gate lines 11b As shown in Fig. Each of the gate connection lines 11a is connected to each of the gate lines 11b.

That is, one gate connection line 11a is connected to one gate line 11b. Therefore, one scan signal output from the gate drive IC 20 can be supplied to any one of the gate lines 11b through the one gate connection line 11a.

In this case, as shown in the enlarged rectangle in Fig. 1, one pixel 13 is formed for each region where the gate connection line 11a, the data line 12 and the gate line 11b intersect each other .

The above-described conventional display device has the following problems.

As described above, the scan signal output from the gate drive IC 20 is formed in parallel with the horizontal line of the panel through the gate connection line 11a formed in parallel with the data line 12 The transfer of the scan signal may be delayed in the display device which is transmitted to the gate line 11b, and thus the panel may malfunction.

That is, due to the very large size (60 inches or more, 100 inches) of the panel 10 and the narrowness of the bezel, the widths and spaces of the wirings in the panel become narrow, and resistance and parasitic capacitance increase In particular, in the display device as shown in FIG. 1, since the gate connecting line 11a formed in parallel with the data line 12 is added, the scanning signal is applied to the enlarged square B of FIG. To the gate line 11b via the gate connection line 11a, as indicated by an arrow in Fig.

Accordingly, resistance and parasitic capacitance due to the internal wirings are increased, which may delay the transmission of the scan signal, and may cause malfunction of the panel.

1, the panel 10, which is distant from the upper portion of the panel 10 to which the chip-on film 60 is connected, An image distortion due to a voltage drop and a delay of a scan signal may occur in the gate line 11b formed at the lower end of the gate line 11b.

2, the waveform x of the scan signal output from the gate drive IC 20 and output to the gate line 11b formed at the upper portion of the panel 10, The waveform (y) of the scan signal outputted to the gate line formed at the lower end portion of the panel 10 is compared with the waveform (y) of the scan signal output to the gate line formed at the lower end portion of the panel 10 y), a voltage drop phenomenon is occurring.

Such a voltage drop phenomenon causes a decrease in the charge ratio in the pixel, which causes various problems such as flicker.

In addition to the display device as shown in FIG. 2, the above-described voltage drop phenomenon may also occur in a display device having a configuration in which a length difference occurs between gate drive ICs and gate connection lines connecting the gate lines .

That is, in the case of a display device in which gate lines are connected to gate connection lines having different distances from the gate drive IC regardless of the layout of gate connection lines and gate lines, In the gate line connected to the line, the above-described voltage drop may occur.

SUMMARY OF THE INVENTION The present invention has been proposed in order to solve the above-described problems. It is an object of the present invention to provide a semiconductor device having a gate driver IC and a gate driver IC, And to increase the magnitude of a gate high voltage (VGH) of a scan signal sequentially output to the gate lines toward the gate lines, and a driving method thereof.

According to an aspect of the present invention, there is provided a display device including: a panel having pixels formed in regions where gate lines and data lines intersect; A gate drive IC for sequentially supplying a scan signal to the gate lines; A data drive IC for supplying a data voltage to the data lines; A timing controller for controlling driving of the gate drive IC and the data drive IC; And gate lines formed on a first side of the gate lines, which are short in distance from the gate drive IC, to gate lines formed on a second side, the gate lines being longer in distance from the gate drive IC, And a power supply unit capable of increasing a magnitude of a gate high voltage (VGH) of the scan signal.

According to another aspect of the present invention, there is provided a method of driving a display device, the method comprising: receiving a power control signal; Generating a switching voltage using the power control signal; And a gate driver IC for outputting the gate high voltage to the gate line and a gate driver IC for outputting the gate high voltage of the scan signal outputted to the gate lines formed on the panel for one frame period according to the switching voltage, And a step of outputting the changed data according to the distance from the line.

According to the present invention, a voltage drop phenomenon in the gate lines formed on the second side, which is distant from the first side, to which the chip-on film with the gate drive IC and the source drive IC are connected, Image quality defects can be improved.

1 is an exemplary view schematically showing a conventional display device;
BACKGROUND OF THE INVENTION 1. Field of the Invention [0001]
Fig. 3 is an exemplary view schematically showing a display device according to the present invention. Fig.
FIG. 4 is an internal configuration diagram of a power supply unit applied to a display device according to the present invention. FIG.
5 is a waveform diagram of signals output from the PWM unit shown in FIG.
6 is an exemplary view showing the configuration of the PWM unit shown in FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Hereinafter, for convenience of explanation, a liquid crystal display device will be described as an example of the present invention, but the present invention is not limited thereto. That is, the present invention can be applied to various display devices capable of displaying an image by supplying a scan signal to a gate line.

For convenience of explanation, a display device in which a chip-on film including a source drive IC, a gate drive IC, a film on which the source drive IC and the gate drive IC are mounted is connected to a panel is described as an example of the present invention . However, the present invention is not limited thereto. That is, the present invention can be applied to various types of display devices configured such that a length difference occurs between gate drive ICs and gate connection lines connecting the gate lines.

FIG. 3 is a schematic view showing a display device according to the present invention, FIG. 4 is a diagram showing the internal configuration of a power supply part applied to a display device according to the present invention, FIG. 6 is an exemplary diagram illustrating a configuration of the PWM unit shown in FIG. 4. Referring to FIG.

3, the display device according to the present invention includes a panel 100 in which pixels are formed in regions where gate lines GL1 to GLn and data lines DL1 to DLm intersect, A data drive IC 300 for supplying a data voltage to the data lines, a gate drive IC 200 for supplying a scan signal to the gate drive IC 200 and the data drive IC 300 A timing controller 400 for controlling the driving of the gate driver IC 200 and a plurality of gate lines GL1 to GLn provided on the first side portion 160, A power supply unit 700 capable of increasing the size of the gate high voltage VGH of the scan signal toward the gate lines formed in the second side portion 160 having a long distance from the gate drive IC 200, ).

The source driver IC 300 converts the digital image data transmitted from the timing controller 400 into analog data voltages and transmits the analog data voltages to the data lines DL formed on the panel 100.

That is, the source driver IC 300 converts the image data into the data voltage using the gamma voltages supplied from the gamma voltage generator (not shown), and outputs the data voltage to the data line.

To this end, the source drive IC 300 includes a shift register unit, a latch unit, a digital-analog converter (DAC), and an output buffer.

The source drive IC 300 may receive the image data from the timing controller 400 using an EPI interface but may receive the image data from the timing controller 400 using a mini-LVDS method, And may receive image data.

The shift register unit generates a sampling signal using data control signals (SSC, SSP, etc.) received from the timing controller (400).

The latch unit latches the digital image data (Data) sequentially received from the timing controller (400), and simultaneously outputs the digital image data (Data) to the digital-analog converter (DAC).

The digital-to-analog converter converts the image data transmitted from the latch unit into a data voltage of positive or negative polarity and outputs the same. That is, the digital-analog converter converts the image data into a positive or negative data voltage (data signal) using the polarity control signal POL transmitted from the timing controller 400, and outputs the data voltage to the data lines do.

The digital-to-analog converter converts the image data into the data voltage using a driving voltage (VDD) supplied from the power supply unit 700.

The output buffer outputs the positive or negative polarity data voltage transmitted from the digital-analog converter to the data lines of the panel in accordance with the source output enable signal SOE transmitted from the timing controller 400 do.

The output buffer amplifies the data voltage transmitted from the digital-analog converter using the driving voltage (VDD) supplied from the power supply unit 700, and outputs the amplified data voltage to data lines formed on the panel.

Next, the gate drive IC 200 generates a scan signal according to a gate control signal transmitted from the timing controller 400, and supplies the scan signal to the gate line (not shown) through a gate connection line 110a formed in the panel. GL.

The gate drive IC 200 and the source drive IC 300 may be individually formed on a panel or a flexible film and connected to the gate lines and the data lines. However, as shown in FIG. 3, And may be mounted on the film 600. [

That is, the chip-on film 600 connected to the first side portion 160 of the panel 100 is connected to the source drive IC 300 and the gate drive IC 200 and the source drive IC 300, And a film 500 formed of a flexible material on which the gate drive IC 200 is mounted.

Here, the first side portion 160 refers to a region having a short distance from the gate drive IC 200 among regions where the gate lines are formed, and the second side portion 170 refers to a region The gate drive IC 200 has a relatively long distance from the gate drive IC 200. [

More specifically, a region where the length of the gate connection line 110a connecting the gate drive IC 200 and the gate line is relatively long, rather than the distance from the gate drive IC 200, Two side portions 170 are formed.

That is, the length of the gate connection line 110a connected to the gate line formed in a region distant from the gate drive IC 200 is formed in a region close to the gate drive IC 200 Is longer than the length of the gate connection line 110a connected to the gate line. Thus, the two representations described above can be interpreted in the same sense.

Although the present invention will be described with reference to a display device in which the source drive IC 300 and the gate drive IC 200 are formed on the chip-on film 600 as described above, The present invention can also be applied to a display device in which the source drive IC 300 and the gate drive IC 200 are formed in different positions at different positions.

That is, the gate drive IC 200 may be connected to the panel 100 in a state where the gate drive IC 200 is separated from the source drive IC 300 and mounted on a separate film, Gate In Panel (GIP) method.

On the other hand, when the gate drive IC 200 and the source drive IC 300 are formed on the chip-on film 600 as shown in FIG. 3, At least one source line 310 of the source lines may be connected to the data line DL through a channel (port or gate connection line) of the gate drive IC 200.

The number of the gate drive IC 200 and the source drive IC 300 and the number of the chip-on film 600 can be variously set according to the size and resolution of the panel.

Next, the panel 100 includes a thin film transistor (TFT) formed at each intersection of the gate lines GL1 to GLn and the data lines DL1 to DLm, and pixels including a pixel electrode do.

The thin film transistor TFT supplies a data voltage (video signal) supplied from the data line 120 to the pixel electrode in response to a scan signal supplied from the gate line 110a. The pixel electrode adjusts the transmittance of light by driving a liquid crystal positioned between the pixel electrode and the common electrode in response to the data voltage.

The liquid crystal mode of the panel applicable to the present invention may be any mode of liquid crystal mode as well as a TN mode, a VA mode, an IPS mode, and an FFS mode. Further, the liquid crystal display device according to the present invention can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, and a reflective liquid crystal display device.

In addition to the above-described liquid crystal panel, the panel 100 may be applied to various types and types of panels configured to output an image according to a scan signal supplied to the gate line 110b.

On the other hand, when the source drive IC 300 and the gate drive IC 200 are composed of one chip-on film 600 as described above, the gate line 110b and the data line 120 , A gate connection line 110a for connecting the gate drive IC 200 and the gate line 110b may be further formed.

In this case, data lines 120 connected to the source drive IC 300, the gate drive IC 200, and the data lines 120b are disposed in the panel 100, And gate lines 110b perpendicular to the gate connection lines 110a and the data lines 120 and connected to the gate connection lines 110a are formed .

Therefore, as shown in FIG. 3, one gate line 110a and one data line 120 are formed in parallel to the gate connection line 110a, and the gate connection line 110a, One pixel P is formed for each crossing region of one gate line 110b formed in the data line 120 perpendicularly.

Next, the timing controller 400 aligns input image data (Input RGB) input from an external system according to the structure and characteristics of the panel, and transmits the aligned image data to the data drive IC 300 .

The timing controller 400 may use the timing signals transmitted from the external system, that is, the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the data enable signal DE, Generates a data control signal DCS for controlling the IC 300 and a gate control signal GCS for controlling the gate drive IC 200 and outputs the control signals to the data drive IC and the gate drive IC And performs the function of transmitting.

The gate control signals GCS generated in the timing controller 400 may vary according to the type of the gate drive IC. For example, the gate drive IC 200 may be formed on the chip-on-film (COF) 600 as described above, or may be separated from the source drive IC 300 in the form of a separate tape carrier package (TCP) A gate shift clock GSC, a gate output enable signal GOE, and the like are included in the gate control signals generated by the timing controller 400. [ In the case of the GIP type in which the gate drive IC 200 is mounted on the panel, the gate control signals generated in the timing controller 400 include a gate start signal VST, a gate clock GCLK, .

The data control signals generated by the timing controller 400 include a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, a polarity control signal POL, and the like. However, these data control signals can be changed in various forms depending on whether the interface method used between the timing controller and the data drive IC is a TTL method, a mini LVDS method, or an EPI method. The timing controller 400 is mounted on the main board 800 and the main board 800 is connected to the panel 100 through the chip-on film 600.

Lastly, the power supply 700 supplies power to the timing controller 400, the gate drive IC 200, and the source drive IC 300 using the input voltage VIN input from the external system. Generate power.

The power supply unit 700 supplies power from the gate lines formed in the first side portion 160 of the gate lines GL1 to GLn to the gate drive IC 200, (VGH) of the scan signal to the gate lines formed on the second side portion 170, which are long in distance from the scan line 200, to increase the size of the gate high voltage VGH of the scan signal.

Here, the scan signal is output to the gate line 110b to turn on or turn off a thin film transistor (TFT) formed in each pixel.

When the data voltage of one horizontal line is output from the source drive IC 300 to the data line DL, the scan signal is supplied to the gate line 110b for one horizontal period, And a low-level gate-low voltage (VGL) output to the gate line for the remaining one frame period after the data voltage is output.

That is, when the scan signal having the gate high voltage VGH is output to the gate line, the thin film transistor connected to the gate line is turned on, and the data voltage is supplied to the pixels in which the thin film transistor is formed Whereby an image is output to the panel.

Further, the scan signal having the gate-low voltage (VGL) is output to the gate line before the data voltage is supplied to the data line during one frame period and after the data voltage is supplied to the data line .

Particularly, in the one frame period, the power supply unit 700 supplies power from the gate lines formed on the first side portion 160 to the gate lines formed on the second side portion 170, The magnitude of the gate high voltage VGH may be increased for each gate line.

That is, the length of the gate connection line 110a increases from the first side 160 to the second side 170. Accordingly, the voltage drop phenomenon described with reference to FIG. 2 is severely generated from the first side portion 160 to the second side portion 170.

In order to overcome this problem, the present invention is characterized in that from the gate lines formed on the first side portion 160 to the gate lines formed on the second side portion 170, The magnitude of the voltage VGH is increased, and this function is performed in the power supply unit 700.

The reason why the gate high voltage VGH is changed to one frame period is because the gate line at which the gate high voltage VGH is output is repeated every frame.

The power supply unit 700 may supply the first gate line group from the first gate line group formed in the first side portion 160 among the gate line groups formed of at least two gate lines during one frame period, The magnitude of the gate high voltage VGH may be increased for each gate line group toward the kth gate line group formed in the side portion 170. [ Here, the first gate line group is formed in a region closest to the gate drive IC 200, and the k-th gate line group is formed in an area furthest from the gate drive IC 200.

That is, the power supply unit 700 supplies the gate-to-source voltage to the gate lines formed in the second side portion 170 from the gate lines formed in the first side portion 160 during one frame period, When the voltage VGH is output, the gate high voltage VGH may be sequentially increased for each gate line, and the gate high voltage VGH may be sequentially output. After at least two or more gate lines are grouped into gate line groups, The gate high voltage VGH may be increased.

The power supply unit 700 may use any one of a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, or a gate control signal or a data control signal generated from the timing controller, The magnitude of the gate high voltage can be changed for each one frame period.

That is, the gate high voltage VGH increases from the gate lines formed in the first side portion 160 to the gate lines formed in the second side portion 170 during one frame period, When the one frame period ends, the gate high voltage (VGH) is changed to the smallest gate high voltage (VGH), and another one frame period starts. Then, from the gate lines formed in the first side portion 160, The power supply unit 700 changes the size of the gate high voltage for each one frame period by using signals capable of distinguishing each frame, .

For example, the vertical synchronization signal (Vsync) has a repetition period for each frame, and the power supply unit 700 uses the vertical synchronization signal as the power control signal PCS to generate the gate high voltage VGH) can be changed.

The horizontal synchronization signal Hsync defines a period during which the data voltage is output, and the one frame period may be defined by the number of the horizontal synchronization signal Hsync. Accordingly, the power supply unit 700 may count the horizontal synchronizing signal Hsync, define the one frame period, and then change the size of the gate high voltage VGH during the one frame period.

Also, the power supply unit 400 may define one frame period using various control signals as described above, and then change the size of the gate high voltage (VGH) during the one frame period.

Here, the various control signals for defining one frame period are collectively referred to as a power control signal (PCS).

4, the power supply unit 400 uses the input voltage and the power control signal PCS input from the external system to perform the above-described functions, A PWM (Pulse Width Modulation) unit 710 for outputting a switching voltage SV capable of sequentially changing the magnitude of the gate high voltage, a gate high voltage generating unit 710 for generating the gate high voltage according to the switching voltage SV, A gate low voltage generator 730 for generating a gate low voltage VGL of the scan signal by using an output voltage from the PWM unit 710, And a driving voltage generator 740 for generating and outputting a driving voltage VDD to be supplied to the source driver IC 300 using the output voltage output from the PWM unit 710.

The PWM unit 710 boosts or bucks the input voltage VIN according to a pulse width of a switching signal generated internally to generate a plurality of output voltages.

In particular, the PWM unit 710 generates a switching voltage SV capable of sequentially changing the magnitude of the gate high voltage every frame period by using the input voltage and the power control signal PCS. That is, according to the magnitude of the switching voltage SV, the gate high voltage generator 720 generates a gay high voltage VGH having different magnitudes.

The PWM unit 710 is a PWM integrated circuit (IC) (PWM-IC) having output pins such as drive for negative charge pump (DRN), feedback for negative charge pump Lt; / RTI >

5A and 6, the PWM unit 710 includes a reference swing block (Ref Swing Block) for generating a rectangular wave having a predetermined frequency and a reference swing block And a ramp block (Ramp Block) for outputting the triangular wave as the switching voltage SV as shown in (b) of FIG. 5 by using the square wave generated by using the square wave (MUX).

The reference swing block generates a Vref Swing signal (square wave) as shown in FIG. 5A by using the MUX as two channels.

The ramp block is turned on during a high time (ON time) of the Vre Swing signal (rectangular wave) as shown in FIG. 5A, As shown in Fig. The ramp block is turned off during a low time (OFF) of the Vre Swing signal (square wave), and outputs a Gradual Vref (for example, 1.1 V DC) as a final output.

The PWM unit 710 configured as described above generates a square wave as shown in FIG. 5 (a) by using the input voltage and the power control signal PCS, and outputs the square wave pulse width And the PWM unit 710 outputs the triangular wave as the switching voltage SV to the gate high voltage generator 720. [ In other words, the triangular wave is input to the gate high voltage generator 720 to vary the magnitude of the gate high voltage VGH.

That is, a rectangular wave as shown in FIG. 5 (b) is generated through a mux of the reference swing block, and the triangle wave (or sawtooth wave) is generated through the ramp block , The sawtooth wave is input to the gate high voltage generator 720 with the switching voltage SV to vary the magnitude of the gate high voltage.

Here, the power control signal PCS may be a vertical synchronization signal Vsync as described above. For example, the vertical synchronization signal may be a control signal of the reference swing block, and the pulse (square wave) described above may be generated by the vertical synchronization signal. The level of the square wave may be determined as Vref (+) and Vref (-) as shown in FIG.

To be more specific, the PWM unit 710 repeats the process of changing the magnitude of the gate high voltage VGH every frame by the power control signal PCS.

Also, the PWM unit 710 may generate a periodic signal for changing the magnitude of the gate high voltage VGH using the power control signal PCS. For example, as described above, when the magnitude of each gate high voltage to be output to one gate line increases, a periodic signal corresponding to a period in which the gate high voltage is output is generated, and two or more gate lines The periodic signal corresponding to the output period of the gate group is generated when the magnitude of the gate high voltage increases for each gate group formed by the gate group.

The PWM unit 710 varies the magnitude of the switching voltage for each periodic signal. In this case, the PWM unit 710 may vary the magnitude of the switching voltage using the switching information stored in the PWM unit 710 or an external memory. That is, the PWM unit 710 may change the magnitude of the switching voltage by varying the pulse width or magnitude of the square wave to a predetermined value according to the period signal, and varying the size of the triangular wave.

The gate high voltage generator 720 generates the gate high voltage from the gate lines formed in the first side 160 during one frame period using the switching voltage generated by the PWM unit 710, The gate high voltage VGH output to the gate lines formed in the two side portions 170 is increased. That is, the gate high voltage generator 720 varies the magnitude of the gate high voltage VGH according to the magnitude of the switching voltage.

The gate low voltage generator 730 generates the gate low voltage VGH to be output to the gate lines where the gate high voltage VGH is not outputted by using the output voltage and the charge pump generated by the PWM unit 710, (VGL).

The driving voltage generator 740 generates a driving voltage VDD using the output voltage and the charge pump and outputs the driving voltage VDD to the source driver IC 300. The driving voltage VDD is used as a gamma reference voltage or the like in the source drive IC 300.

A driving method of the display device as described above will be briefly summarized as follows.

First, the power supply unit 700 receives the power control signal PCS.

Next, the power supply unit 700 generates the switching voltage using the power control signal.

Lastly, the power supply unit 700 adjusts the magnitude of the gate high voltage (VGH) of the scan signal output to the gate lines formed on the panel for one frame period according to the switching voltage to the gate line And changes the value according to the distance between the gate drive IC 200 outputting the gate high voltage and the gate line.

At this time, the power supply unit 700 may be configured such that the distance from the gate drive IC 200 connected to the panel is shortened from the gate lines formed on the first side, And increases the size of the gate high voltage VGH toward the gate lines formed on the long side and the second side.

The power supply unit 700 may be configured such that during the one frame period, from the gate lines formed on the first side portion 160 to the gate lines formed on the second side portion 170, The gate high voltage VGH may be increased in the first gate line group or the first gate line group formed in the first side among the gate line groups formed by at least two gate lines The gate high voltage (VGH) may be increased for each gate line group toward the kth gate line group formed on the second side portion.

It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

100: Panel 500: Film
300: Source drive IC 200: Gate drive IC
600: chip-on film 400: timing controller
700: power supply unit 800: main board

Claims (10)

A panel in which pixels are formed in each of regions where gate lines and data lines intersect;
A gate drive IC for sequentially supplying a scan signal to the gate lines;
A data drive IC for supplying a data voltage to the data lines;
A timing controller for controlling driving of the gate drive IC and the data drive IC; And
The gate lines are formed in the first side portion of the gate lines, the gate lines being formed in the second side portion, which is long in distance from the gate drive IC, from the gate lines formed in the first side portion, And a power supply unit capable of increasing the size of the gate high voltage (VGH) of the scan signal. The method according to claim 1,
The power supply unit,
During the one frame period, the gate high voltage (VGH) is increased from the gate lines formed on the first side portion to the gate lines formed on the second side portion, . The method according to claim 1,
The power supply unit,
A first gate line group formed on the first side portion and a second gate line group formed on the second side portion among the gate line groups formed of at least two gate lines during one frame period And increases the size of the gate high voltage (VGH) for each gate line group. The method according to claim 1,
The power supply unit,
A method of driving a liquid crystal display device, comprising: using a vertical synchronization signal, a horizontal synchronization signal, a data enable signal input from an external system, or a gate control signal or a data control signal generated by the timing controller, Of the display device (10). The method according to claim 1,
The power supply unit,
A PWM unit for outputting a switching voltage capable of changing the magnitude of the gate high voltage sequentially in every one frame period using an input voltage and a power control signal input from an external system; And
And a gate high voltage generator for generating the gate high voltage according to the switching voltage and outputting the gate high voltage to the gate drive IC. The method according to claim 1,
Wherein the chip-on film connected to the first side of the panel comprises a film on which the source drive IC, the gate drive IC, the source drive IC and the gate drive IC are mounted. The method according to claim 6,
The panel includes data lines connected to the source drive IC, gate connection lines connected to the gate drive IC and arranged in parallel with the data lines, and gate connection lines arranged perpendicular to the gate connection line and the data lines. And gate lines connected to the gate connection line are formed on the gate line. Receiving a power control signal;
Generating a switching voltage using the power control signal; And
A gate driver IC for outputting the gate high voltage to the gate line and a gate driver IC for outputting the gate high voltage to the gate line, And outputting the changed output signal. 9. The method of claim 8,
The step of varying the magnitude of the gate high voltage to output,
The distance from the gate drive ICs connected to the panel to the gate lines formed on the first side is shorter than the distance from the gate drive ICs to the gate lines formed on the second side, And increases the magnitude of the gate high voltage (VGH) and outputs the increased voltage. 10. The method of claim 9,
The gate line group formed from the first gate line group to the gate line group formed from the first side portion to the k-th gate line group formed at the second side portion among the gate line groups formed from at least two gate lines, And increases the size of the gate high voltage (VGH) for each group.

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