KR102450256B1 - Liquid Crystal Display - Google Patents

Abstract

A liquid crystal display device according to an embodiment of the present invention. A plurality of sub-pixels defined in the intersection region of the plurality of gate lines (G) and the plurality of data lines (D), and a plurality of thin film transistors disposed in each of the plurality of sub-pixels and controlled by the gate line (G) ( T), the display panel 100 outputs a first voltage V1 based on the input high-level power voltage Vcc, and based on the power supply voltage Vcc of the input preset voltage Vset. DC converter 510 for outputting a second voltage V2 to output a gate high voltage Vgh based on the input first voltage V1, and outputting a gate high voltage Vgh based on the input second voltage V2. A level shifter 520 that outputs a discharge voltage DSC higher than the gate high voltage Vgh, outputs the gate high voltage Vgh to each of the plurality of gate lines G, and outputs the discharge voltage DSC and a gate driving circuit 400 for outputting . can provide

Description

Liquid Crystal Display {Liquid Crystal Display}

The present invention relates to a liquid crystal display device, and more specifically, to an invention for removing a residual voltage when the power supply of the liquid crystal display device is turned off.

With the development of various portable devices such as mobile phones, laptops, and computers, and information electronic devices that implement high-resolution and high-quality images such as HDTVs, flat panel displays applied thereto device) is gradually increasing. Although LCD (Liquid Crystal Display), PDP (Plasma Display Panel), FED (Field Emission Display) and OLED (Organic Light Emitting Diodes) have been actively studied as such flat panel display devices, mass production technology, ease of driving means, and high quality Liquid crystal display (LCD) is currently in the spotlight due to the reason of realization and realization of a large-area screen. Recently, it is expanding to the area of 3D display and flexible display.

In a thin film transistor (TFT) liquid crystal display device, an active matrix structure in which a switch element is composed of a TFT and is placed in each pixel to perform control individually has resolution, contrast ratio, and viewing angle compared to a simple matrix structure. It is a structure that can improve its properties.

In the active matrix structure, a data signal collectively applied to the thin film transistors of a horizontal line turned on by a gate signal that is sequentially turned on is scanned. After the gate is turned off, it operates according to the driving principle of holding the charge charged to the pixel voltage until the next frame.

Such a liquid crystal display has a problem in that unevenness occurs due to the accumulation of DC voltage in the panel.

A liquid crystal display device according to an embodiment of the present invention. A plurality of sub-pixels defined in the intersection region of the plurality of gate lines (G) and the plurality of data lines (D), and a plurality of thin film transistors disposed in each of the plurality of sub-pixels and controlled by the gate line (G) ( T), the display panel 100 outputs a first voltage V1 based on the input high-level power voltage Vcc, and based on the power supply voltage Vcc of the input preset voltage Vset. DC converter 510 for outputting a second voltage V2 to output a gate high voltage Vgh based on the input first voltage V1, and outputting a gate high voltage Vgh based on the input second voltage V2. A level shifter 520 that outputs a discharge voltage DSC higher than the gate high voltage Vgh, outputs the gate high voltage Vgh to each of the plurality of gate lines G, and outputs the discharge voltage DSC and a gate driving circuit 400 for outputting . can provide In addition, in the liquid crystal display according to the embodiment of the present invention, the DC converter 510 includes a discharge circuit 530 for outputting any one of the first and second voltages V1 and V2, and the discharge circuit 530 outputs a discharge control signal DC to the level shifter 520 in synchronization with the power supply voltage Vcc of a preset voltage Vset, and the level shifter 520 outputs the discharge control signal ( DC) based on the discharging voltage DSC, a discharging sequence is performed when the display is turned off to prevent unevenness due to the residual voltage of the display panel 100 , and the discharging sequence in the display panel 100 is performed. As the level of the discharge voltage DSC, which is a voltage for turning on the thin film transistor T, is raised, the discharge function can be improved by compensating for a voltage drop according to the resistance of the display panel 100, and the display panel ( According to the size of the display panel 100 , the second reference voltage Vref2 at an appropriate level can be set according to the resistance of the display panel 100 , so that the liquid crystal display device capable of improving the discharge function can be provided.

In addition, in the liquid crystal display according to the embodiment of the present invention, the DC converter 510 amplifies the power supply voltage Vcc to output any one of the first and second voltages V1 and V2. ), the control unit 550 and the control unit 550 for adjusting the amount of amplification of the amplifier 540 and feedback control of the output signal of the amplifier 540 to change the output voltage of the amplifier 540 to the input reference voltage. The output of the amplifier 540 close to the reference voltage Vref by using the feedback control system of the amplifier 540 and the control unit 550 including the reference voltage generator 560 for outputting the reference voltage Vref. Since the voltage Vo can be generated, by setting the reference voltage Vref differently depending on whether or not the discharge sequence is present, the amplifier 540 generates the thin film transistor T in the display panel 100 suitable for each of the display period and the discharge sequence. ), it is possible to provide a liquid crystal display capable of generating a voltage for turning on.

In addition, in the liquid crystal display according to an embodiment of the present invention, the reference voltage generator 560 detects a change in the power supply voltage Vcc and outputs any one of the first and second reference voltages Vre1 and Vref2. , the reference voltage generator 560 may detect a change in the input voltage Vcc to detect the display off, and accordingly output different reference voltages Vref, suitable for each display period and discharge sequence. It is possible to provide a liquid crystal display device capable of generating a voltage for turning on the thin film transistor T in the display panel 100 .

In addition, in the liquid crystal display according to the embodiment of the present invention, the reference voltage generator 560 outputs an output signal of a first level based on the high level of the power voltage Vcc, and the preset voltage Vset ) of a preset voltage detector 561 that outputs an output signal of a second level based on the power supply voltage Vcc, and a switch driving signal of a different logic level according to the level of the output signal of the preset voltage detector 561 A switch driver 562 that outputs 570) may be provided.

In addition, in the liquid crystal display according to the embodiment of the present invention, the reference voltage setting unit 570 includes the first and second switch elements S1 and S2 controlled by the output signal from the switch driver 562, the A first reference voltage setting unit 563 that outputs a first reference voltage Vref1 to the control unit 550 through a first switch element S1 and the control unit 550 through the second switch element S2 The liquid crystal display device including the second reference voltage setting unit 565 for outputting the second reference voltage Vref2 may be provided.

In addition, in the liquid crystal display according to an embodiment of the present invention, the first and second switch elements S1 and S2 are N-type MOSFETs, and the reference voltage setting unit 565 is By further including an inverter 564 for inverting the output signal and outputting the output signal to the gate terminal of the second switch element S2, the first and second switch elements S1 and S2 are formed in the same type, the switch It is possible to provide a liquid crystal display device capable of improving operation accuracy by preventing a switching driving deviation due to a material difference of elements.

In addition, in the liquid crystal display device according to an embodiment of the present invention, the first switch element S1 is an N-type MOSFET, and the second switch element S2 is formed of a P-type MOSFET, so that the output of the switch driver 562 is It is not necessary to provide a separate inverter for inverting the signal, so that it is possible to provide a liquid crystal display in which circuit complexity can be reduced.

The liquid crystal display device according to an embodiment of the present invention may provide a liquid crystal display device capable of preventing unevenness due to residual voltage of a display panel by performing a discharge sequence when the display is turned off.

In addition, the liquid crystal display device according to an embodiment of the present invention has a discharge function by compensating for a voltage drop according to the resistance of the display panel as the level of the discharge voltage, which is a voltage for turning on the thin film transistor in the display panel, is increased during the discharge sequence. It is also possible to provide an improved liquid crystal display device.

In addition, the liquid crystal display device according to the embodiment of the present invention can set a reference voltage of an appropriate level suitable for the resistance of the display panel according to the size of the display panel, etc., so that it is possible to provide a liquid crystal display with improved discharge function.

The liquid crystal display according to an embodiment of the present invention may perform a discharging sequence when the display is turned off, thereby preventing unevenness due to the residual voltage of the display panel.

In addition, as the level of the discharge voltage, which is a voltage for turning on the thin film transistor in the display panel, is increased during the discharge sequence, the discharge function may be improved by compensating for a voltage drop according to the resistance of the display panel. In addition, it is possible to set a reference voltage of an appropriate level suitable for the resistance of the display panel according to the size of the display panel, etc., so that the discharge function can be improved.

1 is a view showing a liquid crystal display device according to an embodiment of the present invention.
2 is a block diagram illustrating a power supply unit according to an embodiment of the present invention;
3 is an operation timing diagram of the power supply unit;
4 is a circuit diagram showing a discharge circuit;
5 is a detailed circuit diagram of a reference voltage generator;

Hereinafter, with reference to the drawings of a liquid crystal display according to an embodiment of the present invention will be described in detail. The embodiments introduced below are provided as examples so that the spirit of the present invention can be sufficiently conveyed to those skilled in the art. Accordingly, the present invention is not limited to the embodiments described below and may be embodied in other forms. And, in the drawings, the size and thickness of the device may be exaggerated for convenience. Like reference numbers refer to like elements throughout.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be embodied in various different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the art to which the present invention pertains It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout. The sizes and relative sizes of layers and regions in the drawings may be exaggerated for clarity of description.

The terminology used herein is for the purpose of describing the embodiments, and thus is not intended to limit the present invention. In this specification, the singular also includes the plural, unless specifically stated otherwise in the phrase. As used herein, “comprise” and/or “comprising” refers to the presence of one or more other components, steps, operations and/or elements mentioned. or addition is not excluded.

<Liquid crystal display device according to the embodiment>

1 is a view showing a liquid crystal display device according to an embodiment of the present invention.

Referring to FIG. 1 , a liquid crystal display 10 according to an embodiment of the present invention includes a display panel 100 , a timing controller 200 , a data driving circuit 300 , a gate driving circuit 400 , and a power supply unit 500 . And a system board 20 may be provided. In addition, the timing controller 200 , the data driving circuit 300 , the gate driving circuit 400 , and the power supply unit 500 may be referred to as driving units for driving the display panel 100 .

The display panel 100 includes liquid crystal molecules disposed between two glass substrates. In the display panel 100 , m × n (m, n is a positive integer) sub-pixel regions are defined in a matrix form by an intersecting structure of the data lines D1 to Dm and the gate lines G1 to Gn. and liquid crystal cells Clc are disposed in each of the sub-pixel regions. In addition, the sub-pixel area defined by the intersection of the plurality of gate lines and the plurality of data lines includes a first sub-pixel displaying a first color, a second sub-pixel displaying a second color, and a third sub-pixel displaying a third color. a first sub-pixel including a sub-pixel, a first sub-pixel displaying a first color, a second sub-pixel displaying a second color, a third sub-pixel displaying a third color, and a fourth sub-pixel displaying a fourth color include The first color means Red, the second color means Green, the third color means Blue, and the fourth color means White do.

The lower glass substrate of the display panel 100 is connected to m data lines D1 to Dm, n gate lines G1 to Gn, a thin film transistor (TFT), and TFTs, respectively. A sub-pixel including the pixel electrode 110 of the liquid crystal cell Clc and the storage capacitor Cst may be formed.

A black matrix, a color filter, and a common electrode 120 may be formed on the upper glass substrate of the display panel 100 . The common electrode 120 is formed on the upper glass substrate in a vertical electric field driving method such as TN (Twisted Nematic) mode and VA (Vertical Alignment) mode, IPS (In Plane Switching) mode and FFS (Fringe Field Switching) mode and In the same horizontal electric field driving method, it may be formed on the lower glass substrate together with the pixel electrode 1 .

The liquid crystal mode of the liquid crystal display panel 10 applicable in the present invention may be implemented in any liquid crystal mode as well as the aforementioned TN mode, VA mode, IPS mode, and FFS mode.

In addition, the liquid crystal display of the present invention may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, or a reflective liquid crystal display. In the transmissive liquid crystal display device and the transflective liquid crystal display device, a backlight unit omitted from the drawings is required.

A polarizing plate having an optical axis orthogonal to each other is attached to the upper glass substrate and the lower glass substrate of the display panel 100 , and an alignment layer for setting a pretilt angle of the liquid crystal may be formed on the inner surface in contact with the liquid crystal.

The system board 20 may supply a timing signal including a vertical/horizontal synchronization signal, a dot clock signal, a data enable signal, and the like, digital video data, and a power voltage Vcc to the timing controller 200 . The power voltage Vcc may be supplied to a digital circuit unit such as the timing controller 200 , the data driving circuit 300 , the gate driving circuit 200 , and the power supply unit 500 . The system board 20 has a built-in scaler circuit to adjust the resolution of digital video data to be supplied to the timing controller 200 . The system board 20 may transmit a timing signal and digital video data to the timing controller 200 through a low voltage differential signaling (LVDS) interface.

The data driver circuit 300 may include a plurality of data driver integrated circuits. The data driving circuit 300 latches digital video data (RGB or RGBW) under the control of the timing controller 200 and converts the digital video data into analog positive/negative gamma compensation voltage to obtain positive/negative data voltage can be generated. Each of the plurality of data driver integrated circuits may provide a data signal to each of the plurality of grouped data lines D1 to Dm. Accordingly, the number of the data driver integrated circuits may vary according to the degree of grouping of the data driver integrated circuits according to the resolution of the liquid crystal display device.

The data driving circuit 300 may supply a data voltage to the data lines D1 to Dm during each horizontal period in which the source output enable signal SOE is maintained at a low logic level.

The data driver integrated circuits may be mounted on a tape carrier package (TCP) and bonded to the lower glass substrate of the display panel 100 by a tape automated bonding (TAB) process.

The gate driving circuit 400 includes a shift register, a level shifter for converting the output signal of the shift register to a swing width suitable for driving the TFT of the liquid crystal cell, and an output buffer connected between the level shifter and the gate lines G1 to Gn. etc. may be included. The gate driving circuit 400 may sequentially supply gate signals having a pulse width of approximately one horizontal period to the gate lines G1 to Gn under the control of the timing controller 200 . The gate driving circuit 400 is mounted on the TCP and bonded to the lower glass substrate of the display panel 100 by the TAB process, or directly on the lower glass substrate simultaneously with the pixel array by the GIP (Gate driver In Panel) process. can be formed.

Unlike FIG. 1 , the gate driving circuit 400 of the liquid crystal display 10 according to the embodiment of the present invention may be a gate in panel (GIP) type in which a level shifter and a shift register are separated. . In this case, the level shifter may be included in the power supply unit 500 , and may be disposed on a printed circuit board separate from the power supply unit 500 .

The power supply unit 500 supplies power required to drive the liquid crystal display device using the power voltage Vcc input from the system board 20 to the data and gate driving circuits 300 and 400 and the timing controller 200 , etc. can provide

The timing controller 200 is driven by the power supply voltage Vcc from the system board 20 to align digital video data received from the system board 20 through the LVDS receiving circuit and supply it to the data driving circuit 300 . can In addition, when the display panel 100 includes the first to fourth sub-pixels, digital video data (RGB) input from the system board 20 is converted into RGBW video data and rearranged to fit the display panel 100 . It may be supplied to the data driving circuit 300 . In addition, the timing controller 200 receives timing signals such as vertical/horizontal synchronization signals (Vsync, Hsync), data enable, and clock signal CLK from the system board 20 and receives the data driving circuit 300 ) and control signals GCS and DCS for controlling the operation timing of the gate driving circuit 400 may be generated.

A gate timing control signal GCS for controlling the gate driving circuit 400 includes a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable signal (Gate Output Enable). , GOE) and the like. The gate start pulse GSP is applied to the first gate drive IC that generates the first gate pulse (or scan pulse). The gate shift clock GSC is a clock signal commonly input to the gate drive ICs and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls outputs of the gate drive ICs. The data timing control signal includes a source start pulse (Source, Start Pulse, SSP), a source sampling clock (SSC), a polarity control signal (POL), and a source output enable signal (SOE). and the like. The source start pulse SSP controls a data sampling start time of the data driving circuit 300 . The source sampling clock SSC is a clock signal that controls a sampling operation of data in the data driving circuit 300 based on a rising or falling edge. The polarity control signal POL controls the vertical polarity of the data voltage output from the data driving circuit 300 . The source output enable signal SOE controls the output of the data driving circuit 300 . If digital video data and a mini LVDS clock are transmitted between the timing controller 200 and the data driving circuit 300 in the mini LVDS method, the first clock generated after the reset signal of the mini LVDS clock serves as a start pulse, so the source start pulse (SSP) may be omitted. The data timing control signal DCS for controlling the data driving circuit 300 includes a source start pulse (SSP), a source sampling clock (SSC), and a vertical polarity control signal (Polarity, POL). and a source output enable signal (Source Output Enable, SOE). The source start pulse SSP is a signal that controls the data sampling start timing of the data driving circuit 300 , and the source sampling clock SSC corresponds to a rising or falling edge in each IC constituting the data driving circuit 300 . A clock signal that controls the sampling timing of data. In addition, the vertical polarity control signal Polarity POL controls the vertical polarity inversion timing of the data voltage output from the data driving circuit 300 for each gate line G1 to Gn, and the source output enable signal SOE is It serves to control the output timing of the data driving circuit 300 .

The data driving circuit 300 latches RGBW DATA (or RGB DATA) input according to the control of the timing controller 200 . Then, the vertical polarity control signal (Polarity, POL) is converted into an analog positive or negative gamma compensation voltage (GAMMA) and simultaneously output to the display panel 100 through all data lines D1 to Dm.

Specifically, the data driving circuit 300 may set the polarity of the data voltage output from the data driving circuit 300 to a positive polarity when the vertical polarity control signal POL provided from the timing controller 200 is high logic. , when the logic is low, the polarity of the data voltage output from the data driving circuit 300 may be negative. In addition, the polarity may be inverted in units of vertical lines by the vertical polarity control signal POL.

<Power unit according to the embodiment>

2 is a block diagram illustrating a power supply unit according to an embodiment of the present invention. 3 is an operation timing diagram of the power supply unit. And Figure 4 is a circuit diagram showing the discharge circuit.

2 to 4 , the power supply unit 500 according to an embodiment of the present invention may include a DC converter 510 and a level shifter 520 . In addition, the DC converter 510 may include a discharge circuit 530 . In addition, the level shifter 520 may be provided separately from the power supply unit 500 and formed on a separate substrate.

The DC converter 510 outputs a first voltage V1 based on the input high-level power voltage Vcc, and a second voltage V2 based on the input power supply voltage Vcc of a preset voltage. can be printed out. In addition, the level shifter 520 outputs a gate high voltage Vgh based on the input first voltage V1 and higher than the gate high voltage Vgh based on the input second voltage V2. A high discharge voltage (DSC) can be output.

In addition, the gate driving circuit 400 outputs the gate high voltage Vgh to each of the plurality of gate lines G during the display-on period, and applies the discharge voltage to the plurality of gate lines G1 to Gn after the display is turned off. ), and the discharge voltage may be simultaneously output to all or a portion of the plurality of gate lines G1 to Gn to discharge the residual voltage of the display panel 100 .

Meanwhile, the power supply voltage Vcc may decrease from a high level to the preset voltage according to the power-off of the display.

As described above, as the level of the discharge voltage DSC, which is a voltage for turning on the thin film transistor T in the display panel 100, is increased during the discharge sequence, a voltage drop according to the resistance of the display panel 100 is compensated for. The discharge function can be improved.

Specifically, the DC converter 510 may boost or reduce the power voltage Vcc to generate panel driving voltages supplied to the display panel 10 . The panel driving voltages output from the DC converter 510 are a high potential supply voltage (Vdd), positive/negative gamma reference voltages (+VGMA, -VGMA), a common voltage (Vcom), a gate high voltage (Vgh), It may include a gate low voltage Vgl and a discharge voltage DSC.

The positive/negative gamma reference voltages (+VGMA, -VGMA) are voltages generated by dividing the high potential power voltage Vdd, and are referred to as a digital-to-analog converter of the data driving circuit 300 (hereinafter referred to as “DAC”). ) can be supplied. The gate high voltage Vgh is a high logic voltage of a gate pulse set above the threshold voltage of the TFT formed in the pixel array, and is supplied to the level shifter of the gate driving circuit 400 or the level shifter 530 provided in the power supply unit 500 , , the gate low voltage Vgl is a low logic voltage of the gate pulse set to the off voltage of the TFT formed in the pixel array, and is applied to the level shifter provided in the gate driving circuit 400 or the level shifter 520 provided to the power supply unit 800 . can be supplied.

The discharge circuit 530 may receive the power supply voltage Vcc and output any one of the first and second voltages V1 and V2. The first voltage V1 may become a gate high voltage Vgh through the level shifter 520 , and the second voltage V2 may become a discharge voltage DSC through the level shifter 520 .

The level shifter 520 may output a gate high voltage Vgh when receiving the first voltage V1 and output a discharge voltage DSC when receiving the first voltage V2, and the gate Any one of the high voltage Vgh and the discharge voltage DSC may be output. That is, the gate high voltage Vgh may be output during the display-on period, and the discharge voltage DSC may be output according to a discharge sequence after the display is turned off.

The discharge circuit 530 may include an amplifier 540 , a controller 550 , and a reference voltage generator 560 .

3 and 4 , the amplifier 540 may amplify an input power supply voltage Vcc to output an output voltage Vo, and the output voltage Vo may include a first voltage V1 and a second voltage voltage Vo. It may include two voltages (V2).

The controller 550 may control the amplifier 540 to adjust the amplification amount of the power supply voltage Vcc of the amplifier 540 . Specifically, the control unit 550 compares the input reference voltage Vref with the output voltage Vo of the amplifier 540 fed back, and when the power supply voltage Vcc is lower than the reference voltage Vref, the The amplification amount of the power supply voltage Vcc is increased, and when the power supply voltage Vcc is higher than the reference voltage Vref, the amplification amount of the power supply voltage Vcc is lowered to set the output voltage Vo of the amplifier 540 as the reference. It can be changed by the voltage (Vref).

As described above, by using the feedback control system of the amplifier 540 and the controller 550, the output voltage Vo of the amplifier 540 close to the reference voltage Vref can be generated. By setting differently depending on whether or not a discharge sequence exists, the amplifier 540 may generate a voltage for turning on the thin film transistor T in the display panel 100 suitable for each of the display period and the discharge sequence.

The reference voltage generator 560 may detect a change in the input power voltage Vcc and output a reference voltage Vref to the controller 550 . The reference voltage generator 560 may adjust and output the reference voltage Vref. That is, the reference voltage Vref may include first and second reference voltages Vref1 and Vref2, and the reference voltage generator 560 may select any one of the first and second reference voltages Vref1 and Vref2. You can print one.

The reference voltage generator 560 may detect a change in the input voltage Vcc to detect the display off, and accordingly output different reference voltages Vref, suitable for each display period and discharge sequence. A voltage for turning on the thin film transistor T in the display panel 100 may be generated.

Specifically, the liquid crystal display device 10 maintains a high potential of the power supply voltage Vcc during the display-on period, and the power supply voltage Vcc at a time point Toff when the liquid crystal display device 10 is turned off. ) falls to a low level potential.

The reference voltage generator 560 outputs a first reference voltage Vref1 when the power supply voltage Vcc having a high level potential is input, and the power supply voltage Vcc is lower than the high level potential. When the set voltage Vset is reached, the second reference voltage Vref2 may be output. In addition, the reference voltage generator 560 outputs a high level discharge control signal DC to the level shifter 520 when the power supply voltage Vcc having a high level potential is input, and the power supply voltage Vcc ) becomes the preset voltage Vset lower than the high-level potential, the low-level discharge control signal DC may be output to the level shifter 520 . The level shifter 520 may output a discharge signal DSC to an output terminal when the input discharge control signal DC becomes a low level.

In this case, the voltage value of the first reference voltage Vref1 may be the same as the voltage value of the first voltage V1 which is the output voltage of the amplifier 540 . The voltage value of the second reference voltage Vref2 may be the same as the voltage value of the second voltage V2 which is the output voltage of the amplifier 540 .

When the first reference voltage Vref1 is input from the reference voltage generator 560 , the control unit 550 controls the amplifier 540 to amplify the power supply voltage Vcc by controlling the amplifier 540 . The first voltage V1 having the same potential as the first reference voltage Vref1 may be output. In addition, when the control unit 550 receives the second reference voltage Vref2 from the reference voltage generator 560, it controls the amplifier 540 so that the amplifier 540 amplifies the power supply voltage Vcc. A second voltage V2 having the same potential as the second reference voltage Vref2 may be output.

The level shifter 520 may output a gate high voltage Vgh based on the first voltage V1 from the amplifier 540 and based on the second voltage V2 from the amplifier 540 . Thus, the discharge voltage DSC may be output.

In addition, the level shifter 520 outputs a gate high voltage Vgh to an output terminal during the display period Td, and a discharge voltage ( DSC) can be output. Also, in synchronization with the timing at which the level shifter 520 outputs the discharge voltage DSC, the gate driving circuit 400 outputs the discharge voltage DSC through all the gate lines G1 and Gn to the display panel ( A discharge sequence may be performed by turning on the thin film transistors T of all pixels of 100 ).

The thin film transistor T of the display panel 100 is turned on by the discharge sequence. Accordingly, the charge charged in the sub-pixel (storage capacitor, etc.) of the display panel 100 may be discharged through the common voltage line and the data line having an equipotential level corresponding to the ground voltage GND.

<Reference voltage generator according to the embodiment>

5 is a detailed circuit diagram of a reference voltage generator.

The reference voltage generator 560 outputs an output signal of a first level based on the power supply voltage Vcc of a high level, and outputs a second level output signal based on the power supply voltage Vcc of the preset voltage Vset. A preset voltage detector 560 that outputs an output signal of a level, a switch driver 562 that outputs switch driving signals of different logic levels according to the level of the output signal of the preset voltage detector 560, the switch driver The reference voltage setting unit 570 may include a reference voltage setting unit 570 for outputting one of the first and second reference voltages Vref1 and Vref2 that is controlled and set by the output signal of 562 .

In addition, the reference voltage setting unit 560, the first and second switch elements (S1, S2) controlled by the output signal from the switch driver 562, the control unit (S1) through the first switch element (S1) A first reference voltage setting unit 563 for outputting a first reference voltage Vref1 to 550 and a second reference voltage Vref2 for outputting a second reference voltage Vref2 to the control unit 550 through the second switch element S2 2 may include a reference voltage setting unit 565 .

Also, the first and second switch elements S1 and S2 may be N-type MOSFETs. In this case, the reference voltage setting unit 570 inverts the output signal from the switch driving unit 562 . Thus, an inverter 564 outputting to the gate terminal of the second switch element S2 may be further included. As described above, by forming the first and second switch elements S1 and S2 in the same type, it is possible to prevent a switching driving deviation due to a material difference of the switch element, thereby improving the accuracy of operation.

Also, the first switch element S1 may be an N-type MOSFET, and the second switch element S2 may be a P-type MOSFET. In this case, the output terminal of the switch driver 562 is the first and It may be directly connected to each of the second switch elements S1 and S2. Accordingly, it is not necessary to provide a separate inverter for inverting the output signal of the switch driver 562 , thereby reducing circuit complexity.

As an example, when the first and second switch elements S1 and S2 are N-type MOSFETs, the reference voltage generator 560 will be described with reference to FIG. 5 below.

The reference voltage generator 560 includes a preset voltage detection unit 561 , a switch driver 562 , a first reference voltage setting unit 563 , a second reference voltage setting unit 565 , an inverter 564 , and first and It may include a second switch element (S1, S2).

The preset voltage detection unit 561 may detect whether the input power voltage Vcc becomes the preset voltage Vset. The preset voltage detection unit 561 outputs a high level signal when the input power voltage Vcc is higher than the preset voltage Vset, and the input power voltage Vcc is the preset voltage Vset. From this point on, a low level signal can be output.

The switch driving unit 562 outputs a high level switch driving signal when a high level signal is input from the preset voltage detection unit 561 , and outputs a high level switch driving signal when a low level signal is input from the preset voltage detection unit 561 . , a low level switch driving signal may be output.

The first switch element S1 may be turned on by the high level output signal from the switch driving unit 562 to output the first reference voltage Vref1 output from the first reference voltage setting unit 563 . have.

The first switch element S1 may be turned off by a low-level output signal from the switch driver 562 .

The second switch element S2 is turned on by the high-level output signal of the inverter 564 as the low-level output signal from the switch driver 562 passes through the inverter 564, a second reference The second reference voltage Vref2 output from the voltage setting unit 565 may be output.

When the high level output signal from the switch driving unit 562 is output, the second switch element S2 is turned to a low level by the inverter 564 , and is thus turned on by the low level output signal of the inverter 564 . can be turned off

The output terminals of the first and second switch elements S1 and S2 may be connected to each other to be connected to the control unit 550 .

The first reference voltage setting unit 563 is configured to generate a first reference voltage Vref1 necessary to generate a first voltage V1 necessary to generate a gate high voltage Vgh that turns on the thin film transistor T of the display panel 1000 . ), and the voltage value of the first reference voltage Vref1 that is the output voltage of the first reference voltage setting unit 563 can be set.

The second reference voltage setting unit 565 is configured to generate a second reference voltage Vref2 necessary to generate a second voltage V2 necessary to generate a discharge signal DSC for turning on the thin film transistor T of the display panel 1000 . can be output, and the voltage value of the second reference voltage Vref2 that is the output voltage of the second reference voltage setting unit 565 can be set.

In addition, in order to generate a voltage required to turn on all the thin film transistors T of the display panel 1000 in a discharge sequence operation, the second reference voltage Vref2 has a higher voltage value than the first reference voltage Vref1. In addition, the second reference voltage Vref2 may be set in consideration of an increase in the number of gate lines due to an increase in resolution, an increase in the line resistance of the gate line, and an increase in the resistance of the gate line due to an increase in the size of the panel.

In addition, each of the first and second reference voltage setting units 563 and 565 is provided in each of the first and second reference voltage setting units 563 and 565 by a user according to I2C (I-square-C) communication. The reference voltage Vref suitable for the driving and discharging sequence of the display panel 100 may be set by using the lookup table on the memory.

As described above, by performing the discharge sequence when the display is turned off, it is possible to prevent stain defects due to the residual voltage of the display panel 100 . In addition, as the level of the discharge voltage DSC, which is a voltage for turning on the thin film transistor T in the display panel 100, is increased during the discharge sequence, the voltage drop according to the resistance of the display panel 100 is compensated for to discharge. function can be improved. In addition, according to the size of the display panel 100 , it is possible to set the second reference voltage Vref2 at an appropriate level suitable for the resistance of the display panel 100 , so that the discharge function can be improved.

In the detailed description of the present invention described above, although it has been described with reference to preferred embodiments of the present invention, those skilled in the art or those having ordinary skill in the art will It will be understood that various modifications and variations of the present invention can be made without departing from the spirit and scope of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10 Liquid crystal display
100 display panel
101 display area
102 non-display area
110 pixel electrode
120 common electrode
200 timing controller
300 data drive circuit
400 gate driving circuit
500 power supply
510 DC converter
520 level shifter
530 discharge circuit
540 Amplifier
550 control
560 reference voltage generator
561 preset voltage detection unit
562 switch drive
563 first reference voltage generator
564 inverter
565 second reference voltage generator

Claims (8)

A display panel comprising: a display panel including a plurality of sub-pixels defined in an intersection region of a plurality of gate lines and a plurality of data lines, and a plurality of thin film transistors disposed in each of the plurality of sub-pixels and controlled by the gate lines;
a DC converter for outputting a first voltage based on the input high-level power supply voltage and outputting a second voltage based on the input power supply voltage of a preset voltage;
a level shifter outputting a gate high voltage based on the input first voltage and outputting a discharge voltage higher than the gate high voltage based on the input second voltage;
a gate driving circuit for outputting the gate high voltage to each of the plurality of gate lines and outputting the discharge voltage to the plurality of gate lines; and
As the display power is turned off, the power supply voltage decreases from a high level to the preset voltage,
The DC converter includes a discharge circuit for outputting any one of the first and second voltages,
The discharging circuit includes an amplifier, a control unit, and a reference voltage generator,
The amplifier receives the power supply voltage and amplifies any one of the first and second voltages as an output voltage,
The reference voltage generator receives the power supply voltage, detects a change thereof, and outputs any one of the first and second reference voltages as a reference voltage,
The controller controls the output voltage of the amplifier as the reference voltage by feeding back the output voltage of the amplifier. The method of claim 1,
The reference voltage generator outputs a discharge control signal to the level shifter in synchronization with the power supply voltage of a preset voltage,
The level shifter outputs the discharge voltage based on the discharge control signal. The method of claim 1,
The reference voltage generator,
When the high-level power voltage is input, outputting a high-level discharge control signal,
A liquid crystal display for outputting a low-level discharge control signal when the power supply voltage of the preset voltage is input. delete The method of claim 1,
The reference voltage generator,
a preset voltage detector for outputting an output signal of a first level based on the power supply voltage of a high level and outputting an output signal of a second level based on the power supply voltage of the preset voltage;
a switch driving unit for outputting switch driving signals of different logic levels according to the level of the output signal of the preset voltage detecting unit; and
and a reference voltage setting unit configured to output one of the first and second reference voltages controlled by the output signal of the switch driver and set. 6. The method of claim 5,
The reference voltage setting unit,
first and second switch elements controlled by an output signal from the switch driver;
a first reference voltage setting unit for outputting a first reference voltage to the control unit through the first switch element; and
and a second reference voltage setting unit outputting a second reference voltage to the control unit through the second switch element. 7. The method of claim 6,
The first and second switch elements are N-type MOSFETs,
The reference voltage setting unit,
and an inverter for inverting the output signal from the switch driver and outputting the inverted signal to the gate terminal of the second switch element. 7. The method of claim 6,
The first switch element is an N-type MOSFET,
The second switch element is a P-type MOSFET.

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