KR102008133B1 - Display device and driving method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to gate lines formed in a second side portion having a long distance from the gate drive IC from gates formed in the first side portion having a short distance from the gate drive IC. To provide a display device and a driving method thereof, which can increase the magnitude of the gate high voltage VGH of a scan signal sequentially output to the gate lines. To this end, the display device according to the present invention includes a panel in which pixels are formed at regions where gate lines and data lines cross each other; A gate drive IC for sequentially supplying scan signals to the gate lines; A data drive IC for supplying a data voltage to the data lines; A timing controller for controlling driving of the gate drive IC and the data drive IC; And from the gate lines formed on the first side of the gate lines, which are shorter to the gate drive IC, to the gate lines formed on the second side of the gate line, which have a long distance from the gate drive IC. It includes a power supply for increasing the magnitude of the gate high voltage (VGH) of the scan signal.

Description

Display device and its driving method {DISPLAY DEVICE AND DRIVING METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device and a driving method thereof, and more particularly, to a display device using a chip-on film in which a gate drive IC and a data drive IC are integrally formed on one film, and a driving method thereof.

Flat panel displays (FPDs) are used in various types of electronic products, including mobile phones, tablet PCs, and notebook computers. The flat panel display includes a liquid crystal display (LCD), a plasma display panel (PDP), an organic electroluminescent display (OLED), and more recently, an electrophoretic display ( EPD: ELECTROPHORETIC DISPLAY) is also widely used.

1 is an exemplary view schematically showing a conventional display device, and FIG. 2 is an exemplary view showing a voltage drop of a scan signal generated in a conventional display device.

In a panel of a conventional flat panel display device (hereinafter, simply referred to as a 'display device'), gate lines and data lines are formed to cross each other. Thus, for example, when the data drive IC is in the upper non-display area, the gate connection lines for connecting the gate drive IC or the gate in panel GIP and the gate lines are disposed in the left and right non-display areas of the panel. Formed.

However, in order to prevent the width of the non-display area from being increased by the gate connection lines formed on the left and right sides of the panel, as shown in FIG. 1, a gate drive IC 20 and A display device having a form in which a plurality of chip-on-films 60 having a data drive IC 30 formed on one film 50 are connected to a non-display area above the panel 10 has been developed.

In such a display device, since the gate connection lines are not formed in the non-display areas formed on the left and right sides of the panel 10, that is, the bezel, the bezel may be formed to be narrowest to the minimum, and thus, narrow. Panels can be implemented.

That is, a chip on film 60 for driving a narrow panel may include one data drive IC 30, one gate drive IC 20, and the data drive IC 30. It consists of one film 50 in which the gate drive IC 20 is embedded.

In the conventional display device as described above, the gate connection lines 11a connected to the gate drive IC 20 and the data lines 12 connected to the data drive IC 30 do not overlap each other. To avoid this, as shown in the enlarged circle A of FIG. 1, at least one data line 12 is connected between two channels (gate connection line 11a) of the gate drive IC 20. .

In addition, the gate connection lines 11a and the data lines 12 are formed to be parallel to each other on the panel 10.

On the other hand, the gate lines 11 for inputting the scan signal to the pixels formed on each horizontal line of the panel 10, as in a conventional general display device, are arranged on the data line on the panel 10. 12) is formed in the form perpendicular to the cross.

Accordingly, each of the gate connection lines 11a for transmitting the scan signal output from the gate drive IC 20 to each of the gate lines 11b is perpendicular to each of the gate lines 11b. In the panel 10. In addition, each of the gate connection lines 11a is connected to each of the gate lines 11b.

That is, one gate connection line 11a is connected to one gate line 11b. Accordingly, one scan signal output from the gate drive IC 20 may be supplied to one gate line 11b through the one gate connection line 11a.

In this case, as shown in the enlarged quadrangle of FIG. 1, one pixel 13 is formed in each region where the gate connection line 11a intersects the data line 12 and the gate line 11b. Is formed.

The conventional display device as described above has the following problems.

As described above, the scan signal output from the gate drive IC 20 is formed in parallel with the horizontal line of the panel through the gate connection line 11a formed in parallel with the data line 12. In the display device transmitted to the gate line 11b, the transmission of the scan signal may be delayed, which may cause the panel to malfunction.

That is, due to the extra-large size of the panel 10 (more than 60 inches, 100 inches) and the narrowing of the bezel, the width and the spacing of the wirings inside the panel are narrowed, thereby increasing the resistance and parasitic capacitance. In particular, in the display device as shown in FIG. 1, since the gate connection line 11a formed in parallel with the data line 12 is added, the scan signal is enlarged in the rectangle B of FIG. 1. As indicated by arrows in FIG. 2, the gate connection line 11a is transmitted to the gate line 11b through the gate connection line 11a.

Therefore, the resistance and parasitic capacitance caused by the internal wirings are increased, which may delay the transmission of the scan signal and may cause a malfunction of the panel.

In particular, for the above reasons, in the display device as shown in FIG. 1, the panel 10 is far from the upper end of the panel 10 to which the chip-on film 60 is connected. In the gate line 11b formed at the lower portion of the gate, an image distortion phenomenon may occur due to a voltage drop and a delay of a scan signal.

That is, as shown in Figure 2, the waveform (x) of the scan signal output from the gate drive IC 20 and output to the gate line 11b formed on the upper portion of the panel 10, and When comparing the waveform y of the scan signal output to the gate line formed at the bottom of the panel 10, the waveform of the scan signal output to the gate line formed at the bottom of the panel 10 ( In y), a voltage drop phenomenon occurs.

Such a voltage drop phenomenon causes a reduction in the charging ratio in the pixel, which causes various problems such as flicker.

In addition to the display device as shown in FIG. 2, the voltage drop as described above may occur in a display device configured such that a length difference occurs between the gate drive IC and the gate connection lines connecting the gate lines. Can be.

That is, in a display device in which gate lines are connected to gate connection lines having different distances from the gate drive IC, regardless of the arrangement of the gate connection line and the gate line, the gate connection having a long distance from the gate drive IC is performed. In the gate line connected to the line, the voltage drop as described above may occur.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned problem, and is formed in the second side portion having a long distance from the gate drive IC from the gate lattice formed in the first side portion having a short distance from the gate drive IC. An object of the present invention is to provide a display device and a driving method thereof, which can increase the magnitude of the gate high voltage VGH of a scan signal sequentially output to the gate lines.

According to an aspect of the present invention, there is provided a display device including: a panel in which pixels are formed in regions where gate lines and data lines cross each other; A gate drive IC for sequentially supplying scan signals to the gate lines; A data drive IC for supplying a data voltage to the data lines; A timing controller for controlling driving of the gate drive IC and the data drive IC; And from the gate lines formed on the first side of the gate lines, which are shorter to the gate drive IC, to the gate lines formed on the second side of the gate line, which have a long distance from the gate drive IC. It includes a power supply for increasing the magnitude of the gate high voltage (VGH) of the scan signal.

According to an aspect of the present invention, there is provided a method of driving a display device, the method including receiving a power control signal; Generating a switching voltage using the power control signal; And a gate drive IC outputting the gate high voltage of the scan signal output to the gate lines formed in the panel for one frame period according to the switching voltage and the gate high voltage to the gate line. And changing the output according to the distance from the line.

According to the present invention, the voltage drop phenomenon in the gate lines formed in the second side portion, which is far from the first side portion, to which the gate drive IC and the chip-on film incorporating the data drive IC are connected, is prevented, Image quality defects can be improved.

1 is a schematic view showing a conventional display device.
2 is a diagram illustrating a voltage drop of a scan signal generated in a conventional display device.
3 is an exemplary view schematically showing a display device according to the present invention.
4 is a diagram illustrating an internal configuration of a power supply unit applied to a display device according to the present invention.
FIG. 5 is a waveform diagram of signals output from the PWM unit shown in FIG. 4. FIG.
6 is an exemplary view showing a configuration of a PWM unit shown in FIG. 4.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

Hereinafter, for convenience of description, the liquid crystal display device will be described as an example of the present invention, but the present invention is not limited thereto. That is, the present invention can be applied to various display devices that can display an image by supplying a scan signal to a gate line.

In addition, hereinafter, for convenience of description, a display device in which a chip on film including a data drive IC, a gate drive IC, and a film on which the data drive IC and the gate drive IC are mounted is connected to a panel is an example of the present invention. It is explained. However, the present invention is not limited thereto. That is, the present invention can be applied to various types of display devices configured to have a length difference between the gate drive IC and the gate connection lines connecting the gate lines.

3 is an exemplary view schematically showing a display device according to the present invention, FIG. 4 is an internal configuration diagram of a power supply unit applied to the display device according to the present invention, and FIG. 5 is a PWM unit shown in FIG. 4. Figure 6 is a waveform diagram of the signals output from the, Figure 6 is an exemplary view showing the configuration of the PWM unit shown in FIG.

In the display device according to the present invention, as illustrated in FIG. 3, a panel 100 in which pixels are formed in each region where gate lines GL1 to GLn and data lines DL1 to DLm intersect, and the gate A gate drive IC 200 for sequentially supplying scan signals to lines, a data drive IC 300 for supplying a data voltage to the data lines, the gate drive IC 200 and the data drive IC 300 From the timing controller 400 and the gate lines GL1 to GLn to control the driving of the gate lines formed on the first side portion 160 having a short distance from the gate drive IC 200. The power supply unit 700 may increase the magnitude of the gate high voltage VGH of the scan signal toward the gate lines formed on the second side 160 having a long distance from the gate drive IC 200. ).

First, the data drive IC 300 converts the digital image data transmitted from the timing controller 400 into an analog data voltage and transmits the converted digital image data to a data line DL formed on the panel 100.

That is, the data drive IC 300 converts the image data into the data voltage using the gamma voltages supplied from a gamma voltage generator (not shown), and outputs the image data to the data line.

To this end, the data drive IC 300 includes a shift register unit, a latch unit, a digital analog converter (DAC), and an output buffer.

The data drive IC 300 may receive the image data from the timing controller 400 using an EPI interface. However, the data drive IC 300 may receive the image data from the timing controller 400 using a mini-LVDS scheme. Image data may also be received.

The shift register unit generates a sampling signal using data control signals SSC, SSP, etc. received from the timing controller 400.

The latch unit latches the digital image data Data sequentially received from the timing controller 400, and simultaneously outputs the digital image data to the digital analog converter DAC.

The digital-to-analog converter converts the image data transmitted from the latch unit into a positive or negative data voltage at the same time and outputs the data voltage. That is, the digital analog converter converts the image data into a positive or negative data voltage (data signal) using the polarity control signal POL transmitted from the timing controller 400 and outputs the data voltages to the data lines. do.

The digital-analog converter converts the image data into the data voltage using the driving voltage VDD supplied from the power supply 700.

The output buffer outputs the positive or negative data voltage transmitted from the digital analog converter to the data lines of the panel according to the source output enable signal SOE transmitted from the timing controller 400. do.

The output buffer amplifies the data voltage transmitted from the digital-to-analog converter by using the driving voltage VDD supplied from the power supply unit 700 and outputs the data voltage to the data lines formed on the panel.

Next, the gate drive IC 200 generates a scan signal according to the gate control signal transmitted from the timing controller 400, and generates a gate signal through the gate connection line 110a formed in the panel. GL).

The gate drive IC 200 and the data drive IC 300 may be separately formed on a panel or a flexible film and connected to the gate lines and the data lines. However, as illustrated in FIG. It may be mounted on the film 600.

That is, the chip-on film 600 connected to the first side portion 160 of the panel 100 may include the data drive IC 300, the gate drive IC 200, and the data drive IC 300. And a film 500 formed of a flexible material on which the gate drive IC 200 is mounted.

Here, the first side part 160 refers to an area where a distance from the gate drive IC 200 is short among the areas where the gate lines are formed, and the second side part 170 refers to the first side part. In comparison with the above, it refers to an area having a long distance from the gate drive IC 200.

More specifically, a region where the length of the gate connection line 110a that connects the gate drive IC 200 and the gate line, rather than the distance to the gate drive IC 200 is relatively long, may be formed. It becomes the two side part 170.

That is, the length of the gate connection line 110a connected to the gate line formed in the region far from the gate drive IC 200 is formed in the region close to the gate drive IC 200. It is longer than the length of the gate connection line 110a connected to the gate line. Thus, the two expressions described above may be interpreted in the same sense.

As described above, in the following description, the present invention will be described as an example of a display device in which the data drive IC 300 and the gate drive IC 200 are formed in the chip-on-film 600. The present invention can also be applied to a display device in which the data drive IC 300 and the gate drive IC 200 are formed in different positions at different positions.

That is, the gate drive IC 200 may be connected to the panel 100 in a state in which the gate drive IC 200 is separated from the data drive IC 300 and mounted on a separate film, and is mounted in the panel. Gate In Panel (GIP) can also be configured.

Meanwhile, when the gate drive IC 200 and the data drive IC 300 are formed on the chip-on film 600 as shown in FIG. 3, the gate drive IC 200 and the data drive IC 300 extend from the data drive IC 300. At least one source line 310 of the source lines may be connected to the data line DL through a channel (port or gate connection line) of the gate drive IC 200.

The number of the gate drive IC 200 and the data drive IC 300 and the number of the chip on film 600 may be variously set according to the size and resolution of the panel.

Next, the panel 100 includes a thin film transistor TFT formed at each region defined by the intersection of the gate lines GL1 to GLn and the data lines DL1 to DLm, and pixels including a pixel electrode. do.

The thin film transistor TFT supplies a data voltage (image signal) supplied from the data line 120 to the pixel electrode in response to a scan signal supplied from the gate line 110a. The pixel electrode adjusts light transmittance by driving a liquid crystal positioned between the common electrode and the common electrode in response to the data voltage.

As for the liquid crystal mode of the panel applied to this invention, not only TN mode, VA mode, IPS mode, FFS mode but any kind of liquid crystal mode is possible. In addition, the liquid crystal display according to the present invention may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display.

In addition to the liquid crystal panel as described above, the panel 100 may include various types and types of panels configured to output an image according to a scan signal supplied to the gate line 110b.

Meanwhile, when the data drive IC 300 and the gate drive IC 200 are configured as one chip-on-film 600 as described above, the gate line 110b and the data line 120 are formed on the panel. In addition, the gate connection line 110a may be further formed to connect the gate drive IC 200 and the gate line 110b.

In this case, in the panel 100, data lines 120 connected to the data drive IC 300 and the gate drive IC 200 are arranged in parallel with the data lines 120b. Gate connection lines 110a and gate lines 110b disposed perpendicular to the gate connection lines 110a and the data lines 120 and connected to the gate connection lines 110a. It is.

Thus, as shown in FIG. 3, one data line 120 formed in parallel with one gate connection line 110a and the gate connection line 110a, and the gate connection line 110a and the One pixel P is formed at each crossing area of one gate line 110b perpendicular to the data line 120.

Next, the timing controller 400 aligns input image data (Input RGB) input from an external system according to the structure and characteristics of the panel and transmits the aligned image data to the data drive IC 300. .

In addition, the timing controller 400 uses the timing signals transmitted from the external system, that is, the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the data enable signal DE. A data control signal DCS for controlling the IC 300 and a gate control signal GCS for controlling the gate drive IC 200 are generated to transfer the control signals to the data drive IC and the gate drive IC. Perform the function of sending.

The gate control signals GCS generated by the timing controller 400 may vary according to the type of the gate drive IC. For example, the gate drive IC 200 is formed on the chip-on-film (COF) 600 as described above or separated from the data drive IC 300 to form a separate tape carrier package (TCP) panel. When connected to the gate controller, the gate control signals generated by the timing controller 400 include a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, and the like. In addition, in the case of a gate in panel (GIP) type in which the gate drive IC 200 is mounted on the panel, the gate control signals generated by the timing controller 400 may include a gate start signal VST and a gate clock GCLK. Etc.

The data control signals generated by the timing controller 400 include a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, a polarity control signal POL, and the like. However, these data control signals may be changed in various forms depending on whether the interface method used between the timing controller and the data drive IC is a TTL method, a mini LVDS method, or an EPI method. The timing controller 400 is mounted on the main board 800, and the main board 800 is connected to the panel 100 through the chip-on film 600.

Finally, the power supply 700 is required by the timing controller 400, the gate drive IC 200, and the data drive IC 300 by using an input voltage VIN input from the external system. Generate power.

The power supply unit 700 may include the gate drive IC from the gate lines formed at the first side portion 160 of the gate lines GL1 to GLn, which have a short distance from the gate drive IC 200. The gate line voltage VGH of the scan signal increases as the gate lines formed on the second side portion 170, which have a long distance from the reference point 200, increase.

Here, the scan signal is output to the gate line 110b to turn on or off the thin film transistor TFT formed in each pixel.

The scan signal is a high level gate high output to the gate line 110b during one horizontal period when a data voltage corresponding to one horizontal line is output from the data drive IC 300 to the data line DL. And a low level gate low voltage VGL output to the gate line for the remaining one frame period after the voltage VGH and the data voltage are output.

That is, when the scan signal having the gate high voltage VGH is output to the gate line, the thin film transistor connected to the gate line is turned on so that the data voltage is supplied to the pixels on which the thin film transistor is formed. As a result, an image is output to the panel.

In addition, the scan signal having the gate low voltage VGL is output to the gate line before the data voltage is supplied to the data line and after the data voltage is supplied to the data line during one frame period. .

Particularly, the power supply unit 700 gradually moves from the gate lines formed on the first side portion 160 to the gate lines formed on the second side portion 170 during the one frame period. The gate high voltage VGH may be increased for each gate line.

That is, the length of the gate connection line 110a becomes longer from the first side portion 160 to the second side portion 170. Therefore, as the voltage goes from the first side portion 160 to the second side portion 170, the voltage drop phenomenon described with reference to FIG. 2 is seriously generated.

In order to overcome this problem, the present invention, the gate high from the gate lines formed on the first side portion 160 to the gate lines formed on the second side portion 170, the gate high for each gate line. The magnitude of the voltage VGH is increasing, and this function is executed in the power supply 700.

The gate high voltage VGH is changed in one frame period because the gate line to which the gate high voltage VGH is output is repeated every frame.

The power supply unit 700 may include the second power supply unit 700 from the first gate line group formed on the first side unit 160 among the gate line groups formed of at least two gate lines during one frame period. As the k-th gate line group is formed on the side portion 170, the gate high voltage VGH may be increased for each gate line group. Here, the first gate line group is formed in the region closest to the gate drive IC 200, and the k-th gate line group is formed in the region furthest from the gate drive IC 200.

That is, the gate high of the power supply unit 700 and the gate lines formed in the second side unit 170 from the gate lines formed in the first side unit 160 during one frame period. When the voltage VGH is output, the gate high voltage VGH may be sequentially increased for each of the gate lines and output. The at least two gate lines may be grouped into a gate line group, and the gate line group may be configured. The gate high voltage VGH may be increased.

The power supply unit 700 uses any one of a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, or a gate control signal or data control signals generated by the timing controller, input from the external system. The magnitude of the gate high voltage may be changed every one frame period.

That is, the gate high voltage VGH is increased from gate lines formed in the first side portion 160 to gate lines formed in the second side portion 170 during one frame period. When the one frame period ends, the gate high voltage VGH is changed to the smallest magnitude, and when another one frame period begins, again, from the gate lines formed in the first side portion 160, As the gate lines are formed on the second side 170, the power supply 700 changes the magnitude of the gate high voltage every one frame period by using signals that can distinguish each frame. You can.

For example, the vertical synchronous signal Vsync has a cycle repeated every one frame, and the power supply unit 700 uses the vertical synchronous signal as a power control signal PCS. VGH) can be changed in size.

In addition, the horizontal synchronization signal (Hsync) defines a period during which the data voltage is output, the one frame period may be defined by the number of the horizontal synchronization signal (Hsync). Accordingly, the power supply unit 700 may count the horizontal synchronization signal Hsync to define the one frame period, and then change the magnitude of the gate high voltage VGH during the one frame period.

In addition, the power supply unit 400 may define one frame period using various control signals as described above, and then change the magnitude of the gate high voltage VGH during the one frame period.

Here, the various control signals for defining the one frame period are collectively referred to as a power control signal PCS.

In order to perform the function as described above, the power supply unit 400 uses the input voltage and the power control signal PCS input from an external system, as shown in FIG. 4, every one frame period. A pulse width modulation (PWM) unit 710 for outputting a switching voltage (SV) for sequentially changing the magnitude of the gate high voltage, and generates the gate high voltage according to the switching voltage (SV) to the gate drive IC. A gate high voltage generator 730 for outputting the gate low voltage generator 730 for generating and outputting a gate low voltage VGL of the scan signal using the output voltage output from the PWM unit 710; And a driving voltage generator 740 for generating and outputting a driving voltage VDD to be supplied to the data drive IC 300 using the output voltage output from the PWM unit 710.

The PWM unit 710 generates a plurality of output voltages by boosting or bucking the input voltage VIN according to a pulse width of a switching signal generated therein.

In particular, the PWM unit 710 generates a switching voltage SV that can sequentially change the magnitude of the gate high voltage every frame period by using an input voltage and a power control signal PCS. That is, according to the magnitude of the switching voltage SV, the gate high voltage generator 720 generates a gay high voltage VGH having different magnitudes.

The PWM unit 710 is a PWM integrated circuit (PWM-IC) having output pins such as a drive for negative charge pump (DRN), a feedback for negative charge pump (FBN), and a reference (REF). Can be configured.

As shown in FIGS. 5A and 6, the PWM unit 710 includes a reference swing block for generating a rectangular wave of a predetermined frequency and a mux in the reference swing block. And a ramp block for outputting the triangular wave as shown in FIG. 5B using the square wave generated using the MUX) as the switching voltage SV.

The reference swing block (Ref Swing Block) generates a Vref swing signal (square wave) as shown in (a) of FIG. 5 by using the mux MUX as two channels Ch.

The ramp block is turned on for a high time (ON) of the Vre Swing signal (square wave) as shown in FIG. 5A, and is shown in FIG. 5B. As such, it is gradually charged in the period C2. In addition, the ramp block is turned off during the Low Time (OFF) of the Vre Swing signal (square wave), and outputs a Gradual Vref (eg, 1.1V DC) as a final output.

The PWM unit 710 configured as described above generates a square wave as shown in FIG. 5A by using the input voltage and the power control signal PCS, and the pulse width of the square wave. The triangular wave is changed in size by the change of the light source, and the PWM unit 710 outputs the triangular wave as the switching voltage SV to the gate high voltage generator 720. In detail, the triangular wave is input to the gate high voltage generator 720 to vary the magnitude of the gate high voltage VGH.

That is, a square wave as shown in FIG. 5B is generated through a mux (analog switch) of the reference swing block, and the triangular wave (or sawtooth wave) is generated through the ramp block. The sawtooth wave is input to the gate high voltage generator 720 as the switching voltage SV to vary the magnitude of the gate high voltage.

The power control signal PCS may be a vertical synchronization signal Vsync as described above. For example, the vertical synchronization signal may be a control signal of a mux of the reference swing block, and the pulse (square wave) described above may be generated by the vertical synchronization signal. As shown in FIG. 6, the level of the square wave may be determined as Vref (+) and Vref (−).

In detail, the PWM unit 710 repeats the process of changing the magnitude of the gate high voltage VGH every frame by the power control signal PCS.

In addition, the PWM unit 710 may generate a periodic signal for changing the magnitude of the gate high voltage VGH by using the power control signal PCS. For example, as described above, when the magnitude of each gate high voltage to be output to one gate line is increased, a periodic signal corresponding to a period at which the gate high voltage is output is generated, and two or more gate lines are generated. When the gate high voltage of each gate group is increased, a period signal corresponding to the output period of the gate group is generated.

The PWM unit 710 varies the magnitude of the switching voltage for each periodic signal. In this case, the PWM unit 710 may vary the magnitude of the switching voltage using the switching information stored in the PWM unit 710 or an external memory. That is, the PWM unit 710 may vary the magnitude of the switching voltage by varying the pulse width or the magnitude of the square wave to a preset value according to the periodic signal and varying the magnitude of the triangle wave.

The gate high voltage generation unit 720 may be configured to, from the gate lines formed on the first side unit 160 during one frame period, by using the switching voltage generated by the PWM unit 710. The gate high voltage VGH output to the gate lines formed on the second side 170 is increased. That is, the gate high voltage generator 720 outputs the gate high voltage VGH by varying the size of the gate high voltage VGH according to the size of the switching voltage.

The gate low voltage generation unit 730 uses the output voltage and the charge pump generated by the PWM unit 710 to output gate low voltages to the gate lines to which the gate high voltage VGH is not output. Generate and print (VGL).

The driving voltage generator 740 generates a driving voltage VDD using the output voltage and the charge pump, and outputs the driving voltage VDD to the data drive IC 300. The driving voltage VDD is used as the gamma reference voltage in the data drive IC 300.

The driving method of the display device as described above is briefly described as follows.

First, the power supply unit 700 receives the power control signal PCS.

Next, the power supply unit 700 generates the switching voltage using the power control signal.

Lastly, according to the switching voltage, the power supply unit 700 converts the gate high voltage VGH of the scan signal output to the gate lines formed in the panel into the gate line for one frame period. The gate drive IC 200 for outputting the gate high voltage is changed according to the distance between the gate line and output.

At this time, the power supply unit 700 has a short distance from the gate drive IC 200 from gate lines formed on the first side of the power supply unit 700 having a short distance from the gate drive IC 200 connected to the panel. As the gate lines formed in the second side portion are longer, the gate high voltage VGH is increased and output.

The power supply unit 700, from the gate lines formed on the first side unit 160 to the gate lines formed on the second side unit 170, during the one frame period, is formed in the gate line. Each of the gate high voltages VGH may be increased, or from a first gate line group formed on the first side of the gate line groups formed of at least two gate lines. As the k-th gate line group is formed on the second side, the magnitude of the gate high voltage VGH may be increased for each gate line group.

Those skilled in the art to which the present invention pertains will understand that the present invention can be implemented in other specific forms without changing the technical spirit or essential features. Therefore, it is to be understood that the embodiments described above are exemplary in all respects and not restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention. do.

100: panel 500: film
300: data drive IC 200: gate drive IC
600: chip on film 400: timing controller
700: power supply 800: main board

Claims (11)

A panel in which pixels are formed at regions where the gate lines and the data lines cross each other;
A gate drive IC for sequentially supplying scan signals to the gate lines;
A data drive IC for supplying a data voltage to the data lines;
A timing controller for controlling driving of the gate drive IC and the data drive IC; And
From the gate lines formed on the first side of the gate lines, which are shorter to the gate drive IC, from the gate lines formed on the second side of the gate line, which are longer to the gate drive IC, And a power supply unit capable of increasing the magnitude of the gate high voltage VGH of the scan signal. The method of claim 1,
The power supply unit,
During the one frame period, the gate high voltage VGH is increased for each of the gate lines from the gate lines formed on the first side to the gate lines formed on the second side. Display device. The method of claim 1,
The power supply unit,
From the first gate line group formed on the first side to the kth gate line group formed on the second side, among the gate line groups formed of at least two gate lines during one frame period. Increasingly, the magnitude of the gate high voltage (VGH) for each gate line group increases. The method of claim 1,
The power supply unit,
By using any one of a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, or a gate control signal or data control signal generated by the timing controller, the gate high voltage may be generated every frame period. A display device characterized in that the size is changed. The method of claim 1,
The power supply unit,
A PWM unit outputting a switching voltage capable of sequentially changing the magnitude of the gate high voltage every frame period by using an input voltage and a power control signal input from an external system; And
And a gate high voltage generator configured to generate the gate high voltage according to the switching voltage and output the gate high voltage to the gate drive IC. The method of claim 1,
And the chip-on film connected to the first side of the panel includes a film on which the data drive IC, the gate drive IC, and the data drive IC and the gate drive IC are mounted. The method of claim 6,
The panel includes data lines connected to the data drive IC, gate connection lines connected to the gate drive IC and disposed in parallel with the data lines, and perpendicular to the gate connection line and the data lines. And gate lines connected to the gate connection line. Receiving a power control signal;
Generating a switching voltage using the power control signal; And
A gate drive IC and a gate line outputting the gate high voltage of the scan signal output to the gate lines formed in the panel for one frame period according to the switching voltage. And driving the display device according to the distance from the display device. The method of claim 8,
The step of outputting by changing the magnitude of the gate high voltage,
From the gate lines formed in the first side portion having a short distance to the gate drive IC connected to the panel, from the gate lines formed in the second side portion having a long distance from the gate drive IC, A method of driving a display device, characterized in that for increasing the output of the gate high voltage (VGH). The method of claim 9,
Among the gate line groups formed of at least two gate lines, the gate line is gradually moved from the first gate line group formed in the first side portion to the k-th gate line group formed in the second side portion. And increasing the size of the gate high voltage (VGH) for each group. A panel in which pixels are formed at regions where the gate lines and the data lines cross each other;
A gate drive IC for sequentially supplying scan signals to the gate lines;
A data drive IC for supplying a data voltage to the data lines;
A timing controller for controlling driving of the gate drive IC and the data drive IC; And
From the gate lines formed on the first side of the gate lines, which are shorter to the gate drive IC, from the gate lines formed on the second side of the gate line, which are longer to the gate drive IC, It includes a power supply for increasing the magnitude of the gate high voltage (VGH) of the scan signal,
The power supply unit may generate a square wave having a period of one frame period by using an input voltage and a power control signal input from an external system, and generate a ramp wave rising during a high time of the square wave to adjust the magnitude of the gate high voltage. And a PWM unit for outputting a switching voltage to be sequentially changed.

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