KR101696462B1 - Apparatus and method for modulating gate pulse, and display device using the same - Google Patents

Abstract

The present invention relates to a gate pulse modulation apparatus. The gate pulse modulator includes an option signal generator for generating an option signal of the first logic voltage in the forward shift mode and an option signal for generating the option signal to the second logic voltage in the reverse shift mode, A second detecting section for detecting an overlapping section of the n-2 th to the n < th > gate shift clocks, and a second detecting section for detecting an overlapping section of the clocks, A control unit for controlling the modulation timing of the gate shift clock in response to the output of the FLK signal and the selection unit; And a modulation driver for down-modulating the gate high voltage of the gate shift clocks in response to the output of the control section.

Description

TECHNICAL FIELD [0001] The present invention relates to a gate pulse modulation apparatus and method, and a display apparatus using the gate pulse modulation apparatus and method.

The present invention relates to a gate pulse modulation apparatus and method, and a display apparatus using the same.

BACKGROUND ART [0002] Liquid crystal display devices are becoming increasingly widespread due to features such as light weight, thinness, and low power consumption driving. The liquid crystal display device is used as a portable computer such as a notebook PC, an office automation device, an audio / video device, and an indoor / outdoor advertisement display device. A liquid crystal display controls an electric field applied to liquid crystal cells to modulate light incident from a backlight unit to display an image.

The active matrix type liquid crystal display device includes a liquid crystal display panel including a TFT (Thin Film Transistor) formed for each pixel and switching a data voltage supplied to the pixel electrode, a data driving circuit for supplying a data voltage to the data lines of the liquid crystal display panel A gate driving circuit for sequentially supplying gate pulses (or scan pulses) to the gate lines of the liquid crystal display panel, and a timing controller for controlling the operation timing of the driving circuits.

In an active matrix type liquid crystal display device, the voltage charged in the liquid crystal cell is affected by a kickback voltage (or a feed through voltage, DELTA Vp) generated due to the parasitic capacitance of the TFT. The kickback voltage (Vp) is expressed by Equation (1).

Here, 'Cgd' is the parasitic capacitance formed between the gate terminal of the TFT connected to the gate line and the drain terminal of the TFT connected to the pixel electrode of the liquid crystal cell, and 'VGH-VGL' And the difference voltage between the gate high voltage and the gate low voltage.

The voltage applied to the pixel electrode of the liquid crystal cell varies due to the kickback voltage Vp, and flicker, afterimage, color deviation, and the like can be seen in the display image. In order to reduce the kickback voltage Vp, a gate pulse modulation method (GPM) for modulating the gate high voltage VGH at the polling edge of the gate pulse is applied.

1 is a waveform diagram showing an example in which a gate shift clock (GCLK) is modulated in synchronization with a gate pulse modulation control signal (hereinafter referred to as "FLK signal") in a forward shift mode. The timing controller generates a FLK signal for controlling the timing of modulation of the gate pulse, together with a gate shift clock for shifting a gate start pulse (GSP). In general, the gate shift clocks are generated with clocks of two or more phases sequentially delayed, and the FLK signals are synchronized with each gate shift clock.

2 is a waveform diagram showing an example in which gate shift clocks are modulated in synchronization with an FLK signal in a backward shift mode. 3 is a simulation image showing an example in which, in the reverse shift mode, the gate shift clock is modulated at an abnormal time. In FIG. 1 and FIG. 2, 'GPM' indicates the modulation timing of the gate shift clock.

Referring to FIG. 2 and FIG. 3, in the reverse shift mode, the gate high voltage (VGH) is maintained not at the polling edge of the gate shift clock, that is, at the timing of inappropriate modulation, VGH) can be modulated. This results in not only an increase in current consumption but also a reduction in the data voltage charging rate of the liquid crystal display panel. Therefore, even if gate pulse modulation is performed in the backward shift mode, the problem of color saturation arises. In addition, if gate pulse modulation is not performed in the backward shift mode due to such a problem, problems such as afterimage and flicker may occur.

The present invention provides a gate pulse modulation apparatus and method capable of modulating a gate shift clock at an optimal modulation timing in each of a forward shift mode and a backward shift mode, and a display using the same.

The gate pulse modulation apparatus of the present invention includes gate shift clocks for shifting gate pulses to be sequentially supplied to gate lines of a display panel and control signal generation for generating an FLK signal for controlling the modulation timing of the gate shift clocks part; An option signal generator for generating an option signal of the first logic voltage in the forward shift mode and generating an option signal to the second logic voltage in the reverse shift mode; A first detecting unit for detecting an overlapping period of the nth (n is a positive integer of 3 or more) to (n + 2) th gate shift clocks; A second detector for detecting an overlap period of the (n-2) th to (n) th gate shift clocks; A selection unit for generating an inversion option signal by inverting the option signal and selecting either the output of the first detection unit or the output of the second detection unit in response to the option signal and the inversion option signal; A control unit for controlling the modulation timing of the gate shift clock in response to the FLK signal and the output of the selection unit; And a modulation driver for down-modulating a gate high voltage of the gate shift clocks in response to an output of the control unit.

The gate pulse modulation method of the present invention includes the steps of generating gate shift clocks for shifting gate pulses to be sequentially supplied to gate lines of a display panel and an FLK signal for controlling modulation timing of the gate shift clocks; Generating an option signal of a first logic voltage in a forward shift mode and an option signal in a reverse shift mode to a second logic voltage; Detecting an overlapping section of the nth (n is a positive integer of 3 or more) to (n + 2) th gate shift clocks using the first detecting section; Detecting an overlapping section of the (n-2) th to (n) th gate shift clocks using the second detecting section; Generating an inversion option signal by inverting the option signal and selecting either the output of the first detection unit or the output of the second detection unit in response to the option signal and the inversion option signal; Controlling the modulation timing of the gate shift clock in response to the output of the detection unit selected from the first and second detection units and the FLK signal; And down modulating the gate high voltage of the gate shift clocks at the modulation timing of the gate shift clock. The gate shift clock is sequentially delayed from the (n + 2) -th gate shift clock to the (n + 2) -th gate shift clock in the forward shift mode, while the gate shift clock is sequentially delayed from the And the gate shift clock is sequentially delayed in the order of the (n-2) th gate shift clock.

A display device of the present invention includes: a display panel in which gate lines and data lines cross; A control signal generator for generating gate shift clocks for shifting gate pulses to be sequentially supplied to the gate lines and an FLK signal for controlling the modulation timing of the gate shift clocks; An option signal generator for generating an option signal of the first logic voltage in the forward shift mode and generating an option signal to the second logic voltage in the reverse shift mode; A first detecting unit for detecting an overlapping period of the nth (n is a positive integer of 3 or more) to (n + 2) th gate shift clocks; A second detector for detecting an overlap period of the (n-2) th to (n) th gate shift clocks; A selection unit for selecting the output of the first detection unit and the output of the second detection unit in response to the option signal and the inverted option signal by inverting the option signal to generate an inverted option signal, And a modulation driver for down-modulating a gate high voltage of the gate shift clocks in response to an output of the control unit, so that the gate shift clocks are input A gate driver for receiving the gate pulses; And a data driver for supplying data voltages to the data lines in synchronization with the gate pulses.

The present invention can select a forward shift mode and a reverse shift mode using the option signal generator and modulate a gate shift clock at a desired modulation timing in each of a forward shift mode and a reverse shift mode. As a result, it is possible to modulate the gate shift clock in the backward shift mode and to solve problems such as crushing of color, afterimage, and flicker.

1 is a waveform diagram showing an example where 6-phase gate shift clocks are modulated in synchronism with an FLK signal in forward shift mode.
FIG. 2 is a waveform diagram showing an example in which six-phase gate shift clocks are modulated in synchronism with the FLK signal in the backward shift mode.
3 is a simulation image showing an example in which, in the reverse shift mode, the gate shift clock is modulated at an abnormal time.
FIG. 4 is a waveform diagram showing an example in which six-phase gate shift clocks are modulated in synchronism with the FLK signal in the reverse shift mode of the present invention.
5 is a simulation image showing an example in which, in the reverse shift mode, the gate shift clock is modulated at a normal time.
6 is a block diagram showing a gate pulse modulation apparatus according to the first embodiment of the present invention.
7 is a block diagram showing a gate pulse modulation apparatus according to a second embodiment of the present invention.
8 is a flowchart showing a gate pulse modulation method according to an embodiment of the present invention.
9 is a view illustrating a display device according to an embodiment of the present invention.
10 is a detailed block diagram of an option signal generator according to an embodiment of the present invention.
11 is a view showing that a printed circuit board (PCB) including a timing controller is located above the liquid crystal display device.
12 is a view showing that a printed circuit board (PCB) including a timing controller is positioned below the liquid crystal display device.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that although the present invention has been described with reference to a liquid crystal display as an example in the following embodiments, it is not limited to a liquid crystal display. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

The names of components used in the following description are selected in consideration of ease of specification, and may be different from actual product names.

FIG. 4 is a waveform diagram showing an example in which six-phase gate shift clocks are modulated in synchronism with the FLK signal in the reverse shift mode of the present invention. In FIG. 4, 'GPM' indicates the modulation timing of the gate shift clock.

4, the control signal generator outputs 6-phase gate shift clocks GCLK1-GCLK6 whose phases are sequentially delayed and an FLK signal generated at frequencies higher than 6-phase gate shift clocks GCLK1-GCLK6 do. The gate shift clocks GCLK1 to GCLK6 are phase clocks having a predetermined phase difference. The gate shift clock is used as a clock signal for shifting the gate start pulse (GSP). The gate shift clocks (GCLK1 to GCLK6) and the FLK signal swing between the ground voltage (GND 0V) and the logic power supply voltage (Vcc 3.3V).

In the reverse shift mode, the gate shift clocks are sequentially shifted in the order of GCLK6 to GCLK1 as shown in Figs. In the reverse shift mode as shown in FIG. 4, the nth gate shift clock (n is an integer circulating between 1 and 6 in FIG. 4) is overlapped with the leading portion of the (n-1) th gate shift clock for a predetermined time, 1 < / RTI > gate shift clock. For example, in the reverse shift mode, the second gate shift clock GCLK2 is superimposed on the front portion of the first gate shift clock GCLK1 and overlaps the rear portion of the third gate shift clock GCLK3. In the forward shift mode, the gate shift clocks are sequentially shifted in the order of GCLK1 to GCLK6 as shown in Fig.

The clocks of the FLK signal are synchronized with each of the gate shift clocks GCLK1 to GCLK6. The frequency of the FLK signal is about six times higher than the frequency of the gate shift clocks (GCLK1 to GCLK6).

The 6-phase gate shift clocks as shown in FIG. 4 may be modulated using a gate pulse modulation apparatus as shown in FIG.

5 is a simulation image showing an example in which, in the reverse shift mode, the gate shift clock is modulated at a normal time. As can be seen in FIG. 5, the present invention modulates the gate high voltage (VGH) at the falling edge of the gate shift clock in the reverse shift mode.

6 is a block diagram showing a gate pulse modulation apparatus according to the first embodiment of the present invention. Referring to FIG. 6, the gate pulse modulation apparatus of the present invention includes a control signal generator, an option signal generator, an overlapped interval detector 100, a gate shift clock modulator 200, and the like.

The control signal generator generates gate shift clocks for shifting gate pulses to be sequentially supplied to the gate lines of the display panel and an FLK signal for controlling the modulation timing of the gate shift clocks.

6, the gate shift clocks GCLK1 to GCLK6 illustrate six-phase clocks. The gate shift clocks include n-2 (n is a positive integer of 3 or more) to n + 2 gate shift clocks GCLK n-2 to GCLK n + 2, which are partially overlapped with each other. In the forward shift mode, the gate shift clocks are sequentially delayed from the (n-2) th gate shift clock GCLK n-2 to the (n + 2) th gate shift clock GCLK n + 2. In the reverse shift mode, the gate shift clocks are sequentially delayed in order from the (n + 2) -th gate shift clock GCLK n + 2 to the (n-2) -th gate shift clock GCLK n-2. The n-2 th to (n + 2) th gate shift clocks (GCLK n-2 to GCLK n + 2) output from the control signal generating unit are input to the overlap period detecting unit 100.

The FLK signal is generated with clocks synchronized every clock of the gate shift clock to control the modulation timing of the gate pulse. The FLK signal output from the control signal generation unit is input to the gate shift clock modulation unit 200.

As shown in FIG. 9, the control signal generator may be implemented by a timing controller 51 that generates a timing control signal to control the operation timing of the driving circuit.

The option signal generator indicates the modulation timing of the gate shift clocks in the forward shift mode in which gate pulses are shifted in the forward direction and in the reverse shift mode in which gate pulses are shifted in the reverse direction. The option signal generator outputs the high logic voltage or the low logic voltage as an option signal OPT and the option signal OPT is input to the gate shift clock modulation unit 200. The high logic voltage may be implemented at approximately 3.3V and the low logic voltage at 0V.

The overlap detecting unit 100 detects overlapping periods of the gate shift clocks. The overlap detecting section 100 includes a first detecting section 11 for detecting an overlap period of nth to (n + 2) th gate shift clocks GCLK n to GCLK n + 2, (GCLK n-2 to GCLK n).

The first detector 11 receives the nth to (n + 2) th gate shift clocks GCLK n to GCLK n + 2 from the control signal generator. The first detection unit 11 includes a first AND gate 11 for outputting a result of a logical multiplication of nth to (n + 2) th gate shift clocks GCLK n to GCLK n + 2. The result output from the first detection unit 11 is input to the gate shift clock modulation unit 200.

The second detection unit 12 includes a second AND gate 12 for outputting a result of the AND operation of the (n-2) th to (n) th gate shift clocks GCLK n-2 to GCLK n. The result output from the second detection unit 12 is input to the gate shift clock modulation unit 200.

The gate shift clock modulation unit 200 selects any one of the output of the first detection unit 11 and the output of the second detection unit 12 of the overlapping section detection unit 100 in response to the option signal OPT, The high logic voltage of the gate shift clock is modulated in response to the FLK signal. The gate shift clock modulation section 200 includes a selection section, a control section, and a modulation drive section.

The selecting unit inverts the option signal OPT output from the option signal generating unit to generate an inverting option signal and outputs the output of the first detecting unit 11 and the output of the second detecting unit 12 ) Is selected.

The selector includes a first inverter 31, a third AND gate 13, a fourth AND gate 14, and an OR gate 21. The first inverter 31 inverts the option signal OPT to generate an inverting option signal. The third AND gate 13 outputs a result of the AND operation of the inverted option signal inverted through the first inverter 31 and the output of the first detector 11 of the overlap period detector 100. The fourth AND gate 14 outputs a result of the AND operation of the option signal OPT and the output of the second detector 12 of the overlap section detector 100. The OR gate 21 outputs a result of performing an OR operation on the output of the third AND gate 13 and the output of the fourth AND gate 14.

The control unit controls the modulation timing of the gate shift clock in response to the FLK signal output from the control signal generation unit and the output of the selection unit. The control unit includes a second inverter (32) and a fifth AND gate (15). The second inverter 32 inverts the FLK signal to generate an inverted FLK signal. The fifth AND gate 15 outputs the result of the AND operation of the inverted FLK signal and the output of the OR gate 21 of the selector.

The modulation driving unit down-modulates the high logic voltage of the gate shift clock in response to the output of the control unit. The modulation driver includes first to third switch elements. The first and third switch elements 41 and 43 may be implemented as a p-type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), and the second switch element 42 may be implemented as an n-type MOSFET.

The first switch element 41 is turned on in response to the high logic voltage (3.3V) of the n-th gate shift clock GCLK n. The modulation driver outputs the gate high voltage VGH when the first switch element 41 is turned on. The second switch element 42 is turned on in response to the low logic voltage (0 V) of the n-th gate shift clock GCLK n. The modulation driving section outputs the gate low voltage VGL lower than the gate high voltage VGH when the second switch element 42 is turned on. The third switch element 43 is turned on in response to the output of the control section. The modulation driver outputs the modulation voltage VGM when the third switch element 43 is turned on. The gate high voltage VGH is a voltage of 15V or more, and the gate low voltage VGL is a voltage of -3V or less. The modulation voltage VGM is lower than the gate high voltage VGH and higher than the gate low voltage VGL.

The logic gates on the overlap section detection unit 100 and the gate shift clock modulation unit 200 of the present invention can be freely configured through general-purpose transistors.

7 is a block diagram showing a gate pulse modulation apparatus according to a second embodiment of the present invention. FIG. 7 illustrates a case where gate shift clocks are four-phase clocks. The control signal generator may generate four-phase gate shift clocks (GCLK1 to GCLK4). In this case, the gate shift clocks include m-1 (m is a positive integer of 2 or more) to m + 1 gate shift clocks GCLK m-1 to GCLK m + 1 which are partially overlapped with each other.

In the forward shift mode, the gate shift clocks are sequentially delayed in order from the m-1 gate shift clock GCLK m-1 to the m + 1 gate shift clock GCLK m + 1. In the reverse shift mode, the gate shift clocks are sequentially delayed in order from the m + 1 gate shift clock GCLK m + 1 to the m-1 gate shift clock GCLK m-1. The m-1 th to (m + 1) th gate shift clocks GCLK m-1 to GCLK m + 1 output from the control signal generating unit are input to the overlap period detecting unit 100.

The overlap detecting unit 100 detects overlapping periods of the gate shift clocks. The overlap detecting section 100 includes a first detecting section 11 for detecting an overlap period of the mth to (m + 1) th gate shift clocks GCLK m to GCLK m + 1, (GCLK m-1 to GCLK m).

Other parts are the same as the case where the control signal generator generates 6-phase gate shift clocks. Meanwhile, the gate shift clocks of the present invention are not limited to 6-phase gate shift clocks or 4-phase gate shift clocks. For example, the control signal generator may output n-phase gate shift clocks sequentially delayed with the FLK signal.

8 is a flowchart showing a gate pulse modulation method according to an embodiment of the present invention. 8 is a gate pulse modulation method for a 6-phase gate shift clock.

Referring to FIG. 8, the gate pulse modulation method includes first through sixth steps S1 through S6.

The first step S1 generates the gate shift clocks for shifting the gate pulses to be sequentially supplied to the gate lines of the display panel and the FLK signal for controlling the modulation timing of the gate shift clocks. In addition, the first step S1 generates the option signal OPT indicating the modulation timing of the gate shift clocks in the forward shift mode and the reverse shift mode.

The second step S2 includes a first overlapping period of the n-th to (n + 2) th gate shift clocks GCLK n to GCLK n + 2, To GCLK n). If the second step is implemented in hardware, it is the same as the overlap period detection unit 100 shown in FIG. 6 and FIG.

The third step S3 determines whether the option signal OPT is a high logic voltage. The fourth step S4 down-modulates the gate high voltage VGH of the n-th gate shift clock GCLK n in the second overlap period, if the option signal OPT is a high logic voltage. The fifth step S5 down-modulates the gate high voltage VGH of the n-th gate shift clock GCLK n in the first overlap period, if the option signal OPT is a low logic voltage. The sixth step S6 outputs the n-th gate shift clock GCLK n modulated through the fourth and fifth steps as a gate pulse. Implementing the third through sixth steps in hardware is the same as the gate shift clock modulating unit 200 shown in Figs. 6 and 7.

The gate pulse modulation method can be applied not only to the six-phase gate shift clock exemplified above, but also to the four-phase gate shift clock. However, the gate shift clocks of the present invention are not limited to 6-phase gate shift clocks or 4-phase gate shift clocks. For example, the first stage may generate n-phase gate shift clocks that are sequentially delayed with the FLK signal.

The display device of the present invention includes any display device that sequentially supplies gate pulses (or scan pulses) to gate lines (or scan lines) to write video data to pixels by line sequential scanning. For example, the display device of the present invention can be any one of a liquid crystal display (LCD), an organic light emitting diode (OLED), and an electrophoresis (EPD) .

The liquid crystal display of the present invention may be implemented in a liquid crystal mode such as TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In Plane Switching) mode and FFS . The liquid crystal display device of the present invention can be realized in a Normally White mode or a Normally Black mode when it is classified into the transmittance versus voltage characteristics. The liquid crystal display device of the present invention can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, and a reflective liquid crystal display device.

9 and 10 are views schematically showing a display device according to an embodiment of the present invention. In the display panel 50, a liquid crystal layer is formed between two substrates. The lower substrate of the display panel 50 is connected to data lines, gate lines intersecting the data lines, TFTs formed at intersections of the data lines and the gate lines, TFTs connected to the TFTs, And a TFT array including storage capacitors and the like are formed. On the upper substrate of the display panel 50, a color filter array including a black matrix and a color filter is formed. The common electrode may be formed on the upper substrate in a vertical electric field driving mode such as a TN mode and a VA mode, and may be formed on a lower glass substrate together with the pixel electrode in a horizontal electric field driving mode such as an IPS mode and an FFS mode. On the upper substrate and the lower substrate of the display panel 50, a polarizing plate whose optical axis is orthogonal is attached, and an alignment film for setting a pretilt angle of the liquid crystal is formed at the interface with the liquid crystal layer.

The display panel 50 is not limited to a liquid crystal display, and may be implemented by any one of an organic light emitting diode display (OLED) and an electrophoretic display (EPD).

The data drive circuit includes a plurality of source drive ICs 52. The source drive ICs 52 receive the digital video data RGB from the timing controller 51. [ The source drive ICs 52 convert the digital video data RGB to a positive / negative analog data voltage in response to a source timing control signal from the timing controller 51, To the data lines of the display panel (50). The source drive ICs 52 may be connected to the data lines of the display panel 50 by a COG (Chip On Glass) process or a TAB (Tape Automated Bonding) process. The source drive ICs 52 are mounted on a TCP (Tape Carrier Package) and are bonded to a printed circuit board (PCB) 55 and a lower glass substrate of the display panel 50 in a TAB manner.

10 is a detailed block diagram of an option signal generator 56 according to an embodiment of the present invention. The option signal generator 56 indicates the modulation timing of the gate shift clocks in the forward shift mode and the reverse shift mode.

10, the option signal generator 56 includes an option pin terminal formed in the IC chip of the gate driver to supply an option signal to the gate driver, an optional pin terminal, a power voltage source for generating a high logic voltage, And a switch element connected between the base voltage source generating the logic voltage and applying either the high logic voltage or the low logic voltage of the option signal to the option pin terminal. The high logic voltage may be implemented at approximately 3.3V and the low logic voltage at 0V.

9 and 10, the gate shift clocks GCLK1 to GCLK6 illustrate six-phase clocks, but may be implemented with four-phase clocks. However, the gate shift clocks of the present invention are not limited to 6-phase clocks or 4-phase clocks, and may be implemented with n-phase gate shift clocks.

9, the gate drive circuit includes a level shifter 54 connected between the timing controller 51 and the gate lines of the display panel 50, and a shift register 53 .

The level shifter 54 level shifts the TTL (Transistor-Transistor-Logic) logic level of the gate shift clocks GCLK inputted from the timing controller 51 to the gate high voltage VGH and the gate low voltage VGL . The gate shift clocks GCLK1 to GCLK6 are input to the level shifter 54 as an n-phase clock having a predetermined phase difference.

The level shifter 54 may include an overlap section detection section. In this case, the gate shift clocks input from the timing controller 51 are input to the overlap section detection section, and the overlap section detection section detects the overlap section of the gate shift clocks. In the case of a 6-phase gate shift clock, the overlap section detection section includes a first detection section for detecting overlapping sections of the nth to (n + 2) th gate shift clocks (GCLK n to GCLK n + 2) And a second detecting section for detecting an overlapping section of the shift clocks GCLK n-2 to GCLK n. The level shifter 54 selects one of the overlapping intervals output from the overlapping section detection unit in response to the option signal of the option signal generation unit 56 and outputs the selected overlapping interval in response to the FLK signal input from the timing controller 51. [ The gate high voltage VGH of the gate shift clock is modulated.

The overlapping section detecting section may be constituted by one circuit outside the level shifter 54. [ In this case, the overlap section detector receives the gate shift clocks from the timing controller 51, and detects the overlap section of the gate shift clocks. When the overlapping sections output from the overlapping section detection section are input to the level shifter 54, the level shifter 54 selects any one of the detected overlapping sections, and the FLK signal inputted from the timing controller 51 in the selected overlapping section And modulates the gate high voltage VGH of the gate shift clock in response to the clock signal CLK.

The overlapping section detecting section and the overlapping section selecting section may be constituted by one circuit outside the level shifter 54. [ In this case, the overlap section detector receives the gate shift clocks from the timing controller 51, and detects the overlap section of the gate shift clocks. The overlapping section selection section selects one of the overlapping sections output from the overlapping section detection section and outputs the selected overlapping section to the level shifter 54. The level shifter 54 modulates the gate high voltage VGH of the gate shift clock in the overlapping section output from the overlap section selection section in response to the FLK signal input from the timing controller 51. [

The level shifter 54 may be represented by a block diagram according to the first embodiment shown in Fig. 6, or a block equivalent to the second embodiment shown in Fig.

The shift register 53 shifts the clocks input from the level shifter 54 and sequentially supplies gate pulses to the gate lines of the display panel 50.

The gate drive circuit may be formed directly on the lower substrate of the display panel 50 in a GIP (Gate In Panel) manner or may be connected between the gate lines of the display panel 50 and the timing controller 51 in a TAB manner. In the GIP scheme, the level shifter 54 is mounted on the printed circuit board (PCB) 55, and the shift register 53 can be formed on the lower substrate of the display panel 50. In the TAB method, the level shifter 54 and the shift register 53 are integrated into one IC chip, mounted on the TCP, and bonded to the lower substrate of the display panel 50.

The timing controller 51 also serves as a control signal generating section as described above. The timing controller 51 receives digital video data RGB from an external host computer through an interface such as a Low Voltage Differential Signaling (LVDS) interface or a Transition Minimized Differential Signaling (TMDS) interface. The timing controller 51 transmits the digital video data RGB input from the host computer to the source drive ICs 52.

The timing controller 51 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE and a main clock MCLK from the host computer through an LVDS or TMDS interface receiving circuit And receives a signal. The timing controller 51 generates timing control signals for controlling the operation timing of the source drive ICs 52 and the gate drive circuit on the basis of the timing signal from the host computer. The timing control signals include a gate timing control signal for controlling the operation time of the gate drive circuit, a data timing control signal for controlling the operation timing of the source drive ICs 52 and the polarity of the data voltage.

The gate timing control signal includes a gate start pulse GSP, a gate shift clock GCLK, a FLK signal, a gate output enable signal GOE, and the like. The gate start pulse GSP is input to the shift register 53 to control the shift start timing. The gate shift clock GCLK is input to the level shifter 54 and level-shifted, and then input to the shift register 53 and used as a clock signal for shifting the gate start pulse GSP. The FLK signal is generated with clocks synchronized with each clock of the gate shift clock (GCLK) to control the modulation timing of the gate pulse. The gate output enable signal GOE controls the output timing of the shift register 53.

The data timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), and a source output enable signal (SOE) . The source start pulse SSP controls the shift start timing of the source drive ICs 52. [ The source sampling clock SSC is a clock signal that controls the sampling timing of the data in the source drive ICs 52 based on the rising or falling edge. The polarity control signal POL controls the polarity of the data voltage output from the source drive ICs 52. [ The source start pulse SSP and the source sampling clock SSC may be omitted if the data transfer interface between the timing controller 51 and the source drive ICs 52 is a mini LVDS interface.

11 is a view showing that a printed circuit board (PCB) including a timing controller is located above the liquid crystal display device. 11, a liquid crystal display device such as a monitor or a TV is driven in a standing state so that the screen can be easily viewed, and a printed circuit board (PCB) 55 including a timing controller is usually placed at the top of the liquid crystal display do. In this case, when the liquid crystal display device is driven, much heat is generated due to a backlight or the like, and the generated heat moves to the upper portion of the liquid crystal display device. As a result, the timing controller is further heated, and the timing controller may malfunction due to heat.

12 is a view showing that a printed circuit board (PCB) including a timing controller is positioned below the liquid crystal display device. As shown in FIG. 12, when the printed circuit board (PCB) 55 including the timing controller is positioned below the liquid crystal display, the timing controller can operate efficiently regardless of the temperature characteristics. In addition, since the liquid crystal display device is becoming lighter and thinner, it is advantageous in terms of space utilization that the printed circuit board (PCB) 55 is disposed under the liquid crystal display device having a relatively large space. When the timing controller is positioned below the liquid crystal display, gate pulses are sequentially supplied from the bottom of the liquid crystal display panel. That is, gate pulses are sequentially supplied to the gate lines in the reverse direction.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100: Overlap section detecting section 200: Gate shift clock modulating section
11: first detection unit, first AND gate 12: second detection unit, second AND gate
13: third AND gate 14: fourth AND gate
15: fifth AND gate 21: OR gate
31: first inverter 32: second inverter
41: first switch element 42: second switch element
43: third switch element 50: display panel
51: Timing controller 52: Source drive IC
53: shift register 54: level shifter
55: printed circuit board (PCB) 56: option signal generating section

Claims (20)

(Hereinafter referred to as "FLK signal") for controlling the modulation timing of the gate shift clocks and gate shift clocks for shifting the gate pulses to be sequentially supplied to the gate lines of the display panel A control signal generator for generating a control signal;
An option signal generator for generating an option signal of the first logic voltage in the forward shift mode and generating an option signal to the second logic voltage in the reverse shift mode;
A first detector for detecting an overlap period of an nth (n is a positive integer of 3 or more) to n + 2 gate shift clocks among the gate shift clocks;
A second detector for detecting an overlap period of the (n-2) th to (n) th gate shift clocks among the gate shift clocks;
A selection unit for generating an inversion option signal by inverting the option signal and selecting either the output of the first detection unit or the output of the second detection unit in response to the option signal and the inversion option signal;
A control unit for controlling the modulation timing of the gate shift clock in response to the FLK signal and the output of the selection unit; And
And a modulation driver for down-modulating a gate high voltage of the gate shift clocks in response to an output of the controller,
The control signal generator shifts the gate shift clocks, superimposes the gate shift clocks on each other,
The gate shift clock is sequentially delayed from the (n + 2) -th gate shift clock to the (n + 2) -th gate shift clock in the forward shift mode, while the gate shift clock is sequentially delayed from the And the gate shift clock is sequentially delayed in the order of the (n-2) th gate shift clock.
delete delete The method according to claim 1,
Wherein the first detection unit comprises:
And a first AND gate for outputting a result of a logical multiplication of the nth to (n + 2) th gate shift clocks.
5. The method of claim 4,
Wherein the second detection unit comprises:
And a second AND gate for outputting a result of an AND operation of the (n-2) th to (n) th gate shift clocks.
delete 6. The method of claim 5,
Wherein the selection unit comprises:
A first inverter for inverting the option signal to generate an inverted option signal;
A third AND gate for outputting a result of the AND operation of the inverted option signal and the output of the first detector;
A fourth AND gate for outputting a result of the AND operation of the option signal and the output of the second detector; And
And an OR gate for outputting a result of performing an OR operation on the output of the third AND gate and the output of the fourth AND gate.
8. The method of claim 7,
Wherein,
A second inverter for inverting the FLK signal to generate an inverted FLK signal; And
And a fifth AND gate for outputting a result of the AND operation of the inverted FLK signal and the output of the OR gate.
9. The method of claim 8,
The modulation driving unit includes:
A first switch element for outputting said gate high voltage in response to said nth gate shift clock;
A second switch element responsive to the nth gate shift clock for outputting a gate low voltage lower than the gate high voltage;
And a third switch element responsive to an output of the control section for outputting a modulation voltage lower than the gate high voltage and higher than the gate low voltage.
(Hereinafter referred to as "FLK signal") for controlling the modulation timing of the gate shift clocks and gate shift clocks for shifting the gate pulses to be sequentially supplied to the gate lines of the display panel A control signal generator for generating a control signal;
An option signal generator for generating an option signal of the first logic voltage in the forward shift mode and generating an option signal to the second logic voltage in the reverse shift mode;
A first detector for detecting an overlap period of the mth (m is a positive integer of 2 or more) to m + 1 gate shift clocks among the gate shift clocks;
A second detector for detecting an overlapping period of m-1 th to m-th gate shift clocks among the gate shift clocks;
A selection unit for generating an inversion option signal by inverting the option signal and selecting either the output of the first detection unit or the output of the second detection unit in response to the option signal and the inversion option signal;
A control unit for controlling the modulation timing of the gate shift clock in response to the FLK signal and the output of the selection unit; And
And a modulation driver for down-modulating a gate high voltage of the gate shift clocks in response to an output of the controller,
The control signal generator shifts the gate shift clocks, superimposes the gate shift clocks on each other,
The gate shift clock is sequentially delayed from the (m + 1) -th gate shift clock to the (m + 1) -th gate shift clock in the forward shift mode, while the gate shift clock is sequentially delayed from the And the gate shift clock is sequentially delayed in order of the (m-1) th gate shift clock.
delete 11. The method of claim 10,
Wherein the first detection unit comprises:
And outputs a result of the AND operation of the mth to (m + 1) th gate shift clocks.
13. The method of claim 12,
Wherein the second detection unit comprises:
And outputting a result of the AND operation of the (m-1) th to (m) th gate shift clocks.
(Hereinafter referred to as "FLK signal") for controlling the modulation timing of the gate shift clocks and gate shift clocks for shifting the gate pulses to be sequentially supplied to the gate lines of the display panel ;
Generating an option signal of a first logic voltage in a forward shift mode and an option signal in a reverse shift mode to a second logic voltage;
Detecting an overlapping section of an nth (n is a positive integer of 3 or more) to (n + 2) -th gate shift clocks among the gate shift clocks using a first detecting unit;
Detecting an overlap period of the (n-2) th to (n) th gate shift clocks among the gate shift clocks using the second detection unit;
Generating an inversion option signal by inverting the option signal and selecting either the output of the first detection unit or the output of the second detection unit in response to the option signal and the inversion option signal;
Controlling the modulation timing of the gate shift clock in response to the output of the detection unit selected from the first and second detection units and the FLK signal; And
Modulating the gate high voltage of the gate shift clocks at the modulation timing of the gate shift clock,
The gate shift clocks are shifted while being overlapped with each other,
The gate shift clock is sequentially delayed from the (n + 2) -th gate shift clock to the (n + 2) -th gate shift clock in the forward shift mode, while the gate shift clock is sequentially delayed from the And the gate shift clock is sequentially delayed in the order of the (n-2) th gate shift clock.
A display panel on which gate lines and data lines cross;
(Hereinafter, referred to as "FLK signal") for controlling the modulation timing of the gate shift clocks and gate shift clocks for shifting gate pulses to be sequentially supplied to the gate lines, A signal generator;
An option signal generator for generating an option signal of the first logic voltage in the forward shift mode and generating an option signal to the second logic voltage in the reverse shift mode;
A first detector for detecting an overlap period of an nth (n is a positive integer of 3 or more) to n + 2 gate shift clocks among the gate shift clocks;
A second detector for detecting an overlap period of the (n-2) th to (n) th gate shift clocks among the gate shift clocks;
A selection unit for selecting the output of the first detection unit and the output of the second detection unit in response to the option signal and the inverted option signal by inverting the option signal to generate an inverted option signal, And a modulation driver for down-modulating a gate high voltage of the gate shift clocks in response to an output of the control unit, so that the gate shift clocks are input A gate driver for receiving the gate pulses; And
And a data driver for supplying data voltages synchronized with the gate pulses to the data lines,
The control signal generator shifts the gate shift clocks, superimposes the gate shift clocks on each other,
The gate shift clock is sequentially delayed from the (n + 2) -th gate shift clock to the (n + 2) -th gate shift clock in the forward shift mode, while the gate shift clock is sequentially delayed from the And the gate shift clock is sequentially delayed in the order of the (n-2) th gate shift clock.
16. The method of claim 15,
Wherein the option signal generator comprises:
An optional pin terminal formed on an IC chip of the gate driver to supply an optional signal to the gate driver;
A switch for connecting either the high logic voltage or the low logic voltage of the option signal to the option pin terminal, the switch being connected between the option pin terminal, a power supply voltage source for generating a high logic voltage, and a base voltage source for generating a low logic voltage, A display comprising a device.
16. The method of claim 15,
Wherein the control signal generator, the option signal generator, and the data driver are located below the display device.
18. The method according to any one of claims 15 to 17,
Wherein the display device is one of a liquid crystal display (LCD), an organic light emitting diode display (OLED), and an electrophoretic display (EPD).
(Hereinafter referred to as "FLK signal") for controlling the modulation timing of the gate shift clocks and gate shift clocks for shifting the gate pulses to be sequentially supplied to the gate lines of the display panel ;
Generating an option signal of a first logic voltage in a forward shift mode and an option signal in a reverse shift mode to a second logic voltage;
Detecting an overlapping section of the m-th gate shift clock (m is a positive integer of 2 or more) to m + 1 gate shift clocks among the gate shift clocks using the first detector;
Detecting overlapping sections of the m-th to (m-1) th gate shift clocks among the gate shift clocks using the second detecting section;
Generating an inversion option signal by inverting the option signal and selecting either the output of the first detection unit or the output of the second detection unit in response to the option signal and the inversion option signal;
Controlling the modulation timing of the gate shift clock in response to the output of the detection unit selected from the first and second detection units and the FLK signal; And
Modulating the gate high voltage of the gate shift clocks at the modulation timing of the gate shift clock,
The gate shift clocks are shifted while being overlapped with each other,
The gate shift clock is sequentially delayed from the (m + 1) -th gate shift clock to the (m + 1) -th gate shift clock in the forward shift mode, while the gate shift clock is sequentially delayed from the And the gate shift clock is sequentially delayed in order of the (m-1) th gate shift clock.
A display panel on which gate lines and data lines cross;
(Hereinafter, referred to as "FLK signal") for controlling the modulation timing of the gate shift clocks and gate shift clocks for shifting gate pulses to be sequentially supplied to the gate lines, A signal generator;
An option signal generator for generating an option signal of the first logic voltage in the forward shift mode and generating an option signal to the second logic voltage in the reverse shift mode;
A first detector for detecting an overlap period of the mth (m is a positive integer of 2 or more) to m + 1 gate shift clocks among the gate shift clocks;
A second detector for detecting an overlapping period of m-1 th to m-th gate shift clocks among the gate shift clocks;
A selection unit for selecting the output of the first detection unit and the output of the second detection unit in response to the option signal and the inverted option signal by inverting the option signal to generate an inverted option signal, And a modulation driver for down-modulating a gate high voltage of the gate shift clocks in response to an output of the control unit, so that the gate shift clocks are input A gate driver for receiving the gate pulses; And
And a data driver for supplying data voltages synchronized with the gate pulses to the data lines,
The control signal generator shifts the gate shift clocks, superimposes the gate shift clocks on each other,
The gate shift clock is sequentially delayed from the (m + 1) -th gate shift clock to the (m + 1) -th gate shift clock in the forward shift mode, while the gate shift clock is sequentially delayed from the And the gate shift clock is sequentially delayed in order of the (m-1) th gate shift clock.

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