CN106875903B

CN106875903B - Display device and driving method thereof

Info

Publication number: CN106875903B
Application number: CN201611044029.5A
Authority: CN
Inventors: 李度坤; 柳连泽
Original assignee: LG Display Co Ltd
Current assignee: LG Display Co Ltd
Priority date: 2015-11-25
Filing date: 2016-11-23
Publication date: 2020-04-21
Anticipated expiration: 2036-11-23
Also published as: KR102556962B1; CN106875903A; KR20170061590A

Abstract

Disclosed are a display device and a driving method thereof, the display device including: a timing controller turned on into a floating state by a first logic voltage and switched from the floating state to a normal operation state by a reset signal to generate a timing control signal after a switching period; a level shifter receiving the first logic voltage and the second logic voltage, and level-shifting the timing control signal to the second logic voltage and outputting; and an output enable signal control section that outputs an output enable signal at an enable level "low" or a disable level "high" in synchronization with the reset signal, wherein during the switching period, the level shifter receives the output enable signal at the disable level "high" and stops the level shifting.

Description

Display device and driving method thereof

Technical Field

The present invention relates to a display device and a driving method thereof.

Background

The main types of display devices include Liquid Crystal Displays (LCDs) and OLED displays comprising Organic Light Emitting Diodes (OLEDs). OLED displays and LCDs come in a variety of sizes, both large and small, and are used in many applications, such as mobile phones, notebook computers, monitors, televisions, and the like.

The display device includes: a display panel having a plurality of pixels arranged in a matrix; a gate driver driving gate lines on the display panel; a data driver which drives data lines on the display panel; a timing control part which controls the gate driver and the data driver, and the like. The gate driver may be embedded in the display panel to reduce volume and weight, and this type of display is called a GIP (gate in panel) display.

In the GIP display, the timing control section includes a timing controller TCON generating a timing control signal and a level shifter LS outputting a plurality of gate driving control signals to be fed to the gate driver by using the timing control signal.

This will be described in detail with reference to fig. 1. The timing controller TCON receives the first logic voltage VCC25, generates timing control signals and feeds them to the level shifter LS. For example, the first logic voltage VCC25 may be 2.5V. The timing controller TCON continuously feeds the timing control signal to the level shifter LS until the received first logic voltage VCC25 drops to 2.5V or less.

In addition, the timing controller TCON receives a reset signal RST output from a reset IC (integrated circuit). The reset signal RST is input to the timing controller TCON at an initial stage of operation and is used to switch the timing controller TCON from a floating state to a normal operation state. More specifically, in an initial stage of operation, the timing controller TCON is turned on upon receiving a first logic voltage VCC25 of 2.5V applied thereto. However, the timing controller TCON is still in a floating state from which an unstable timing control signal is output. After a certain period of time, the timing controller TCON then receives the reset signal RST, thereby preventing the output signal in the floating state from abnormally operating.

This time period may be defined as a time taken for the timing controller TCON to receive the reset signal RST after being turned on in response to the first logic voltage VCC25 of 2.5V applied thereto (hereinafter referred to as a "switching period Tc"). The switching period Tc is the time taken for the timing controller TCON to switch from the floating state to the normal operation state.

The level shifter LS uses the first logic voltage VCC25 as input power and the second logic voltage VCC33 as output power, and converts the level of the timing control signal Tsig input from the timing controller TCON to 3.3V and then outputs. The level shifter LS performs level shifting upon receiving the output enable signal OE.

The output enable signal OE has an enable level (i.e., the output enable signal OE is in a low state) at which the level shifter LS normally operates, and a disable level at which the level shifter LS cannot be input and output.

However, the conventional level shifter LS has a problem in that, since the output enable signal OE is fixed at an enable level "LOW" (i.e., the enable terminal EN is connected to the ground power supply), even an abnormal signal output when the timing controller TCON is in a floating state is level-shifted once the input power VCC25 and the output power VCC33 are appropriately applied.

Further, in the initial stage of the operation, when the timing controller TCON is in a floating state, an abnormal signal is output and then the abnormal signal is coupled with an adjacent signal, thereby causing a glitch. In this case, since the level shifter LS is always available for output, the level shifter LS performs level shifting even on an abnormal signal caused by a glitch. In the case where an abnormal signal is input into the system or the panel driving circuit, this may cause malfunction of the display device.

Disclosure of Invention

Accordingly, the present invention relates to a display device and a driving method thereof that allow removal of an abnormal signal generated when a timing controller is in a floating state at an initial stage of operation.

An exemplary embodiment of the present invention provides a display device including: a timing controller turned on into a floating state by a first logic voltage and switched from the floating state to a normal operation state by a reset signal to generate a timing control signal after a switching period; a level shifter receiving the first logic voltage and the second logic voltage, and level-shifting the timing control signal to the second logic voltage and outputting; and an output enable signal control part outputting an output enable signal at an enable level "LOW" (LOW) or a disable level "HIGH" (HIGH) in synchronization with the reset signal, wherein the level shifter receives the output enable signal at the disable level HIGH and stops level shifting during the switching period.

Another exemplary embodiment of the present invention provides a display device, including: a timing controller operating in response to a reset signal and generating a timing control signal of a first logic voltage level; a level shifter which converts the timing control signal to a second logic voltage level higher than the first logic voltage level and outputs the same, and performs level conversion in response to an output enable signal; and an output enable signal control part which controls the output enable signal at a disable level HIGH during a switching period from the application of the second logic voltage of an ON (ON) level to the application of the reset signal of the ON level, and then controls the output enable signal at an enable level LOW after the switching period ends.

Another exemplary embodiment of the present invention provides a driving method of a display device, the method including: generating a timing control signal of a first logic voltage level in response to a reset signal; converting the timing control signal to a second logic voltage level higher than the first logic voltage level and outputting, and performing level conversion in response to the output enable signal; the output enable signal is controlled at a disable level HIGH during a switching period from the application of the second logic voltage of the turn-on level to the application of the reset signal of the turn-on level, and then controlled at an enable level LOW after the end of the switching period.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings:

fig. 1 is a waveform diagram illustrating an abnormal signal output from a level shifter when a timing controller is in a floating state in a display device according to the related art;

fig. 2 is a block diagram illustrating a display apparatus according to an exemplary embodiment of the present invention;

FIG. 3 is a waveform diagram showing signals input to the timing controller and level shifter of the present invention and the resulting output signal from the level shifter;

fig. 4 is a diagram showing an output enable signal control section that outputs an output enable signal at an enable level LOW or a disable level HIGH in synchronization with a reset signal; and

fig. 5 is a flowchart illustrating a driving method of a display device according to an exemplary embodiment of the present invention.

Detailed Description

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Throughout the specification, like reference numerals denote substantially identical elements. In the following description, a detailed description of known functions or configurations related to the present invention will be omitted if it is considered that the detailed description of the known functions or configurations related to the present invention unnecessarily obscure the subject matter of the present invention.

It should be noted that although the following description will be given with respect to a liquid crystal display device as an example of a display device, the technical idea of the present invention is not limited to a liquid crystal display but may be applied to other types of display devices.

Specific examples of the display device may include a liquid crystal display device (LCD), a plasma display Panel Device (PDP), a field emission display device (FED), an organic light emitting display device (OLED), and the like.

The organic light emitting display device includes a plurality of pixels. Each pixel includes an organic light emitting diode composed of an organic emission layer formed between an anode and a cathode and a pixel driving circuit independently driving the organic light emitting diode. The pixel driving circuit includes a switching thin film transistor (hereinafter, referred to as TFT), a driving TFT, and a capacitor. The switching TFT charges the capacitor with the data voltage in response to the scan pulse, and the driving TFT adjusts an amount of light emitted by the organic light emitting diode by controlling an amount of current supplied to the organic light emitting diode according to the data voltage charged in the capacitor.

The display device of the present invention can be implemented as all known liquid crystal modes such as a TN (twisted nematic) mode, a VA (vertical alignment) mode, an IPS (in-plane switching) mode, an FFS (fringe field switching) mode, and the like. In addition, the display device of the present invention may be implemented as any type of display device, such as a transmissive liquid crystal display, a semi-transmissive liquid crystal display, or a reflective liquid crystal display.

Fig. 2 is a block diagram illustrating a display apparatus according to an exemplary embodiment of the present invention. Fig. 3 is a waveform diagram showing signals input to the timing controller and the level shifter of the present invention and the resultant output signal from the level shifter. Fig. 4 is a diagram showing an output enable signal control section that outputs an output enable signal at an enable level LOW or a disable level HIGH in synchronization with a reset signal.

Referring to fig. 2 to 4, the display device 10 according to the present invention includes a display panel 11, a data driving circuit 12, a gate driving circuit 13, a timing controller 14, a level shifter 16, and an output enable signal control part (OECP) 17.

The display panel 11 includes data lines and gate lines crossing each other and pixels arranged in a matrix.

The display panel 11 includes upper and lower substrates facing each other with a liquid crystal cell (Clc) Clc therebetween. A pixel array including pixels arranged in a matrix is formed on the display panel 11, and an input image is displayed on the pixel array. The pixel array includes a TFT array formed on a lower substrate and a color filter array formed on an upper substrate. In the TFT array, TFTs (thin film transistors) are formed at intersections of data lines and gate lines. The TFT supplies a data voltage from the data line to the pixel electrode 1 of the liquid crystal cell Clc in response to a gate pulse from the gate line. Each of the liquid crystal cells Clc represents a desired gray level by controlling light transmittance according to a difference between a data voltage stored in the pixel electrode 1 and a common voltage Vcom applied to the common electrode 2. A storage capacitor Cst for maintaining a data voltage stored in the pixel electrode 1 for 1 frame period is connected to the liquid crystal cell Clc. The color filter array includes a color filter and a black matrix. Polarizers are attached to the upper and lower glass substrates of the display panel 11, respectively, and form alignment films for setting a pre-tilt angle of the liquid crystal.

The data driving circuit 12 may be implemented as a source drive IC. The data driving circuit 12 receives digital video data RGB from the timing controller 14. The data driving circuit 12 converts the digital video data RGB into a gamma compensation voltage in response to the data driving control signal DDC from the timing controller 14 to generate a data voltage, and supplies the data voltage to the data lines DL of the display panel 11 in synchronization with the gate pulse. The data driving circuit 12 may be connected to the data lines DL of the display panel 11 through a COG (chip on glass) process or a TAB (tape automated bonding) process.

The gate driving circuit 13 may be directly formed on the lower substrate of the display panel 11 by a GIP (gate in panel) technique. The gate driving circuit 13 may be formed in a non-display region of the display panel 11 outside a pixel region where an image is displayed. The gate driving circuit 13 may be implemented as a gate driving IC and connected to the gate lines GL of the display panel 11 through a TAB (tape automated bonding) process. The gate driving circuit 13 generates a gate pulse in response to a gate driving control signal GDC from the timing controller 14 and supplies the gate pulse to the gate line GL by a line-sequential (line-sequential) method. 1 horizontal line to be charged with the data voltage is selected according to the gate pulse.

Referring to fig. 2, the timing controller 14 receives digital video data RGB from the host system 15 and timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a dot clock DCLK. The timing controller 14 transmits the digital video data RGB to the source drive ICs of the data driving circuit 12. The timing controller 14 generates a data driving control signal DDC for controlling the operation timing of the source driving ICs and a gate driving control signal GDC for controlling the operation timing of the gate driving circuit 13 by using the timing signals Vsync, Hsync, DE, and DCLK.

The data driving control signal DDC includes a source start pulse SSP, a source sampling clock SSC, a source output enable signal SOE, a polarity control signal POL, and the like. The source start pulse SSP and the source sampling clock SSC control the timing of data sampling. The polarity control signal POL controls the timing of inverting the polarity of the data voltage output from the data driving circuit 12. The source output enable signal SOE controls the output timing and the charge sharing timing of the data driving circuit 12.

The gate driving control signal GDC includes a gate start pulse GSP, a gate shift clock GSC, and the like. The gate start pulse GSP controls the timing of the first gate pulse. The gate shift clock GSC is a clock signal for shifting the gate start pulse GSP.

Further, the timing controller 14 receives the first logic voltage VCC25, generates the timing control signals Tsig and supplies them to the level shifter 16. The timing control signal Tsig includes a gate modulation signal (e.g., FLK of fig. 4) for controlling the modulation timing of the gate pulse, a power enable signal (DPM of fig. 4) for controlling the generation timing of various types of power applied to the panel driving circuit, and a ready signal (DPX of fig. 4) for notifying the host system 15 that the timing controller 14 is ready to receive data, and the like.

Referring to fig. 2 and 3, in an initial stage of operation, the timing controller 14 is turned on upon receiving the first logic voltage VCC 25. However, the timing controller 14 is still in a floating state from which an unstable timing control signal is output. After the switching period Tc, the timing controller 14 then receives a reset signal RST from a reset IC (integrated circuit) and switches to a normal operation state. That is, the timing controller 14 is kept in a floating state in the initial stage of the operation until the reset signal RST is turned on. Once the reset signal RST is turned on, the timing controller 14 operates normally.

The actual timing at which the timing controller 14 generates the timing control signal Tsig is when the reset signal RST of the ON level is applied, not when the first logic voltage VCC25 of the ON level is applied. Even in the case where the first logic voltage VCC25 of the ON level is applied, the timing controller 14 remains in the floating state until the reset signal RST of the ON level is applied.

The reset IC may be embedded in the host system 15 or mounted on the control board 18.

The level shifter 16 uses the first logic voltage VCC25 as input power and the second logic voltage VCC33 higher than the first logic voltage VCC25 as output power to raise (shift) the timing control signal Tsig input from the timing controller 14 to the second logic voltage VCC33 higher than the first logic voltage VCC25 and then output it. The level shifter 16 may supply the gate drive control signal GDC among the boosted timing control signals Tsig to the gate drive circuit 13, and supply the other boosted timing control signals Tsig to the host system 15. The first logic voltage VCC25, which is the input power for the level shifter 16 and the timing controller 14, may be 2.5V but is not limited to 2.5V. The second logic voltage VCC33, which is the output power of the level shifter 16, may be 3.3V but is not limited to 3.3V.

The operation of the level shifter 16 is controlled by an output enable signal OE input to an enable terminal EN of the level shifter 16. The output enable signal OE has an enable level (i.e., the output enable signal OE is in a low state) at which the level shifter 16 normally operates, and a disable level at which the level shifter 16 cannot input and output.

Referring to fig. 2, the output enable signal OE applied from the output enable signal control section 17 is fixed at an enable level LOW, that is, the enable terminal EN is connected to the ground power supply, as in the related art.

As shown in fig. 3, the output enable signal OE applied from the output enable signal control section 17 is controlled at the disable level HIGH during the switching period Tc from the application of the second logic voltage VCC33 of the ON level to the application of the reset signal RST of the ON level, and then controlled at the enable level LOW after the switching period Tc ends. The output enable signal control section 17 controls the output enable signal OE at the disable level HIGH during the switching period Tc where an abnormal signal (glitch or the like) may occur, thereby blocking the operation of the level shifter 16 and preventing the output of the abnormal signal. Therefore, the switching period Tc may be a period for preventing the output of an abnormal signal.

In the initial stage of the operation, when the first logic voltage VCC25 rises to the ON level in the switching period Tc in which the timing controller 14 is in the floating state, the unstable timing control signal Tsig is output from the timing controller 14. The anomalous signal may then couple with neighboring signals, causing glitches. In this case, the level shifter 16 is controlled at the disable level HIGH by the output enable signal OE and is thus unavailable for output. Therefore, the level shifter 16 is prevented from outputting the unstable timing control signal Tsig output from the timing controller 14 as an abnormal signal caused by a glitch or the like. In order to ensure the safety of the operation, the timing of applying the second logic voltage VCC33 of the ON level (the start timing of the switching period Tc) may be earlier than the timing of applying the first logic voltage VCC25 of the ON level (the timing of the glitch) by a certain amount of time Tx.

Under the control of the output enable signal control section 17, the level shifter 16 stops the level shifting and output of the timing control signal Tsig during the switching period Tc in response to the output enable signal OE of the disable level HIGH. Then, the level shifter 16 starts level shifting and output of the timing control signal Tsig after the switching period Tc ends in response to the output enable signal OE of the enable level LOW.

Referring to fig. 4, the output enable signal control section 17 may control the logic level of the output enable signal OE based on the reset signal RST. For this, the output enable signal control section 17 includes a switching element SS and a resistor R, as shown in fig. 4.

The switching element SS includes a control electrode Ea connected to an input terminal of the reset signal RST, a first electrode Eb connected to a first node N1 that outputs an output enable signal OE, and a second electrode Ec connected to a ground voltage source GND. The switching element SS may be realized as a field effect transistor FET or as a bipolar junction transistor BJT.

The resistor R is connected between the input terminal of the second logic voltage VCC33 and the first node N1.

If the reset signal RST is input at the OFF level, the output enable signal control section 17 interrupts the current between the first node N1 and the ground voltage source GND by using the switching element SS, and outputs the second logic voltage VCC33 as the output enable signal OE. That is, the output enable signal control section 17 outputs the output enable signal OE of the disable level HIGH during the switching period Tc in which the reset signal RST is input at the OFF level.

If the reset signal RST is input at the ON level, the output enable signal control section 17 outputs the ground voltage as the output enable signal OE by allowing a current between the first node N1 and the ground voltage source GND to flow using the switching element SS. That is, the output enable signal control section 17 outputs the output enable signal OE at the enable level LOW during the switching period Tc in which the reset signal RST is input at the ON level.

Referring to fig. 2, the timing controller 14, the level shifter 16, and the output enable signal control part 17 may be mounted on the control board 18.

Fig. 5 illustrates a driving method of a display device according to an exemplary embodiment of the present invention.

Referring to fig. 5, a method of driving a display device according to an exemplary embodiment of the present invention includes: generating a timing control signal Tsig of a first logic voltage level VCC25 in response to a reset signal RST; converts and outputs the timing control signal Tsig to a second logic voltage level VCC33 higher than the first logic voltage level VCC25, and performs level conversion in response to the output enable signal OE; and controlling the output enable signal OE at the disable level HIGH during a switching period Tc from the application of the second logic voltage VCC33 of the ON level to the application of the reset signal RST of the ON level (S1, S2, and S3), and then controlling the output enable signal OE at the enable level LOW after the switching period Tc is ended (S1, S2, and S5).

At the time of level shift in response to the output enable signal OE, level shift and output of the timing control signal Tsig are stopped during the switching period Tc in response to the output enable signal OE of the disable level HIGH (S4).

Upon level conversion in response to the output enable signal OE, level conversion and output of the timing control signal Tsig are started after the switching period Tc ends in response to the output enable signal OE of the enable level LOW (S6).

As described above, the present invention enables the output enable signal input into the level shifter to be controlled at the disable level during the switching period Tc where an abnormal signal (glitch or the like) may occur, thereby stopping the operation of the level shifter during the switching period Tc and preventing the output of the abnormal signal. Thus, the present invention can prevent malfunction of the display apparatus by removing an abnormal signal generated when the timing controller is in a floating state at an initial stage of operation.

The technical idea of the present invention can be applied to other ICs and timing controllers that normally operate after remaining in a floating state for a predetermined period of time at an initial stage of operation.

Throughout the description, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the technical principle of the present invention. Therefore, the technical scope of the present invention is not limited to those detailed description herein, but should be defined by the scope of the appended claims.

Embodiments of the present invention can be described as follows.

An exemplary embodiment of the present invention provides a display device including: a timing controller turned on into a floating state by a first logic voltage and switched from the floating state to a normal operation state by a reset signal to generate a timing control signal after a switching period; a level shifter receiving the first logic voltage and the second logic voltage, and level-shifting the timing control signal to the second logic voltage and outputting; and an output enable signal control part outputting an output enable signal at an enable level LOW or a disable level HIGH in synchronization with the reset signal, wherein the level shifter receives the output enable signal at the disable level HIGH and stops level shifting during the switching period.

During the switching period, the timing controller outputs an abnormal signal that is coupled with an adjacent signal to cause a glitch.

After the switching period is ended, the level shifter receives the output enable signal of the enable level LOW, and level-shifts the timing control signal to the second logic voltage and outputs.

Some of the level-shifted timing control signals are supplied to the gate driving circuit, and other timing control signals are supplied to the host system.

The output enable signal control section includes a switching element and a resistor that control a logic level of the output enable signal.

The switching element includes: the circuit includes a first electrode receiving a reset signal, a second electrode outputting an output enable signal, and a third electrode connected to a ground voltage source.

The second electrode is connected in series to the input terminal of the second logic voltage and the resistor.

Another exemplary embodiment of the present invention provides a display device including: a timing controller operating in response to a reset signal and generating a timing control signal of a first logic voltage level; a level shifter which converts the timing control signal to a second logic voltage level higher than the first logic voltage level and outputs the same, and performs level conversion in response to an output enable signal; and an output enable signal control part which controls the output enable signal at a disable level HIGH during a switching period from the application of the second logic voltage of the ON level to the application of the reset signal of the ON level, and then controls the output enable signal at an enable level LOW after the switching period ends.

The level shifter stops level shifting and outputting of the timing control signal during the switching period in response to the output enable signal of the disable level HIGH.

In response to the output enable signal of the enable level LOW, the level shifter starts level shifting and output of the timing control signal after the end of the switching period.

The timing of applying the second logic voltage of the ON level is earlier than the timing of applying the first logic voltage of the ON level.

The output enable signal control part includes: a switching element including a control electrode connected to an input terminal of the reset signal, a first electrode connected to a first node outputting an output enable signal, and a second electrode connected to a ground voltage source; and a resistor connected between the input terminal of the second logic voltage and the first node.

The switching element is implemented as a field effect transistor or a bipolar junction transistor.

Another exemplary embodiment of the present invention provides a driving method of a display device, the method including: generating a timing control signal of a first logic voltage level in response to a reset signal; converting the timing control signal to a second logic voltage level higher than the first logic voltage level and outputting, and performing level conversion in response to the output enable signal; the output enable signal is controlled at a disable level HIGH during a switching period from the application of the second logic voltage of the ON level to the application of the reset signal of the ON level, and then controlled at an enable level LOW after the end of the switching period.

The method described above, wherein the level shifting and outputting of the timing control signal is stopped during the switching period in response to the output enable signal of the disable level HIGH when the level shifting is performed in response to the output enable signal.

When level shifting is performed in response to the output enable signal, level shifting and output of the timing control signal are started after the end of the switching period in response to the output enable signal at the enable level LOW.

Claims

1. A display device, comprising:

a timing controller turned on into a floating state by a first logic voltage and switched from the floating state to a normal operation state by a reset signal to generate a timing control signal after a switching period;

a level shifter receiving the first and second logic voltages, and level-shifting the timing control signal to the second logic voltage and outputting; and

an output enable signal control section that outputs an output enable signal at a disable level "high" when the timing controller is turned on into the floating state, and outputs an output enable signal at an enable level "low" when the timing controller is switched from the floating state to the normal operation state,

wherein during the switching period, the level shifter receives the output enable signal at a disable level "high" and stops level shifting, an

Wherein, after the switching period, the level shifter receives an output enable signal at an enable level "low" and performs level shifting of the timing control signal.

2. The display device according to claim 1, wherein the timing controller outputs an abnormal signal coupled with an adjacent signal to cause a glitch during the switching period.

3. The display device according to claim 1, wherein the level shifter receives an output enable signal at an enable level "low" after the switching period is ended, and level-shifts the timing control signal to the second logic voltage and outputs.

4. The display device according to claim 3, wherein some of the level-shifted timing control signals are supplied to the gate driving circuit, and the other timing control signals are supplied to the host system.

5. The display device according to claim 1, wherein the output enable signal control section includes a switching element and a resistor that control a logic level of the output enable signal.

6. The display device according to claim 5, wherein the switching element comprises:

a first electrode receiving the reset signal;

a second electrode outputting the output enable signal; and

a third electrode connected to a ground voltage source.

7. The display device according to claim 6, wherein the second electrode is connected in series to the input terminal of the second logic voltage and the resistor.

8. A display device, comprising:

a level shifter level-shifting the timing control signal to a second logic voltage higher than the first logic voltage and outputting, and level-shifting in response to an output enable signal; and

an output enable signal control part controlling the output enable signal to be at a disable level "high" during the switching period in which the timing controller is turned on into the floating state, wherein the second logic voltage becomes a conduction level of the second logic voltage at a start of the switching period in which the timing controller is turned on into the floating state, the reset signal becomes a conduction level of the reset signal at an end of the switching period in which the timing controller is switched from the floating state to the normal operation state, and the output enable signal control part controls the output enable signal to be at an enable level "low" after the end of the switching period.

9. The display device according to claim 8, wherein the level shifter stops level shifting and outputting of the timing control signal during the switching period in response to an output enable signal of a disable level "high".

10. The display device according to claim 8, wherein the level shifter starts level shifting and outputting of the timing control signal after the switching period ends in response to an output enable signal of an enable level "low".

11. The display device according to claim 8, wherein a timing of applying the on level of the second logic voltage is earlier than a timing of applying the on level of the first logic voltage.

12. The display device according to claim 8, wherein the output enable signal control section comprises:

a switching element including a control electrode connected to an input terminal of the reset signal, a first electrode connected to a first node outputting the output enable signal, and a second electrode connected to a ground voltage source; and

a resistor connected between the input of the second logic voltage and the first node.

13. The display device according to claim 12, wherein the switching element is implemented as a field effect transistor or a bipolar junction transistor.

14. A method of driving a display device, the method comprising:

turning on a timing controller of the display apparatus into a floating state by a first logic voltage, and after a switching period, switching the timing controller from the floating state to a normal operation state by a reset signal to generate a timing control signal;

level-converting the timing control signal to a second logic voltage higher than the first logic voltage and outputting, and level-converting in response to an output enable signal;

controlling the output enable signal to be "high" at a disable level during the switching period in which the timing controller is turned on into the floating state, wherein the second logic voltage becomes a turn-on level of the second logic voltage at a start of the switching period in which the timing controller is turned on into the floating state, and the reset signal becomes a turn-on level of the reset signal at an end of the switching period in which the timing controller is switched from the floating state to the normal operation state; and

the output enable signal is controlled to be at an enable level "low" after the switching period is ended.

15. The method of claim 14, wherein level shifting and outputting of the timing control signal is stopped during the switching period in response to an output enable signal of a disable level "high" when level shifting is performed in response to the output enable signal.

16. The method of claim 14, wherein the level shifting and outputting of the timing control signal is started after the end of the switching period in response to the output enable signal of an enable level "low" at the time of level shifting in response to the output enable signal.

17. The method of claim 14, wherein a timing of applying the turn-on level of the second logic voltage is earlier than a timing of applying the turn-on level of the first logic voltage.