KR20190080292A - Electronic device including display apparatus and method for driving the same - Google Patents

Abstract

The present invention relates to an electronic device including a display device capable of preventing a display failure caused by interlace driving and an optional update area during a PSR operation time, and a method for driving the same. According to one embodiment of the present invention, a system of the electronic device is configured to enable the PSR operation of the display device when a processed image is a still image, transmit a still image of at least one frame to the display device, and then turn off a transmitter. When the PSR operation is enabled according to control of the system, the display device of the electronic device stores, in a remote frame buffer, the still image of at least one frame transmitted from the system and displays, on a panel, the image stored in the frame buffer during an active period of the PSR operation. The display device detects whether data is transmitted from the system and operates a section, where there is no data transmitted from the system, in an interlace mode during an active period of the PSR operation and, when the data is transmitted from the system, updates a corresponding area of the remote frame buffer by using the data transmitted from the system and operates the area in a progressive mode.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic device including a display device,

The present invention relates to an electronic device including a display device capable of preventing display failure due to interlace driving and a selective update area during a panel self-refresh operation period, and a driving method thereof.

As a display device for displaying an image, a liquid crystal display (LCD) using a liquid crystal, an organic light emitting diode (OLED) display using an organic light emitting diode, an electrophoretic display using an electrophoretic particle ; EPD).

The display device includes a panel for displaying an image through a pixel array, a panel driver for driving the panel, and a timing controller for controlling the panel driver. The panel driver includes a gate driver for driving the gate lines of the panel, And a data driver for driving the data lines.

The system normally supplies all the image information necessary for the display device to the timing controller in real time, and the timing controller supplies all the image information to the data driver. The data driver converts the digital data supplied from the timing controller into analog data and outputs the analog data to the panel to display the image on the panel.

In an electronic device such as a notebook computer, a tablet, or a smart phone, the system (or processor) stores a still image of one frame in the remote frame buffer of the display device when the current processed image is a still image, (Hereinafter referred to as " panel self-refresh ") which can improve the battery life by reducing power consumption by stopping the power supply.

When the PSR mode is activated by the system, the display device divides the image stored in the remote frame buffer into an odd frame for driving od horizontal lines and an even frame for driving odd horizontal lines. And operates in an interlace mode in which the power consumption is further reduced.

Meanwhile, the system may update the SU area of the remote frame buffer by transmitting the data of the selective update area (SU area) to the display device when the area of the still image needs to be updated during the active period of the PSR mode .

However, when the system continuously transmits the data of the SU area for several frame times, the display device displays the SU area updated as the writing speed at which the SU area is updated is faster than the speed at which the remote frame buffer is read due to the interlace driving. There is a problem that a display failure which can not display the data of the display device is not fully displayed.

The present invention provides an electronic device including a display device capable of preventing display failure due to interlace driving and a selective update area during a PSR operation time and a driving method thereof.

An electronic device according to an embodiment includes a system and a display device. The system enables the PSR operation of the display device when the processed image is a still image, and transmits the still image of at least one frame to the display device, and then turns off the transmitting portion. When the PSR operation is enabled according to the control of the system, the display device stores at least one frame of the still image transmitted from the system in the remote frame buffer and displays the image stored in the remote frame buffer in the active period of the PSR operation on the panel . The display device monitors whether or not data is transmitted from the system during the active period of the PSR operation, and operates in an interlaced mode when there is no data transmission from the system. When a data transmission occurs from the system, And operates in the progressive mode.

The system transmits the PSR active signal for enabling the PSR operation to the timing controller of the display device and transmits the data of the selective update area requiring update in the PSR active section of the PSR active signal to the timing controller together with the position information of the area . The timing controller performs the PSR operation in response to the PSR active signal. The timing controller detects whether or not the system transmits data in units of frames in the PSR active section. When the data transmission is not detected, the timing controller operates in the interlace mode. Updates the corresponding area of the remote frame buffer with the data of the selected update area and operates in the progressive mode.

The timing controller operates in the progressive mode and then in the interlaced mode while storing the image transmitted from the system for at least one frame after the PSR active signal is enabled in the re-mode frame buffer. During the PSR active period, the timing controller operates in the progressive mode when data transmission from the system is detected, further operates in the progressive mode for at least one frame if data transmission from the system is not detected after operating in the progressive mode, .

 The timing controller initializes the frame count when a data transmission from the system is detected during the PSR active period, and increases the frame count if no data transmission from the system is detected. The timing controller operates in the progressive mode when the frame count is less than the preset reference value, and operates in the interlaced mode when the frame count becomes the reference value or more.

A method of driving an electronic device according to an embodiment of the present invention includes: enabling a PSR active signal to be transmitted to a timing controller when a processed image is a still image in the system, transmitting an image of at least one frame to the timing controller, Wherein the timing controller stores in the remote frame buffer an image of at least one frame transmitted from the system when the PSR active signal is enabled and during a PSR active interval of the PSR active signal, A step of monitoring whether or not the system transmits data in units of frames during a PSR active period; and a step in which, during a PSR active period, a timing controller does not transmit data from the system to an interlace mode Operating the PSR active, During the interval, the timing controller includes operating in a progressive mode when data transfer from the system occurs.

The system further includes transmitting data of the selective update area requiring updating in the PSR active section to the timing controller together with positional information of the area. The timing controller detects whether or not data is transmitted from the system on a frame-by-frame basis in the PSR active section, updates the corresponding area of the remote frame buffer when the data of the selected area is transmitted from the system, and operates in the progressive mode.

In a display device of an electronic device according to an exemplary embodiment of the present invention, during a period in which no data is transmitted from the system during a PSR operation, the device operates in an interlace mode to reduce power consumption. In a period in which a selective update occurs, It is possible to prevent the display failure due to the defects.

The display device according to one embodiment can be applied to all display devices such as an OLED display, an LCD, a touch-sensitive display, and the like.

1 is a circuit block diagram schematically showing a configuration of an electronic device including a display device according to an embodiment of the present invention.
2 is a timing chart showing an input / output image frame of a timing controller according to an embodiment of the present invention and an input / output image frame according to a comparative example.
3 is a driving waveform diagram for a PSR active period of a timing controller according to an embodiment of the present invention.
4 is a flowchart illustrating a method of operating a PSR of a timing controller according to an exemplary embodiment of the present invention.
5 is a signal waveform diagram for a PSR operation period of a timing controller according to an embodiment of the present invention.
6 is a diagram illustrating a configuration of a display device using a built-in gate driver according to an embodiment of the present invention.
7 is a diagram showing a partial structure of a display device using a gate driving IC according to an embodiment of the present invention.
8 is a driving waveform diagram of a gate driving IC according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram schematically showing a configuration of an electronic device including a display device according to an embodiment of the present invention.

1, an electronic device includes a system 600 and a display device 500, and a display device 500 connected to the system 600 includes a panel 100, a gate driver 200, and a data driver 300, a timing controller 400, and the like.

The system controller 600 and the timing controller 400 of the display apparatus 500 transmit and receive data using a Display Port (DP) interface using an embedded Display Port (eDP) interface. The eDP interface transmits an image source in a unidirectional communication via a main link between a source device and a sink device and manages the sink in a bidirectional communication via an auxiliary link. Can be controlled. The system 600 corresponding to the source part of the eDP interface transmits the video source through the eDP transmission part TX and the timing controller 400 corresponding to the sink part of the eDP interface supplies the video source through the eDP reception part RX Take it.

The timing controller 400 and the data driver 300 in the display device 500 can transmit and receive data using the embedded point-to-point interface (EPI) to the transmission data. The timing controller 400 transmits the transmission data through the EPI transmission unit TX and the data driver 300 receives the transmission data through the EPI reception unit RX.

The system 600 performs necessary image processing, such as scaling, dithering, and the like, and transmits the image data stored in the internal memory to the timing controller 400 of the display device 500. The system 600 transmits a plurality of timing control signals including a clock, a data enable signal, a vertical synchronizing signal, a horizontal synchronizing signal, and the like to the timing controller 400 together with the image data, and outputs a PSR active signal to a timing controller (400). For example, system 600 may be a system of electronic devices such as notebook PCs, tablets, smart phones, all-in-one desktop PCs, and the like.

In order to reduce power consumption, the system 600 selectively enables the PSR mode of the display apparatus 500 according to whether the currently processed image is a still image. For example, the system 600 compares the processed images on a frame basis, and if the variation between neighboring frames is less than a predetermined threshold value, the system 600 determines the still image to enable the PSR mode of the display apparatus 500, It is determined that the video is a moving picture, and the PSR mode is disabled, and the video source is transmitted for each frame in the normal mode.

When the processed image is a still image, the system 600 transmits the PSR active signal to the timing controller 400 to enable the PSR mode and transmits the still image for at least one frame time, After the data is stored in the remote frame buffer, the transmitter is turned off to stop data transmission, so that power consumption can be reduced.

The system 600 determines that the PSR mode is maintained and the position information (line information) for the selective update (hereinafter, referred to as " SU " The data of the SU area is transmitted to the timing controller 400 so that the corresponding area of the remote frame buffer is updated with the data of the SU area through the timing controller 400. [ When transmitting the SU area in the PSR mode, the system 600 transmits the data of the SU area by turning on the transmitter only in a certain section transmitting the data of the SU area during the corresponding frame time, turns off the transmitter at the remaining time, do.

The timing controller 400 receives timing control signals and image data from the system 600. The timing control signals include a dot clock, a data enable signal, a vertical synchronization signal, and a horizontal synchronization signal. The timing controller 400 generates a plurality of data control signals for controlling the driving timing of the data driver 300 using the timing control signals supplied from the system 600 and the setting information stored therein, And generates a plurality of gate control signals for controlling the driving timing of the gate driver 200 and transmits them to the gate driver 400. [

The timing controller 400 performs various image processing such as luminance correction, image quality correction, and the like for reducing power consumption of the image data supplied from the system 600, and transmits the image-processed data to the data driver 300.

When the PSR active signal transmitted from the system 600 is enabled, the timing controller 400 stores a still image of one frame transmitted from the system 600 in the remote frame buffer, and then stores the still image in the remote frame buffer during the PSR active period And transmits the image data to the data driver 300. Meanwhile, when the PSR active signal transmitted from the system 600 is disabled, the timing controller 400 stops the PSR operation, processes the image source transmitted from the system 600, and transmits the processed image source to the data driver 300.

In particular, the timing controller 400 detects whether the video data is transmitted through the main link from the system 600 during the PSR active period, on a frame-by-frame basis, and selects either the interlace mode or the progressive mode It operates in one mode. During the PSR active period, the timing controller 400 operates in the interlace mode if the video data is not transmitted through the main link, and operates in the progressive mode when the video data is transmitted for updating the SU area. On the other hand, when the PSR mode is disabled, the timing controller 400 operates in the progressive mode.

In the interlace mode in the PSR active period, the timing controller 400 supplies the image of one frame stored in the remote frame buffer separately to the odd frame driving the od horizontal lines and the even frame driving the even horizontal lines, The gate driver 200 and the data driver 300 are controlled such that an image of one frame is displayed on the panel 100 for a predetermined period of time.

In the progressive mode in the PSR active period, the timing controller 400 supplies an image of one frame stored in the remote frame buffer for one frame, so that a still image of one frame is displayed on the panel 100 for each frame 200 and the data driver 300. [

The gate driver 200 receives a plurality of gate control signals from the timing controller 400 and performs a shift operation to individually drive the gate lines of the panel 100. [ The gate driver 200 supplies a scan signal of a gate-on voltage (gate high voltage) to the corresponding gate line in the driving period of each gate line, and applies a gate-off voltage (gate low voltage) Gate line.

The gate driver 200 operates in either the interlaced mode or the progressive mode under the control of the timing controller 400.

In the case of operating in the progressive mode under the control of the timing controller 400, the gate driver 200 sequentially drives all the gate lines in each frame.

When operating in the interlace mode under the control of the timing controller 400, the gate driver 200 sequentially drives the odd gate lines in the odd frame and sequentially drives the even gate lines in the even frame. When operating in the interlace mode, the gate driver 200 sequentially drives the odd gate lines in a half of the odd frame time according to the control of the timing controller 400, The driving is turned off, the even gate lines are sequentially driven only for 1/2 of the even frame time, and the driving of all the gate lines is turned off for the remaining 1/2 time, thereby reducing power consumption.

The gate driver 200 according to an embodiment includes one or a plurality of gate driving integrated circuits (ICs), and gate driving ICs are individually mounted on circuit films such as COF (Chip On Film) Bonded by TAB (Tape Automatic Bonding) method, or mounted on the panel 100 by a COG (Chip On Glass) method. Each of the gate driving ICs constituting the gate driver 200 receives a plurality of gate control signals from the timing controller 400 and performs a shift operation to drive the gate lines.

The gate driver 200 according to one embodiment is formed on the substrate together with the thin film transistor array constituting the pixel array of the panel 100 to form a GIP (Gate) gate on the non-display region on both sides or one side of the panel 100. [ In Panel) type. The gate driver 200 of the GIP type receives a plurality of gate control signals through a level shifter (not shown) controlled by the timing controller 400 and performs a shift operation to drive the gate lines.

The data driver 300 is controlled in accordance with a data control signal supplied from the timing controller 400 and converts the digital pixel data supplied from the timing controller 400 into an analog data signal to be supplied to the data lines of the panel 100 do. At this time, the data driver 300 converts the digital pixel data into an analog data signal using the gradation voltages obtained by subdividing the plurality of reference gamma voltages supplied from the gamma voltage generator (not shown) As shown in FIG.

The data driver 300 operates in either the interlaced mode or the progressive mode under the control of the timing controller 400. [

In the case where the data driver 300 operates in the progressive mode under the control of the timing controller 400, each time the gate lines are driven by the gate driver 200 in each frame, .

When operating in the interlace mode under the control of the timing controller 400, each time the odd gate line is driven by the gate driver 200 in the odd frame, the data driver 300 supplies the video data of the odd horizontal line to the data lines And outputs video data of the even horizontal lines to the data lines every time the even gate lines are driven by the gate driver 200 in the even frame. When operating in the interlace mode, the data driver 300 outputs image data for od horizontal lines only for 1/2 hour of the odd frame time under the control of the timing controller 400, Power consumption can be reduced by turning off the output, outputting the image data for the even horizontal lines only at 1/2 of the even frame time, and turning off the data output for the remaining 1/2 hour.

The data driver 300 includes a plurality of data driving ICs. Data driving ICs are individually mounted on a circuit film such as a chip on film (COF) or the like and bonded to the panel 100 by TAB (Tape Automatic Bonding) And may be mounted on the panel 100 by a COG (Chip On Glass) method.

The panel 100 displays an image through a pixel array in which subpixels connected to gate lines and data lines are arranged in a matrix form. The basic pixel can be composed of at least three subpixels capable of white representation by color mixing among white (W), red (R), green (G) and blue (B) subpixels. For example, the basic pixel may be composed of subpixels of R / G / B combination, or of W / R / G / B combination. The basic pixel can be composed of subpixels of R / G / B combination, subpixels of W / R / G combination, subpixels of B / W / R combination, have.

The panel 100 may be various display panels such as an LCD panel, an OLED panel, and the like, or may be a touch-compatible display panel having a touch sensing function.

When the panel 100 is an OLED panel, the data driver 300 controls the electrical characteristics (threshold voltage and mobility of the driving TFT, threshold voltage of the OLED element, etc.) of each subpixel under the control of the timing controller 400 Sensing the current represented by the current or voltage, converting the sensed current into digital sensing data, and supplying the sensed data to the timing controller 400. [ The timing controller 400 updates the compensation value of each subpixel using the sensing data of each subpixel supplied from the data driver 300 and performs data processing for compensating each pixel data by applying the compensation value It is possible to compensate for the luminance unevenness due to the characteristic difference between the subpixels.

2 is a timing chart showing an input / output image frame of a timing controller according to an embodiment of the present invention and an input / output image frame of a timing controller according to a comparative example.

2 (A) and 2 (B), during a period during which the PSR active signal is disabled, the timing controller according to the comparative example and the timing controller 400 according to an embodiment operate in the progressive mode, (N, N + 1) transmitted from the image processor 600 through the eDP receiver RX and transmits the image N to the data driver 300 through the EPI transmitter TX.

Referring to FIG. 2 (A), during the active period in which the PSR active signal is enabled, the timing controller according to the comparative example stores the image of the (N + 2) frame in the first frame time F1 in the resume frame buffer The image data of the N + 2 frame stored in the remote frame buffer is divided into the odd frame and the even frame by the EPI transmitting unit TX and then the interleaved mode from the second frame time F2. And transmits it to the data driver. (SU1, SU2, SU3) of the N + 3, N + 4, and N + 5 frames from the system are transmitted to the eDP receiving unit RX from the system during the fourth to sixth frame times F4 to F6 of the PSR active period, The timing controller updates the corresponding area of the remote frame buffer to the SU areas SU1, SU2 and SU3 of N + 3, N + 4 and N + 5 frames while operating in the interlace mode, Reads data of the odd lines of the (N + 2) -th frame at time F4, transmits the data of the odd lines of the (N + 2) -th frame to the data driver via the EPI transmitter TX, , And the odd lines of the (N + 4) th frame are read and transmitted at the sixth frame time F6. Accordingly, the odd lines of the (N + 2) -th frame and the even lines of the (N + 3) -th frame are mixed and displayed as a full frame at the fourth and fifth frame times F4 and F5, The odd lines of the (N + 4) -th frame and the even lines of the (N + 5) -th frame are mixed in the frames F6 and F7.

Referring to FIG. 2B, the timing controller 400 according to an exemplary embodiment of the present invention controls the interlace mode when the image is not supplied from the system 600 through the eDP receiver RX among the active periods of the PSR active signal. (SU1, SU2, SU3) of the SU region of the N + 3, N + 4, and N + 5 frames during the fourth through sixth frames F4 through F6 through the eDP receiving unit RX If it is supplied, the corresponding area of the remote frame buffer is updated. At least the fifth to seventh frame times F5 to F7 operate in the progressive mode, and if the image is not supplied through the eDP receiver RX, the interlaced mode is operated again . At this time, in the PSR active period, when the timing controller 400 switches from the progressive mode to the interlaced mode, at least one frame or more can be switched to the progressive mode and then to the interlaced mode.

Accordingly, the panel 100 displays the N + 3, N + 4, and N + 5 frames in which the SU area has been updated during the fifth to seventh frame times F5 to F7 as full frames, Display failure due to the interlace operation can be prevented.

3 is a driving waveform diagram for a PSR active period of a timing controller according to an embodiment of the present invention.

3, in the active period of the PSR active signal, the timing controller 400 determines whether image data is transmitted from the eDP transmitting unit TX of the system 600 to the eDP receiving unit RX via the main link, And operates in either the interlace mode or the progressive mode according to the detection result. The eDP transmitter TX of the system 600 is turned off when not transmitting image data.

If the video data is not supplied from the system 600 in the PSR active period, the timing controller 400 operates in the interlace mode, and in the 1/2 period of the internal vertical data enable period (V-DE) at each frame time, The odd data of the even lines or odd data of the odd lines from the frame buffer is read and transmitted through the EPI transmitting unit TX and the EPI transmitting unit TX can stop the data transmission for the remaining 1/2 period, The power consumption of the data driver 200 and the data driver 300 can be further reduced.

In the PSR active period, when data of the SU area (SU1, SU2, SU3) is transmitted from the system 600, the timing controller 400 updates the corresponding SU area of the remote frame buffer and switches from the next frame time to the progressive mode And reads video data of one frame of the remote frame buffer during the internal vertical data enable period (V-DE) at each frame time, and transmits the read video data through the EPI transmission unit (TX).

The timing controller 400 uses a delay using a register to prevent a collision between a read operation of a remote frame buffer for EPI transmission and a write operation of a remote frame buffer for updating an SU area for display, The address order can be delayed. Since the line information is included in the data of the SU area (SU1, SU2, SU3) transmitted from the system 600, the timing controller 400 delays the read address sequence by using the line information of the SU area Light and lead collision can be prevented.

In the PSR active period, when the timing controller 400 operates in the progressive mode to update the SU area and the video data is not supplied from the system 600 during N (N is a natural number) frame, do. The N frame becomes at least one frame and can be changed through the setting of the timing controller 400 according to the driving environment.

FIG. 4 is a flowchart showing a method of operating a PSR of a timing controller according to an embodiment of the present invention, and FIG. 5 is a signal waveform diagram of a PSR operation period of the timing controller shown in FIG. FIG. 4 illustrates a method of operation for the active period in which the PSR active signal is enabled in FIG.

Referring to FIG. 5, the timing controller 400 operates in the progressive mode during a period in which the PSR active signal is disabled after the power source VCC is turned on. Then, the timing controller 400 receives the image transmitted from the system 600, And transmits the processed data to the data driver 300. The timing controller 400 outputs a gate start pulse (GSP) signal for each frame to the gate driver 200 and the data driver 300 to notify the start timing of each frame. The timing controller 400 enables the progressive signal when operating in the progressive mode, enables the interlace mode signal when operating in the interlace mode, and outputs the progressive signal and the interlace signal to the data driver 300 and gate driver 400, So that the data driver 300 and the gate driver 400 can be controlled.

4 and 5, if the PSR active signal is enabled (S402; Y) under the control of the system 600, the timing controller 400 controls the system 600 to operate in the progressive mode for at least one frame time, In the remote frame buffer and transmits the frame image to the data driver 300 (S404).

When the data is transmitted from the system 600 (Y in step S406), the timing controller 400 updates the remote mode frame buffer and initializes the frame count (Frame_Count = 0) (S408) (Operation S410).

On the other hand, if no data is transmitted from the system 600 in the next frame (S406; N), the timing controller 400 operates in the progressive mode in the next frame (S414) and increases the frame count (Frame_Count + 1) (S416).

If the timing controller 400 determines that the frame count is smaller than 2 (N in step S418), the process proceeds to step S406 and if no data is transmitted from the system 600 (S406; N), the above-described steps S414 and S416 Repeat the step and increase the frame count further (Frame_Count + 1).

Accordingly, if the frame count is determined to be 2 or more in step S418, the timing controller 400 switches from the next frame to the interlaced mode and operates (S420). Thereafter, data is transmitted from the system 600 on a frame- (S422).

If the data is not transmitted from the system 600 in step S422, the timing controller 400 repeats steps S420 and S422 to check whether data is received on a frame-by-frame basis while operating in the interlace mode.

On the other hand, if data (i.e., data in the SU area) is transferred from the system 600 in step S422 (Y), the process proceeds to step S408 to write the data in the SU area to the remote frame buffer and update the frame number to initialize the frame count , And operates in the progressive mode (S410).

Then, if the data of the SU area is transmitted from the system 600 (Y), steps S408 and S410 are repeated, while checking whether data is received on a frame-by-frame basis in step S408.

On the other hand, if no data is transmitted from the system 600 in step S406, the timing controller 400 repeats the above-described steps S414 to S418 to further operate in the progressive mode before the frame count becomes 2, If the frame count is equal to or greater than 2 (Y) in step S418, the interlace mode operation is performed (S420). Then, it is checked whether data is transmitted from the system 600 on a frame-by-frame basis (S422) And operates in either a progressive mode or an interlace mode while repeating one operation.

Accordingly, the timing controller 400 according to the embodiment can operate in the interlace mode during the PSR active period without data transmission from the system, thereby reducing power consumption. In the period in which the selective update occurs, the progressive mode It is possible to prevent display failure due to interlace driving.

6 is a diagram illustrating a configuration of a display device using a built-in gate driver according to an embodiment of the present invention.

Referring to FIG. 6, GIP-type first and second gate drivers 210 and 220 are mounted on both sides of the panel 100. The first gate driver 210 built in one side of the panel 100 receives a plurality of gate control signals from the first level shifter LS1 controlled by the timing controller 400 and supplies the gate lines GL1, GL3, ..., GLn-1. The second gate driver 220 built in the other side of the panel 100 receives the plurality of gate control signals from the second level shifter LS2 controlled by the timing controller 400, GL4, ..., GLn.

Each of the first and second level shifters LS1 and LS2 generates a plurality of gate control signals under the control of the timing controller 400 to control the first and second gate drivers 210 and 220, respectively. The first level shifter LS1 receives first control signals from the timing controller 400 and performs logic processing and level shifting to generate first gate control signals and supplies the first gate control signals to the first gate driver 210, (LS2) receives the second control signals from the timing controller 400 and performs logic processing and level shifting to generate second gate control signals and supplies the second gate control signals to the second gate driver 220. [

The first and second gate drivers 210 and 220 are controlled by the first and second level shifters LS1 and LS2 to operate in the first and second level shifters 210 and 220 in the progressive mode under the control of the timing controller 400. [ Th to n < th > gate lines GL1 to GLn.

The first gate driver 210 in the odd frame controls the odd gate lines GL1 and GL2 according to the control of the first and second level shifters LS1 and LS2 when operating in the interlace mode under the control of the timing controller 400. [ The second gate driver 220 sequentially drives the even gate lines GL2, GL4, ..., and GLn in the even frame.

While the first gate driver 210 drives the odd gate lines GL1, GL3, ..., GLn-1 in a part of the odd frame operating in the interlace mode, the second gate driver 220 drives the odd- Do not drive the lines GL2, GL4, ..., and GLn. The first and second gate drivers 210 and 220 may not drive the gate lines GL1 to GLn during the rest of the odd frame.

The first gate driver 210 drives the even gate lines GL2, GL4, ..., GLn while the second gate driver 220 drives some of the even frames in the interlace mode, (GL1, GL3, ..., GLn-1). The first and second gate drivers 210 and 220 may not drive the gate lines GL1 to GLn during the rest of the even frame.

7 is a diagram showing a part of a configuration of a display device using a gate driving IC according to an embodiment of the present invention, and FIG. 8 is a driving waveform diagram of the gate driving IC shown in FIG.

Referring to Fig. 7, one or a plurality of gate driving ICs (GDIC) are connected to one side of the panel 100. Fig. The gate driving IC GDIC receives a plurality of gate control signals GSP, GSC and GOE from the timing controller 400 and drives the gate lines GL1 to GLn. The gate driving IC GDIC starts operation according to the gate start pulse GSP supplied from the timing controller 400 and performs a shift operation according to the gate shift clock GSC to output a scan signal for driving each gate line , The output period of the scan signal is determined according to the gate output enable signal GOE. The gate drive IC (GDIC) operates in the progressive mode or the interlace mode under the control of the timing controller (400).

The gate driver IC GDIC shifts the gate lines GL1 to GLn to the horizontal periods H1, H2, H3, and H4 for each frame when the timing controller 400 operates in the progressive mode, , ...) and the scan signal is applied to the corresponding gate line during the enable period of the first gate output enable signal GOE1 in each of the horizontal periods H1, H2, H3, H4, ... .

When operating in the interlace mode under the control of the timing controller 400, the gate drive IC GDIC performs a shift operation for each frame, and in the odd frame, by masking the second gate output enable signal GOE2, Only the lines GL1, GL3, ... are driven and the even gate lines GL2, GL4, ... are not driven. In the even frame, by masking the second gate output enable signal GOE2, Only the gate lines GL2, GL4, ... are driven and the odd gate lines GL1, GL3, ... are not driven.

As described above, in the display device of the electronic device according to the embodiment, during the PSR active period, the section without data transmission from the system operates in the interlace mode to reduce the power consumption. In the section where the selective update occurs, Mode, it is possible to prevent display failure due to interlace driving.

One embodiment may be applied to all display devices such as OLED displays, LCDs, touch-sensitive displays, and the like.

The foregoing description is merely illustrative of the present invention, and various modifications may be made by those skilled in the art without departing from the spirit of the present invention. Accordingly, the embodiments disclosed in the specification of the present invention are not intended to limit the present invention. It is intended that the scope of the invention be interpreted by the claims appended hereto, and that all techniques within the scope of equivalents thereof should be construed as being included within the scope of the present invention.

100: panel 200: gate driver
300: Data driver 400: Timing controller
500: Display device 600: System

Claims (10)

A system for enabling a panel self-refresh (hereinafter referred to as PSR) operation of a display apparatus when a processed image is a still image, transmitting a still image of at least one frame to the display apparatus,
Wherein when the PSR operation is enabled according to the control of the system, the at least one frame of still image transmitted from the system is stored in the remote frame buffer, and the image stored in the remote frame buffer in the active period of the PSR operation is transmitted to the panel And a display device for displaying the image on the display device,
Wherein the display device monitors whether or not data is transferred from the system during an active period of the PSR operation, and the section without the data transfer from the system operates in an interlace mode, and when the data transfer occurs from the system, And updates the corresponding area of the remote frame buffer with data transmitted from the system and operates in a progressive mode. The method according to claim 1,
The system transmits a PSR active signal for enabling the PSR operation to the timing controller of the display device and transmits the data of the selective update area requiring updating in the PSR active section of the PSR active signal to the timing controller Controller,
Wherein the timing controller performs the PSR operation in response to the PSR active signal and monitors whether or not the system transmits data in units of frames in the PSR active period so that the section without data transmission operates in the interlace mode, Updates the corresponding area of the remote frame buffer with the data of the selective update area transmitted from the system when the data transmission occurs, and operates in the progressive mode. The method of claim 2,
The timing controller
Operating in the progressive mode and operating in the interlace mode while storing an image transmitted from the system for at least one frame after the PSR active signal is enabled in the re-
Wherein when the data transmission from the system is detected in the PSR active period, the apparatus operates in the progressive mode,
Further operating in the progressive mode in the PSR active period and further in the progressive mode for at least one frame if the data transmission from the system is not detected after switching from the system to the interlaced mode. The method of claim 3,
The timing controller, during the PSR active period,
Initialize a frame count when the data transmission from the system is detected,
Increasing the frame count if the data transmission from the system is not detected,
And operates in the progressive mode if the frame count is less than a preset reference value, and operates in the interlace mode if the frame count is greater than or equal to the reference value. The method of claim 3,
Wherein the timing controller operating in the interlace mode comprises:
Data of the odd lines of the video stored in the remote frame buffer is read and transmitted to the data driver during a part of the odd frame, and data transmission is stopped by the data driver during the remaining period of the odd frame,
Read data of the stored video in a part of the even frame and transmit the read data to the data driver and stop the data transmission in the remaining part of the even frame. The method of claim 5,
Wherein the timing controller operating in the interlace mode comprises:
Controls the data driver so that the data driver outputs data transmitted from the timing controller only during the part of each of the odd frame and the even frame and stops outputting data in the remaining period. The method of claim 5,
The timing controller operating in the interlace mode controls the gate driver,
Driving odd gate lines only during a part of the odd frame,
And drives the even gate lines only for a part of the even frame. The method of claim 7,
The gate driver
And a controller which is incorporated in the panel and operates in the interlace mode or the progressive mode under the control of a level shifter controlled by the timing controller,
And a gate driving IC, and operates in the interlace mode or the progressive mode under the control of the timing controller. The method comprising the steps of: enabling a PSR active signal to be transmitted to a timing controller when a processed image is a still image in a system, transmitting an image of at least one frame to the timing controller and then stopping data transmission;
If the PSR active signal is enabled, the timing controller stores an image of the at least one frame transmitted from the system in a remote frame buffer;
During a PSR active period of the PSR active signal, the timing controller displays an image stored in the remote frame buffer on a panel,
Wherein the timing controller of the PSR active period monitors whether the system transmits data in units of frames,
Wherein, in the PSR active period, the timing controller operates in an interlace mode in a section where there is no data transmission from the system,
Wherein during the PSR active period, the timing controller operates in a progressive mode when data transfer from the system occurs. The method of claim 9,
Wherein the system further comprises the step of transmitting, in the PSR active section, the data of the selective update area requiring updating to the timing controller together with the location information of the area,
Wherein the timing controller updates the corresponding area of the remote frame buffer and operates in the progressive mode when the data of the selected area is transmitted from the system in the PSR active period.

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