KR101957738B1 - Image display device and method of fabricating the same - Google Patents

Abstract

The present invention relates to an image display apparatus and a method of manufacturing the same, the image display apparatus comprising: a display panel for displaying an image; A plurality of gate wirings and a plurality of data wirings formed on the display panel and defining a plurality of sub-pixel regions crossing each other, and a plurality of connection wirings; And a driving driver including a plurality of driving driver ICs for supplying a gate signal or a data signal for driving the display panel, wherein the gate wiring extends in a first direction and is spaced apart from and spaced apart from the data line and parallel to the data line The connection wiring extends in a second direction and is connected to the gate wiring to transmit the gate signal to the sub-pixel region.

Description

TECHNICAL FIELD [0001] The present invention relates to an image display apparatus and a method of manufacturing the same.

The present invention relates to a video display device and a method of manufacturing the same, and more particularly, to a video display device and a method of manufacturing the same. More particularly, the present invention relates to a video display device and a method of manufacturing the same, The present invention relates to a video display device and a method of manufacturing the same that can improve a line dim phenomenon due to a difference in the number of gates and data output terminals of a video display device.

2. Description of the Related Art [0002] With the development of information society in recent years, demands for the display field have been increasing in various forms. In response to this demand, various flat panel display devices having characteristics such as thinning, light weight and low power consumption have been developed, A liquid crystal display device, a plasma display panel device, and an organic light emitting diode display device have been studied.

FIG. 1 is a view schematically showing a general image display apparatus, and FIG. 2 is a view schematically showing a general liquid crystal panel.

As shown in Fig. 1, the video display device includes a display panel 10 for displaying video, a source driver, a gate driver, and a timing controller (not shown).

2, the display panel 10 is provided with a plurality of gate lines G1, G2, G3, G4, G5, .., which intersect each other to define a plurality of sub- D1, D2, D3, D4, D5, ...) may be formed.

The plurality of sub-pixel regions may be, for example, red, green, and blue sub-pixel regions, and may be sequentially arranged in the horizontal direction (horizontal direction).

The first sub-pixel region is connected to a plurality of gate lines G1, G2, G3, G4, G5, ... and a plurality of data lines D1, D2, D3, D4, D5, And the second thin film transistors T1 and T2 may be formed.

Here, the sub-pixel region including the first thin film transistor T1 can receive the data signal through the data line on the left side, and the sub-pixel region including the second thin film transistor T2 can be supplied through the data line on the right side The data signal can be received.

For example, the first thin film transistor T1 connected to the first gate line G1 can receive a data signal through the data line on the left side.

The second thin film transistor T2 connected to the second gate line G2 can receive the data signal through the data line on the right side.

The gate signal is first supplied through the gate lines G1, G2, G3, G4, G5, ... so that the first and second thin film transistors T1 and T2 are turned on When turned on, the data signal supplied through the data lines D1, D2, D3, D4, D5, ... is transferred to the storage capacitor.

The storage capacitor holds the data signal for one frame to maintain the gradation displayed by the image display device constant.

The source driver includes a plurality of source driver ICs 11. The source driver 11 generates a data signal by using the converted image data and a plurality of data control signals transmitted from the timing controller and outputs the generated data signal to the respective sub- Supply.

The gate driver includes a plurality of gate driver ICs 12. The gate driver generates a gate signal by using a plurality of gate control signals transmitted from the timing controller and supplies the generated gate signal to a plurality of gate lines GL1, To the respective sub-pixel regions.

Here, the gate control signal may include a gate start pulse, a gate shift clock, a gate output enable signal, and the like.

The timing control unit receives a plurality of video signals, a vertical synchronizing signal (Vsync), a horizontal synchronizing signal (Hsync), and a data enable signal (DE) from a system such as a graphic card through an LVDS (Low Voltage Differential Signal) A plurality of control signals can be received.

The timing control unit may generate a gate control signal for controlling the gate driver and a data control signal for controlling the source driver using a plurality of control signals.

Although not shown, the apparatus may further include a power supply unit (not shown) for generating and supplying a driving voltage for driving the components of the image display apparatus using a power supply voltage received from the outside.

In such a video display device, left and right panel bezel portions for attaching the gate driver ICs on both sides of the display panel are formed, thereby causing a problem that the width (bezel) of both sides of the display panel is increased.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to reduce the number of bezels of a display panel by applying a multi-drive driver IC and a vertical gate wiring, And it is an object of the present invention to provide an image display apparatus and a method of manufacturing the same that can improve a line dim phenomenon due to a difference in the number of output terminals.

According to an aspect of the present invention, there is provided an image display apparatus including: a display panel for displaying an image; A plurality of gate wirings and a plurality of data wirings formed on the display panel and defining a plurality of sub-pixel regions crossing each other, and a plurality of connection wirings; And a driving driver including a plurality of driving driver ICs for supplying a gate signal or a data signal for driving the display panel, wherein the gate wiring extends in a first direction and is spaced apart from and spaced apart from the data line and parallel to the data line The connection wiring extends in a second direction and is connected to the gate wiring to transmit the gate signal to the sub-pixel region.

Here, the gate wiring may be divided into a general gate wiring for transferring the gate signal and a dummy gate wiring for transferring the gate signal.

The driving driver IC includes: a shift register unit for shifting output of a flip-flop by a plurality of gate control signals; A level shift unit which receives the gate high voltage and the gate low voltage and shifts each output level; And an output buffer unit including a plurality of output terminals connected to the gate wiring and transmitting the gate signal transferred from the level shifting unit to the display panel, And a dummy output terminal that does not transmit the gate signal.

The general output terminal may be connected to the common gate line, and the dummy output terminal may not be connected to the dummy gate line.

On the other hand, the general output terminal may be connected to the common gate line, and the dummy output terminal may be connected to the dummy gate line.

At this time, it is preferable that a low potential voltage terminal or a gate low voltage terminal is connected to the dummy output terminal, and the low potential voltage or the gate low voltage is transmitted to the display panel through the dummy output terminal.

The first thin film transistor receives the data signal through a left data line of the sub pixel region, and the second thin film transistor includes a first thin film transistor The data signal can be received through the right data line of the sub pixel area.

According to an aspect of the present invention, there is provided a method of manufacturing an image display device including a plurality of gate lines and a plurality of data lines crossing each other and defining a plurality of sub- The method comprising the steps of: And connecting a plurality of driving driver ICs for supplying a gate signal or a data signal for driving the display panel to the display panel, wherein the gate wirings extend in a first direction and are spaced apart from each other, And the connection wirings extend in a second direction and are connected to the gate wirings to transfer the gate signal to the sub-pixel region.

Here, the gate wiring may be divided into a general gate wiring for transferring the gate signal and a dummy gate wiring for transferring the gate signal.

The driving driver IC includes: a shift register unit for shifting output of a flip-flop by a plurality of gate control signals; A level shift unit which receives the gate high voltage and the gate low voltage and shifts each output level; And an output buffer unit including a plurality of output terminals connected to the gate wiring and transmitting the gate signal transferred from the level shifting unit to the display panel, A general output terminal or a dummy output terminal which does not transmit the gate signal.

At this time, the general output terminal may be connected to the common gate line, and the dummy output terminal may not be connected to the dummy gate line.

On the other hand, the general output terminal may be connected to the common gate line, and the dummy output terminal may be connected to the dummy gate line.

The low output voltage terminal or the gate low voltage terminal is connected to the dummy output terminal, and the low output voltage or the gate low voltage is transmitted to the display panel through the dummy output terminal.

The first thin film transistor receives the data signal through a data line on the left side of the sub pixel region, and the second thin film transistor includes a first thin film transistor The data signal can be received through the right data line of the sub pixel area.

As described above, in the video display device and the manufacturing method thereof according to the present invention, the bezel of the display panel can be reduced by applying the multi-drive driver IC and the vertical gate wiring.

Through the connection between the dummy gate wiring and the dummy output terminal, the line dim phenomenon due to the difference in the number of gates and data output terminals of the display panel can be improved.

1 is a view schematically showing a general video display device.
2 is a view schematically showing a general liquid crystal panel.
3 is a schematic view illustrating an image display apparatus according to an embodiment of the present invention.
4 is a view schematically showing a display panel according to the first embodiment of the present invention.
5 is a view schematically showing a gate driver IC according to the first embodiment of the present invention.
6 is a diagram referred to explain the rhythm phenomenon of the display panel according to the first embodiment of the present invention.
7 is a view schematically showing a display panel according to a second embodiment of the present invention.
8 and 9 are views schematically showing a gate driver IC according to a second embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 3 is a view schematically showing an image display apparatus according to an embodiment of the present invention, and FIG. 4 is a view schematically showing a display panel according to the first embodiment of the present invention.

As shown in FIG. 3, the video display device according to the embodiment of the present invention includes a display panel 100 for displaying an image, a driving driver, a timing controller (not shown), and the like.

A plurality of gate lines G1, G2, G3, G4, G5, G6, G7, ... and a plurality of data lines D1, D2, D3, D4 A plurality of connection wirings C1, C2, C3, C4, C5, C6, C7, C8, etc. may be formed.

Here, the plurality of sub-pixel regions may be, for example, red, green, and blue sub-pixel regions, and may be sequentially arranged in the horizontal direction (horizontal direction).

In the display panel 100, pixel regions including red, green, and blue pixel regions may be arranged in a matrix of M * N (where M and N are arbitrary natural numbers).

The plurality of gate wirings G1, G2, G3, G4, G5, G6, G7, ... and the plurality of data wirings D1, D2, D3, D4, D5, D6, D7, Extend in one direction (vertical direction), spaced apart from each other, and formed parallel to each other.

The plurality of gate wirings G1, G2, G3, G4, G5, G6, G7, ... and the plurality of data wirings D1, D2, D3, D4, D5, D6, D7, The first gate wiring G1, the first data wiring D1, the second gate wiring G2, the second data wiring D2, and the like are sequentially alternately formed in the second direction (horizontal direction) .

The plurality of gate lines G1, G2, G3, G4, G5, G6, G7 and the plurality of data lines D1, D2, D3, D4, D5, D6, D7, However, the present invention is not limited thereto and two gate wirings may be formed per three data lines.

For example, the first gate wiring G1, the first data wiring D1, the second data wiring D2, the second gate wiring G2, and the third data wiring D3 (in the horizontal direction) ) Can be sequentially formed for each three data wirings.

The plurality of gate wirings G1, G2, G3, G4, G5, G6, G7, ... and the plurality of gate wirings C1, C2, C3, C4, C5, C6, A plurality of sub-pixel regions can be defined by intersecting the plurality of data lines D1, D2, D3, D4, D5, D6, D7,.

The plurality of connection wirings C1, C2, C3, C4, C5, C6, C7, C8, ... extend in a second direction (horizontal direction) and are connected to gate wirings, And transmits the gate signal to the respective sub-pixel regions.

A part of the gate wirings, for example, the fifth to seventh gate wirings G5, G6, G7, among the plurality of the plurality of gate wirings G1, G2, G3, G4, G5, G6, G7, And may not be connected to the fifth through seventh connection wirings C5, C6, and C7.

More specifically, in the display panel 100, pixel regions including red, green, and blue pixel regions may be arranged in a matrix form of M * N (where M and N are arbitrary natural numbers) (M> N The dummy gate wirings G5, G6 and G7 can be formed between the data wirings because the number of gate output terminals and the number of data output terminals of the drive driver IC are different.

The dummy gate lines G5, G6, and G7 may not be connected to the output terminals of the driving driver. (No Connected)

And a plurality of data lines D1, D2, D3, D4, D5, D6, ..., and a plurality of data lines D1, D2, D7, ..., or the like may be formed on the first and second thin film transistors T1 and T2.

Here, the sub-pixel region including the first thin film transistor T1 can receive the data signal through the data line on the left side, and the sub-pixel region including the second thin film transistor T2 can be supplied through the data line on the right side The data signal can be received.

For example, the first thin film transistor T1 connected to the first connection wiring C1 can receive a data signal through the data line D1 on the left side.

The second thin film transistor T2 connected to the second connection wiring C2 can receive the data signal through the data line D1 on the right side.

That is, the first thin film transistor T1 and the second thin film transistor T2 share the same data line and can receive the data signal as they are turned on by the gate signal, respectively.

When driving the sub-pixel region of the image display apparatus, if the gate signals supplied through the gate wiring are first transmitted to the first and second thin film transistors T1 and T2 through the plurality of connection wirings, The thin film transistors T1 and T2 are turned on so that data signals supplied through the plurality of data lines D1, D2, D3, D4, D5, D6, D7, ... are transferred to the storage capacitor do.

The storage capacitor holds the data signal for one frame to maintain the gradation displayed by the image display device constant.

Referring again to FIG. 3, the driving driver includes a plurality of driving driver ICs 110, which may be a multi-driving driver IC including a plurality of source driver ICs and a plurality of gate driver ICs.

The driving driver converts the converted converted video signal received from the timing controller into a data signal using a driver IC control signal such as a source start pulse SSP, a source sampling clock SSC, a source output enable SOE, And to supply the generated data signal to the display panel 100. [

The driving driver generates a gate signal using a plurality of gate control signals transmitted from the timing control unit and controls the generated gate signal to be supplied to the display panel 100 through a plurality of gate lines and a plurality of connection lines Can

Here, the gate control signal may include a gate start pulse, a gate shift clock, a gate output enable signal, and the like.

The timing control unit receives a plurality of video signals, a vertical synchronizing signal (Vsync), a horizontal synchronizing signal (Hsync), and a data enable signal (DE) from a system such as a graphic card through an LVDS (Low Voltage Differential Signal) A plurality of control signals can be received.

The timing control unit may generate a gate control signal and a data control signal for controlling the driving driver by using a plurality of control signals.

The low voltage differential signal (LVDS) interface includes an LVDS transmitter (not shown) for converting a plurality of video signals and a plurality of control signals received from the system into LVDS signals and delivering them to the LVDS transmitter And an LVDS receiving unit (not shown) for receiving a plurality of converted N-bit video signals and a plurality of control signals.

Here, the LVDS transmission unit may be embedded in the system, and the LVDS reception unit may be incorporated in the timing control unit.

The gamma voltage generating circuit may further include a gamma voltage generating circuit (not shown) and a power supply circuit (not shown). The gamma voltage generating circuit divides the high voltage and the low voltage to generate a plurality of gamma voltages, It can be supplied to the driving driver.

The power supply circuit can generate and supply a driving voltage for driving the components of the video display device using the power supply voltage received from the outside.

In the present invention, by applying a plurality of driving driver ICs, the left and right panel bezel portions for attaching the gate driver ICs on both sides of the display panel can be removed. As a result, the bezels on both sides of the display panel are reduced, Bezel) can be implemented.

Further, in the present invention, since the gate wiring formed in the left and right panel bezel portions is formed in the form of a vertical gate wiring in the inside (display region) of the display panel, the space required for forming the gate wiring in the left and right panel bezel portions Can be further reduced, and the narrow bezel can be implemented more effectively.

In addition, in order to compensate for the reduction of the aperture ratio due to the formation of the vertical gate wiring extending in the first direction, the DRD driving for driving two vertical lines using one data line can be applied.

As a result of applying DRD drive in this manner, the number of data lines required for general driving is reduced to a half of that of the number of data lines, so that even when vertical gate lines are formed, the reduction of the aperture ratio can be reduced.

That is, by applying the DRD driving, the vertical gate wiring can be formed in the data wiring region to be removed as the data wiring is reduced compared with the conventional one, and the reduction of the aperture ratio can be reduced.

5 is a view schematically showing a gate driver IC according to the first embodiment of the present invention. 3 and Fig. 4. Fig.

As shown in FIG. 5, the plurality of gate driver ICs may include a shift register unit, a level shift unit (L / S), and an output buffer unit (BUF).

The shift register unit includes a flip-flop (F / F) and the like. The shift register unit can shift each output by the gate start pulse GSP and the gate shift clock GSC to transfer the output to the level shift unit L / S.

The level shifter L / S receives the gate high voltage VGH and the gate low voltage VGL and can shift each output level.

The output buffer unit BUF includes a plurality of output terminals OUT1, OUT2, OUT3, OUT4, ... connected to a plurality of gate wirings and receives the gate signal transmitted from the level shift unit L / And can be transmitted to the display panel 100 through the respective gate wirings.

At this time, since the number of gate output terminals and the number of data output terminals of the display panel 100 are different, dummy gate wirings can be formed between the data wirings.

Such a dummy gate wiring may not be connected to the output terminal (dummy output terminal) of the driving driver IC. (No Connected)

For example, the first to fourth gate lines G1, G2, G3 and G4 are connected to the first to fourth output terminals OUT1, OUT2, OUT3 and OUT4, but the fifth to seventh gate lines G5 , G6 and G7 may not be connected to the output terminal (dummy output terminal). (NC)

6 is a diagram referred to explain the rhythm phenomenon of the display panel according to the first embodiment of the present invention. 4 and 5 will be further described.

As described above, in the display panel 100, the pixel regions including the red, green, and blue pixel regions can be arranged in a matrix form of M * N (where M and N are arbitrary natural numbers) (M> N) , So that the number of gate output terminals and the number of data output terminals of the driving driver IC can be changed.

Therefore, the dummy gate wiring can be formed between the data lines due to the difference between the number of gate output terminals and the number of data output terminals.

On the other hand, when the display panel is driven, coupling between the gate wiring and the pixel region may occur.

The coupling between the gate wiring and the pixel region is performed by the first coupling by the gate wiring (G1, G2, G3, G4) connected to the output terminal of the gate driver IC and the gate wiring (G5, G6, G7).

That is, since the gate signal is transmitted through the gate wiring in the gate wiring (G1, G2, G3, G4) connected to the output terminal of the gate driver IC, the first coupling in the left / right pixel region of the gate wiring becomes large .

On the other hand, since gate signals are not transferred at the gate wirings (G5, G6, G7) connected to the dummy output terminals of the gate driver IC, the second coupling in the left and right pixel regions of the gate wirings have.

Due to the difference between the first coupling and the second coupling, a block dim or a line dim phenomenon may occur as shown in FIG. 6 when the display panel is driven.

Hereinafter, a second embodiment of the present invention for improving the block dim to line dim phenomenon will be described.

7 is a view schematically showing a display panel according to a second embodiment of the present invention. Hereinafter, the gate wiring and the dummy gate wiring are formed so as to have a ratio of 4: 1, but the present invention is not limited thereto and various modifications can be made to the structure in which the block dim or the line dim phenomenon can be improved. 3 will be further described.

G2, G3, G4, G5, G6, G7, G8, and a plurality of data lines D1, D2, D3 And a plurality of connection wirings C1, C2, C3, C4, C5, C6, C7, C8, etc. may be formed on the first and second substrates D2, D4, D5, D6, D7,

Here, the plurality of sub-pixel regions may be, for example, red, green, and blue sub-pixel regions, and may be sequentially arranged in the horizontal direction (horizontal direction).

In the display panel 100, pixel regions including red, green, and blue pixel regions may be arranged in a matrix of M * N (where M and N are arbitrary natural numbers).

The plurality of gate lines G1, G2, G3, G4, G5, G6, G7, G8, ... and the plurality of data lines D1, D2, D3, D4, D5, D6, D7, They may extend in a first direction (vertical direction), be spaced apart from each other, and be parallel to each other.

The plurality of gate wirings G1, G2, G3, G4, G5, G6, G7, G8 and the plurality of data wirings D1, D2, D3, D4, D5, D6, D7, As shown in the drawing, the first gate wiring G1, the first data wiring D1, the second gate wiring G2, the second data wiring D2, and the like are sequentially and alternately arranged in the second direction (horizontal direction) .

The plurality of gate lines G1, G2, G3, G4, G5, G6, G7, G8, ... and the plurality of data lines D1, D2, D3, D4, D5, D6, D7, However, the present invention is not limited thereto and two gate wirings may be formed per three data lines.

For example, the first gate wiring G1, the first data wiring D1, the second data wiring D2, the second gate wiring G2, and the third data wiring D3 (in the horizontal direction) ) Can be sequentially formed for each three data wirings.

The plurality of gate lines G1, G2, G3, G4, G5, G6, G7, G8, .. are connected to the plurality of connection wirings C1, C2, C3, C4, C5, And a plurality of data lines D1, D2, D3, D4, D5, D6, D7, ... intersecting with each other.

The plurality of gate lines G1, G2, G3, G4, G5, G6, G7, G8, ... are connected to the plurality of connection wirings C1, C2, C3, C4, C5, ), And transmits a gate signal transmitted through each gate line to each sub-pixel region.

Partial gate wirings, for example, the fourth and eighth gate wirings G4 and G8, among the plurality of gate wirings G1, G2, G3, G4, G5, G6, G7, It may not be connected to the connection wiring.

In the display panel 100, the pixel regions including the red, green and blue pixel regions can be arranged in a matrix form of M * N (where M and N are arbitrary natural numbers) (M> N) And the number of data output terminals are different, dummy gate wirings G4 and G8 can be formed between the data wirings. (Dum)

In the second embodiment of the present invention, the dummy gate wirings (G4 and G8) can be formed so as to be connected to the dummy output terminals of the driving driver.

That is, in the case of the dummy gate wiring, it is not connected to the first and second thin film transistors T1 and T2 in the display panel 100, but may be connected to the dummy output terminal of the gate driver IC.

A gate low voltage (VGL) or a low potential voltage may be output from the dummy output terminal of the gate driver IC connected to the dummy gate wiring.

And a plurality of data lines D1, D2, D3, D4, D5, D6, ..., and a plurality of data lines D1, D2, D7, ..., or the like may be formed on the first and second thin film transistors T1 and T2.

Here, the sub-pixel region including the first thin film transistor T1 can receive the data signal through the data line D1 on the left side, and the sub-pixel region including the second thin film transistor T2 can receive the data signal on the right side The data signal can be received through the wiring D1.

For example, the first thin film transistor T1 connected to the first connection wiring C1 can receive a data signal through the left data line.

The second thin film transistor T2 connected to the second connection wiring C2 can receive the data signal through the data line on the right side.

That is, the first thin film transistor T1 and the second thin film transistor T2 share the same data line and can receive the data signal as they are turned on by the gate signal, respectively.

When driving the sub-pixel region of the image display apparatus, if the gate signals supplied through the gate wiring are first transmitted to the first and second thin film transistors T1 and T2 through the plurality of connection wirings, The thin film transistors T1 and T2 are turned on so that data signals supplied through the plurality of data lines D1, D2, D3, D4, D5, D6, D7, ... are transferred to the storage capacitor do.

In the second embodiment of the present invention, by applying a plurality of driving driver ICs, the left and right panel bezel portions of the display panel can be removed. As a result, the bezels on both sides of the display panel are reduced to realize a Narrow Bezel .

In addition, in the second embodiment of the present invention, the narrow bezel can be more effectively implemented by forming the gate wiring in the form of a vertical gate wiring in the inside (display area) of the display panel.

In addition, in the second embodiment of the present invention, the dummy gate line and the dummy output terminal of the gate driver IC are connected to each other to form a block dim or line dim line according to the coupling difference in the gate wiring and the dummy gate wiring. dim phenomenon can be improved.

8 and 9 are views schematically showing a gate driver IC according to a second embodiment of the present invention. 3 and 7 will be further described.

As shown in FIG. 8, the plurality of gate driver ICs may include a shift register portion, a level shift portion (L / S), and an output buffer portion (BUF).

Here, the shift register section includes a flip-flop (F / F) and the like, and each output can be shifted by the gate start pulse GSP and the gate shift clock GSC to be transferred to the level shift section L / S.

The level shifter L / S receives the gate high voltage VGH and the gate low voltage VGL and can shift each output level.

The output buffer unit BUF includes a plurality of output terminals OUT1, OUT2, OUT3, OUT4, OUT5, OUT6, OUT7, OUT8, OUT9, L / S) to the display panel 100 through each gate line.

At this time, since the number of gate output channels and the number of data channels of the display panel 100 are different, dummy gate wirings can be formed between the data wirings.

Such a dummy gate wiring can be connected to the dummy output terminals OUT4 and OUT8 of the driving driver IC.

For example, the first to third gate lines G1, G2 and G3 are connected to the first to third output terminals OUT1, OUT2 and OUT3 while the dummy gate line G4 is connected to the dummy output terminal OUT4. As shown in FIG.

The fifth to seventh gate lines G5, G6 and G7 are connected to the fifth to seventh output terminals OUT5 to OUT6 and the dummy gate line G8 is connected to the dummy output terminal OUT8. .

The dummy output terminals OUT4 and OUT8 of the driving driver IC are connected to the dummy gate wiring and a constant low level voltage can be output through the dummy output terminals OUT4 and OUT8.

That is, a separate low potential voltage (Vss) terminal is further provided to connect the dummy gate line to the dummy gate line through the level shifter L / S and the output buffer BUF connected to the dummy output terminals OUT4 and OUT8. (Vss).

That is, the configuration ratio of the general output terminal and the dummy output terminal of the IC of each gate driver is K: 1. (K is the rational number)

Although not shown, all the output terminals of the ICs of any gate driver are all connected as common output terminals to the gate wiring, and the output terminals of the ICs of the remaining gate drivers are all connected to the dummy gate wiring as dummy output terminals .

That is, the gate wiring and the dummy gate wiring can be formed in the IC unit of the gate driver.

For example, in the case of a driving driver IC for driving a side surface of a display panel, in the case of a driving driver IC for driving all the central portions of the display panel, It can be connected to the dummy gate wiring so that all the output terminals are configured as dummy output terminals.

As shown in FIG. 9, the gate line voltage VGL is supplied to the dummy gate line through the output buffer unit BUF having the connection wiring separate from the gate low voltage (VGL) terminal and connected to the dummy output terminals OUT4 and OUT8. And may transmit a low voltage VGL.

As a result, according to the second embodiment of the present invention, since the gate wiring formed in the left and right panel bezel portions is formed in the display region of the display panel, the space for forming the gate wiring can be further reduced, Can be implemented.

In addition, in the second embodiment of the present invention, the dummy gate line and the dummy output terminal of the gate driver IC are connected to each other to form a block dim or line dim line according to the coupling difference in the gate wiring and the dummy gate wiring. dim phenomenon can be improved.

The embodiments of the present invention as described above are merely illustrative, and those skilled in the art can make modifications without departing from the gist of the present invention. Accordingly, the protection scope of the present invention includes modifications of the present invention within the scope of the appended claims and equivalents thereof.

100: display panel 110: drive driver IC
G1, G2, G3, G4, G5, G6, G7, ..: Gate wiring
D1, D2, D3, D4, D5, D6, D7, ...:
C1, C2, C3, C4, C5, C6, C7, C8, ...:

Claims (14)

A display panel for displaying an image;
A plurality of gate wirings and a plurality of data wirings formed on the display panel and defining a plurality of sub-pixel regions crossing each other, and a plurality of connection wirings;
And a driving driver including a plurality of driving driver ICs for supplying a gate signal or a data signal for driving the display panel,
Wherein the gate wirings extend in a first direction and are spaced apart from each other by a predetermined distance and are formed so as to be parallel to the data wirings,
Wherein the connection wiring extends in a second direction and is connected to the gate wiring to transfer the gate signal to the sub pixel region,
Wherein the gate wiring is divided into a general gate wiring for transferring the gate signal and a dummy gate wiring for transferring the gate signal.
delete The method according to claim 1,
The driving driver IC includes:
A shift register unit for shifting and transmitting the output of the flip-flop by a plurality of gate control signals;
A level shift unit which receives the gate high voltage and the gate low voltage and shifts each output level;
And an output buffer unit including a plurality of output terminals connected to the gate wiring and transmitting a gate signal received from the level shifting unit to the display panel,
And an output terminal of the output buffer unit,
Wherein the gate signal is divided into a general output terminal for transmitting the gate signal or a dummy output terminal for not transmitting the gate signal.
The method of claim 3,
Wherein the common output terminal is connected to the common gate line, and the dummy output terminal is not connected to the dummy gate line.
The method of claim 3,
Wherein the common output terminal is connected to the common gate line, and the dummy output terminal is connected to the dummy gate line.
6. The method of claim 5,
And a low potential voltage terminal or a gate low voltage terminal is connected to the dummy output terminal and the low potential voltage or the gate low voltage is transmitted to the display panel through the dummy output terminal.
The method according to claim 1,
A first or second thin film transistor is formed in the sub-pixel region,
The first thin film transistor receives the data signal through the left data line of the sub-pixel region,
Wherein the second thin film transistor receives the data signal through the right data line of the sub-pixel region.
Forming a plurality of gate wirings, a plurality of data wirings, and a display panel on which a plurality of connection wirings are formed, the plurality of gate wirings intersecting with each other to define a plurality of sub-pixel regions;
And connecting a plurality of driving driver ICs for supplying a gate signal or a data signal for driving the display panel to the display panel,
Wherein the gate wirings extend in a first direction and are spaced apart from each other by a predetermined distance and are formed so as to be parallel to the data wirings,
Wherein the connection wiring extends in a second direction and is connected to the gate wiring to transfer the gate signal to the sub pixel region,
Wherein the gate wiring is divided into a general gate wiring for transferring the gate signal and a dummy gate wiring for transferring the gate signal.
delete 9. The method of claim 8,
The driving driver IC includes:
A shift register unit for shifting and transmitting the output of the flip-flop by a plurality of gate control signals;
A level shift unit which receives the gate high voltage and the gate low voltage and shifts each output level;
And an output buffer unit including a plurality of output terminals connected to the gate wiring and transmitting a gate signal received from the level shifting unit to the display panel,
And an output terminal of the output buffer unit,
Wherein the gate signal is divided into a general output terminal for transferring the gate signal or a dummy output terminal for transferring the gate signal.
11. The method of claim 10,
Wherein the common output terminal is connected to the common gate wiring, and the dummy output terminal is not connected to the dummy gate wiring.
11. The method of claim 10,
Wherein the common output terminal is connected to the common gate wiring and the dummy output terminal is connected to the dummy gate wiring.
13. The method of claim 12,
Wherein the low output voltage terminal or the gate low voltage terminal is connected to the dummy output terminal and the low voltage or the gate low voltage is transmitted to the display panel through the dummy output terminal.
9. The method of claim 8,
A first or second thin film transistor is formed in the sub-pixel region,
The first thin film transistor receives the data signal through the left data line of the sub-pixel region,
Wherein the second thin film transistor receives the data signal through the right data line of the sub-pixel region.

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