KR102251620B1 - Driving Circuit And Display Device Including The Same - Google Patents

Abstract

In the present invention, a GOE falling detection unit for detecting a falling edge of a gate output enable of a timing control unit, a GOE rising detection unit for detecting a rising edge of the gate output enable, and a gate shift clock of the timing control unit are counted and counted. A counter for dividing the pulses of the gate output enable into two groups according to a result, and a plurality of output units respectively outputting a plurality of gate signals overlapping each other in a high level section according to the control of the counter, and the counter There is provided a driving circuit for a display device that controls the plurality of output units by independently using pulses of the gate output enable of two separate groups.

Description

Driving circuit and display device including the same

The present invention relates to a driving circuit for a display device, and more particularly, to a gate driver for generating a gate voltage using a gate control signal, and a display device including the same.

In recent years, as society enters the era of full-fledged information, the field of displays that process and display a large amount of information has developed rapidly, and in response to this, various flat panel displays (FPDs) have been developed and are in the spotlight. , Examples of flat panel display devices include a liquid crystal display device (LCD device), an organic light emitting diode device (OLED device), and a plasma display panel device (PDP device). Can be lifted.

BACKGROUND ART In general, a display device displays an image using a plurality of pixel areas. Recently, as the resolution of the display device is required to increase, the number of data wirings increases and the allocated area of each pixel area tends to be insufficient.

To overcome this, a double rate driving (DRD) display device is proposed that reduces the number of data lines and increases horizontal resolution by supplying data signals to two pixel areas using one data line. Became.

However, in such a DRD type display device, since the number of gate wirings increases instead of the number of data wirings, the time allotted to the gate signals supplied through the gate wirings decreases, and as a result, the data signal is converted into each pixel area. There is a problem in that the time supplied to the device, that is, the charging time of the data signal, decreases.

In order to compensate for this, a gate overlap driving method for simultaneously supplying data signals transmitted through one data line to two vertically adjacent pixel regions has been proposed, which will be described with reference to the drawings.

1 is a diagram illustrating a conventional DRD type display device, and FIG. 2 is a timing diagram of a plurality of signals of a conventional DRD type display device.

As shown in FIGS. 1 and 2, a conventional DRD display device includes a timing control unit 20, a gate driver 40, and a display panel 50.

The timing control unit 20 generates a plurality of gate control signals and supplies them to the gate driver 40, and the plurality of gate control signals include first and second gate start pulses (GSP1, GSP2), and a first And second gate output enable (GOE1, GOE2), first and second gate shift clocks (GSC1, GSC2), first and second flicker signals FLK1, FLK2).

The first and second gate start pulses (GSP1, GSP2) are signals indicating the generation time of the gate signals (VG1, VG2, ..., VGm), and the first and second gate output enable (GOE1, GOE2) Is a signal indicating the output timing of the gate signals (VG1, VG2, ..., VGm), and the first and second gate shift clocks (GSC1, GSC2) are the gate signals (VG1, VG2, ..., VGm) Is a signal used as a reference for sequential driving of, and the first and second flicker signals FLK1 and FLK2 are signals used as a reference for modulation of the gate signals VG1, VG2, ..., VGm for improving flicker.

The gate driver 40 generates a plurality of gate signals VG1, VG2, ..., VGm from a plurality of control signals supplied from the timing control unit 20 and supplies them to the display panel 50.

Specifically, the gate driver 40 uses a first gate start pulse (GSP1), a first gate output enable (GOE1), a first gate shift clock (GSC1), and a first flicker signal (FLK1). Generate gate signals (VG1, VG3, ...), second gate start pulse (GSP2), second gate output enable (GOE2), second gate shift clock (GSC2), second flicker signal (FLK2) Even-numbered gate signals (VG2, VG4, ...) can be generated by using.

Accordingly, each of the plurality of gate signals (VG1, VG2, ..., VGm) output from the gate driver 40 increases the high level section, and the plurality of gate signals (VG1, VG2, ..., VGm) Of the two adjacent to each other, the high level sections partially overlap each other, and as a result, it is possible to compensate for the reduction in charging time of the data signal.

That is, in two vertically adjacent pixel regions, while the data signal is applied to the upper pixel region, the data signal is also applied to the lower pixel region, thereby increasing the charging time of the data signal in the lower pixel region.

In general, the timing control unit 20 and the gate driving unit 40 are made of an integrated circuit (IC), and the integrated circuit for the timing control unit 20 is mounted on a printed circuit board (PCB), A plurality of gate control signals are output from the output pins of the integrated circuit for the timing control unit 20 and are input to the input pins of the integrated circuit for the gate driver 40 through wiring on the printed circuit board.

In addition, in some cases, the plurality of gate control signals of the timing control unit 20 pass through the wiring of the printed circuit board, and then the gate driver through a line on glass (LOG) formed in the edge region of the display panel 50. Can be supplied to (40).

However, in a conventional DRD type display device, first and second gate start pulses (GSP1, GSP2), first and second gate output enable (GOE1, GOE2), and first and second gate shift clocks (GSC1) , GSC2) and the first and second flicker signals FLK1 and FLK2, which are twice as large as the gate control signals compared to general display devices, so the size of the integrated circuit for the timing control unit 20 and the number of output pins (at least 8) increases, and the size of the integrated circuit for the gate driver 40 and the number of input pins (at least 8) increase.

In addition, as the number of wirings of the printed circuit board increases, there is a problem in that the degree of freedom in design of the printed circuit board decreases.

In addition, as the number of wires LOG of the display panel 50 increases, the bezel, which is a non-display area of the display panel 50, increases, or the area allocated to each wire LOG decreases. There is a problem that the resistance of the wiring LOG increases.

The present invention has been proposed to solve this problem, and divides the pulses of a plurality of gate control signals into two groups in order, and uses the pulses of a plurality of gate control signals independently to partially overlap each other. An object of the present invention is to provide a driving circuit in which the size and number of input/output pins are reduced and design freedom is improved by generating a plurality of gate signals, and a display device including the same.

And, by dividing the pulses of a plurality of gate control signals into two groups in order, and independently using the pulses of the plurality of gate control signals to generate a plurality of gate signals in which the high level sections partially overlap each other, the bezel is Another object is to provide a reduced driving circuit and a display device including the same.

In order to solve the above problems, the present invention provides a GOE falling detection unit for detecting a falling edge of a gate output enable of a timing control unit, a GOE rising detection unit for detecting a rising edge of the gate output enable, and the timing control unit. A counter for counting the gate shift clock and dividing the pulses of the gate output enable into two groups according to the count result, and a plurality of gate signals each outputting a plurality of gate signals overlapping each other according to the control of the counter. An output unit is provided, and the counter provides a driving circuit for a display device that controls the plurality of output units by independently using pulses of the gate output enable of two separate groups.

In addition, the plurality of output units include n-th and (n+1)-th output units respectively outputting n-th and (n+1)-th gate signals, and the counter is, after counting the gate shift clock, the gate Start (ON) the output of the n-th output unit at the falling edge of the first odd-numbered pulse of the output enable, and stop (OFF) the output of the n-th output unit at the rising edge of the next odd-numbered pulse of the gate output enable. And, at the falling edge of the first even-numbered pulse of the gate output enable, the output of the (n+1)th output unit is started (ON), and at the rising edge of the next even-numbered pulse of the gate output enable, the ( n+1) The output of the output part can be stopped (OFF).

In addition, the driving circuit for the display device further includes an FLK falling detection unit for detecting a falling edge of the flicker signal of the timing control unit, and the counter is, after the count of the gate shift clock, the first even pulse of the flicker signal is An output of the nth output unit may be modulated at a falling edge, and an output of the nth output unit may be modulated at a falling edge of an odd-numbered pulse next to the flicker signal.

On the other hand, the present invention provides a timing control unit for generating a gate control signal, a data control signal and image data, a data driver for generating a data signal using the data control signal and the image data, and a pulse of the gate control signal. A gate driver for generating a plurality of gate signals overlapping each other by dividing into two groups and independently using the pulses of the gate control signals of the divided two groups, and the plurality of gate signals and the data signals. A display device including a display panel displaying an image is provided.

In addition, the gate control signal includes a gate output enable and a gate shift clock, and the gate driver includes a GOE falling detection unit detecting a falling edge of the gate output enable, and a rising edge of the gate output enable. A counter for counting the gate shift clock and dividing the pulse of the gate output enable into two groups according to the count result, and a plurality of outputting the plurality of gate signals respectively according to the control of the counter. It may include an output of.

In addition, the plurality of output units include n-th and (n+1)-th output units respectively outputting n-th and (n+1)-th gate signals, and the counter is, after counting the gate shift clock, the gate Start (ON) the output of the n-th output unit at the falling edge of the first odd-numbered pulse of the output enable, and stop (OFF) the output of the n-th output unit at the rising edge of the next odd-numbered pulse of the gate output enable. And starting (ON) the output of the (n+1)th output unit at the falling edge of the first even-numbered pulse of the gate output enable, and starting (ON) the output of the (n+1)th output unit at the rising edge of the next even-numbered pulse of the gate output enable. n+1) The output of the output part can be stopped (OFF).

And, the gate control signal further includes a flicker signal, the gate driver further includes a FLK falling detection unit for detecting a falling edge of the flicker signal, the counter, after the count of the gate shift clock, the flicker signal The output of the n-th output unit may be modulated at the falling edge of the first even-numbered pulse of, and the output of the n-th output unit may be modulated at the falling edge of the next odd-numbered pulse of the flicker signal.

The present invention has been proposed to solve this problem, and divides the pulses of a plurality of gate control signals into two groups in order, and uses the pulses of a plurality of gate control signals independently so that the high-level sections partially overlap each other. By generating a plurality of gate signals, the size and number of input/output pins are reduced, and design freedom is improved.

In addition, the present invention divides the pulses of a plurality of gate control signals into two groups in order, and generates a plurality of gate signals in which the high level sections partially overlap each other by independently using the pulses of the plurality of gate control signals. , Has the effect of reducing the bezel.

1 is a diagram showing a conventional DRD type display device.
2 is a timing diagram of a plurality of signals in a conventional DRD display device.
3 is a diagram illustrating a display device according to an exemplary embodiment of the present invention.
4 is a diagram illustrating a timing control unit, a gate driver, and a panel of a DRD type display device according to an exemplary embodiment of the present invention.
5 is a timing diagram of a plurality of signals of a DRD display device according to an embodiment of the present invention.

A driving circuit and a display device including the same according to the present invention will be described with reference to the accompanying drawings.

3 is a diagram illustrating a display device according to an exemplary embodiment of the present invention.

As shown in FIG. 3, the DRD type display device 110 according to the embodiment of the present invention includes a timing control unit 120, a data driving unit 130, a gate driving unit 140, and a display panel 150. .

The timing control unit 120 includes a video signal (IS) and a data enable (DE) transmitted from an external system such as a graphic card or a TV system, a horizontal synchronization signal (HSY), a vertical synchronization signal (VSY), and a clock (CLK). A gate control signal (GCS), a data control signal (DCS), and image data (RGB) are generated using a plurality of timing signals, and the generated data control signal (DCS) and image data (RGB) are a data driver. It is supplied to 130 and the generated gate control signal GCS is supplied to the gate driver 130.

The data driving unit 130 generates a data signal by using the data control signal DCS and the image data RGB supplied from the timing control unit 120, and uses the generated data signal to a plurality of data of the display panel 150. It is supplied to the wirings DL1 and DL2.

The gate driver 140 generates a gate signal using the gate control signal GCS supplied from the timing control unit 120, and transmits the generated gate signal to a plurality of gate wirings GL1 to GL4 of the display panel 150. To supply.

The display panel 150 displays an image using a gate signal and a data signal. For this purpose, the display panel 150 crosses each other to define a plurality of pixel regions P1 to P8. To GL4) and a plurality of data lines (DL1, DL2), a plurality of gate lines (GL1 to GL4) and a thin film transistor (T) connected to the plurality of data lines (DL1, DL2), respectively, and a thin film transistor (T) It includes a pixel electrode PE connected to.

Here, the display panel 150 may be a liquid crystal panel or an organic light emitting diode panel, and when the display panel 150 is a liquid crystal panel, gray scale is displayed by adjusting the transmittance of the liquid crystal layer between the pixel electrode PE and the common electrode. , When the display panel 150 is an organic light emitting diode panel, the gray scale is displayed by adjusting the output of the light emitting diode connected to the pixel electrode PE.

Meanwhile, the configuration of the display panel 150 for driving in the DRD method will be described by taking the first to eighth pixel regions P1 to P8 as an example.

A plurality of pixel regions P1 to P8 are disposed between the first and second gate wirings GL1 and GL2 and between the third and fourth gate wirings GL3 and GL4, and the second and third gate wirings ( A pixel area is not disposed between GL2 and GL3.

Specifically, first and second pixel regions P1 and P2 and fifth and sixth pixel regions P5 are provided on both left and right sides of the first data line DL1 between the first and second gate lines GL1 and GL2. , P6) are disposed, and third and fourth pixel areas P3 and P4 and seventh and eighth pixel areas P7 and P8 are disposed on both left and right sides of the second data line DL2.

In addition, the thin film transistors T of the first to fourth pixel regions P1 to P4 between the first and second gate wirings GL1 and GL2 are alternately connected to the first and second gate wirings GL1 and GL2. The thin film transistors T of the fifth to eighth pixel regions P5 to P8 between the third and fourth gate wires GL3 and GL4 are alternately connected to the third and fourth gate wires GL3 and GL4. do.

For example, the thin film transistor T of the first pixel region P1 is connected to the first gate line GL1 and the first data line DL1, and the thin film transistor T of the second pixel region P2 Is connected to the second gate line GL2 and the first data line DL1.

The connection relationship between the thin film transistors T in the third and fourth pixel regions P3 and P4, the connection relationship between the thin film transistors T in the fifth and sixth pixel regions P5 and P6, and the seventh and fourth pixel regions The connection relationship between the thin film transistors T in the eight pixel regions P7 and P8 is similar to the connection relationship between the thin film transistors T in the first and second pixel regions P1 and P2, respectively.

In this configuration, when the thin film transistor T is turned on by a gate signal supplied to a plurality of gate lines GL1 to GL4, data supplied to a plurality of data lines DL1 and DL2 Signals are applied to a plurality of pixel regions P1 to P8 through the thin film transistor T, and one data line supplies data signals to two pixel regions on both left and right sides.

That is, when the thin film transistor T of the first and third pixel regions P1 and P3 is turned on by the gate signal supplied to the first gate line GL1, the data signal is transmitted to the first and second data lines ( The second and fourth pixel regions P2 and P4 are transmitted to the first and third pixel regions P1 and P3, respectively, through DL1 and DL2, and then supplied to the second gate wiring GL2 by a gate signal. When the thin film transistor T of is turned on, a data signal is transmitted to the second and fourth pixel regions P2 and P4 through the first and second data lines DL1 and DL2, respectively.

Likewise, when the thin film transistors T of the first and third pixel regions P1 and P3 are turned on by the gate signal supplied to the third gate line GL3, the data signal is transferred to the first and second data lines. The second and fourth pixel regions P2 and P4 are transmitted to the first and third pixel regions P1 and P3, respectively, through DL1 and DL2, and then supplied to the fourth gate wiring GL4 by a gate signal. When the thin film transistor T of is turned on, a data signal is transmitted to the second and fourth pixel regions P2 and P4 through the first and second data lines DL1 and DL2, respectively.

As described above, in the liquid crystal display device 80 of the dual rate driving method, since two adjacent sub-pixel regions are driven through one data line, the number of data lines is reduced to 1/2, and accordingly, the data driving integrated circuit ( The number of driving integrated circuits (D-ICs) is reduced, which reduces manufacturing costs.

Instead, the number of gate wiring is doubled, but by employing a gate driver formed on an array substrate such as a gate-in-panel (GIP), an increase in the burden on gate driving can be eliminated. .

In the DRD type display device 110, in order to compensate for the charging time of the data signal due to the decrease in the number of gate wirings, the data signal transmitted through one data line is simultaneously supplied to two vertically adjacent pixel areas. The gate overlapping driving method is applied. In this case, the gate driver 140 divides the gate control signal supplied from the timing control unit 120 into 2 groups, and the gate used in the gate overlap driving method from the separated 2 groups of gate control signals. A signal is generated, which will be described with reference to the drawings.

4 is a diagram illustrating a timing control unit, a gate driver, and a panel of a DRD type display device according to an exemplary embodiment of the present invention, and FIG. 5 is a timing diagram of a plurality of signals of a DRD type display device according to an exemplary embodiment of the present invention. It will be described with reference to FIG. 3 together.

4 and 5, in the DRD type display device 110 according to the embodiment of the present invention, the timing control unit 140 generates a plurality of gate control signals and supplies them to the gate driver 140, Multiple gate control signals include gate start pulse (GSP), gate output enable (GOE), gate shift clock (GSC), and flicker signal (FLK). ).

The gate start pulse (GSP) is a signal indicating the generation time of the gate signals (VG1, VG2, ..., VGm), and the gate output enable (GOE) is the gate signal (VG1, VG2, ..., VGm). It is a signal indicating the output point of, and the gate shift clock (GSC) is a signal that serves as a reference for sequential driving of the gate signals (VG1, VG2, ..., VGm).

The flicker signal (FLK) is a signal used as a reference for modulation that reduces the rear end of the gate signal (VG1, VG2, ..., VGm) to prevent flicker, and the kickback voltage is reduced by reducing the rear end of the gate signal. Is reduced and flicker is prevented.

In the embodiment of the present invention, the flicker signal FLK is used to generate the gate signals VG1, VG2, ..., VGm, but in other embodiments where the effect of flicker is small, the flicker signal is omitted and the gate start pulse (GSP) is used. ), gate output enable (GOE), and gate shift clock (GSC) may be used to generate gate signals VG1, VG2, ..., VGm.

The gate driver 140 generates a plurality of gate signals VG1, VG2, ..., VGm from a plurality of control signals supplied from the timing control unit 120 and supplies them to the display panel 150.

Specifically, the gate driving unit 140 includes a GOE falling detection unit 141, a GOE rising detection unit 143, an FLK falling detection unit 145, a counter 147, and a plurality of output units 149.

The GOE falling detection unit 141 and the GOE rising detection unit 143 detect the falling edge and the rising edge of the gate output enable (GOE), respectively, and transmit them to the counter 147, and the FLK falling detection unit The 145 detects the falling edge of the flicker signal and transmits it to the counter 147.

The counter 147 counts the gate shift clock (GSC), and according to the count result, the pulse of the gate output enable (GOE) and the pulse of the flicker signal (FLK) are divided into 2 groups (for example, an odd-numbered pulse group). And even-numbered pulse groups), and control the plurality of output units 149 by independently using the pulses of the gate output enable (GOE) and the pulses of the flicker signal (FLK) of the divided two groups.

The plurality of output units 149 generate a plurality of gate signals VG1, VG2, ..., VGm under the control of the counter 147 and sequentially supply them to the display panel 150.

For example, when the counter 147 detects and counts the rising edge of the gate shift clock (GSC), after detecting the rising edge, the falling edge of the first pulse (first odd pulse) of the gate output enable (GOE) ( At t1), the output of the nth output is started (ON), and the output of the (n+1)th output is started at the falling edge (t2) of the second pulse (first even pulse) of the gate output enable (GOE). (ON), modulates the output of the n-th output unit at the falling edge (t3) of the second pulse (first even-numbered pulse) of the flicker signal FLK, and the third pulse of the gate output enable (GOE) The output of the n-th output unit is stopped (OFF) at the rising edge (t4) of the (next odd-numbered pulse), and at the falling edge (t5) of the third pulse (next odd-numbered pulse) of the flicker signal (FLK) +1) Modulates the output of the output section and stops the output of the (n+1)th output section at the rising edge (t6) of the fourth pulse (next even numbered pulse) of the gate output enable (GOE). )can do.

That is, the gate driver 140 includes a falling edge t1 of the first pulse of the gate output enable GOE, a falling edge t3 of the second pulse of the flicker signal FLK, and the gate output enable GOE. The n-th gate signal is output by controlling the n-th output unit using the rising edge (t4) of the third pulse of, and the falling edge (t2) of the second pulse of the gate output enable (GOE), and the flicker signal (FLK) The (n+1)th gate signal is controlled by controlling the (n+1)th output unit by using the falling edge of the third pulse of (t5) and the rising edge of the fourth pulse of the gate output enable (GOE). Can be printed.

Here, the n-th gate signal has a high level section between the falling edge t1 of the first pulse of the gate output enable GOE and the rising edge t4 of the third pulse, and the (n+1)th gate signal Has a high level section between the falling edge t2 of the second pulse of the gate output enable (GOE) and the rising edge t6 of the fourth pulse, so the nth and (n+1)th gate signals are The high-level section is overlapped between the falling edge t2 of the second pulse of the output enable GOE and the rising edge t4 of the third pulse (OS).

Subsequently, the gate driver 140 controls the (n+2)th and (n+3)th output units according to the gate shift clock GSC to provide the (n+2) and (n+3)th gate signals. Can be printed.

As described above, in the DRD display device 110 according to the embodiment of the present invention, the pulses of the gate output enable (GOE) and the flicker signal (FLK) are divided into two groups according to the gate shift clock (GSC), By using the pulses of the gate output enable (GOE) and the flicker signal (FLK) of two separate groups, a gate signal overlapping the high level section can be generated, and as a result, it is possible to compensate for the reduction in charging time of the data signal. .

In addition, a gate signal in which the high level sections overlap each other is generated by using the gate start pulse (GSP), the gate output enable (GOE), the gate shift clock (GSC), and the gate control signal (GCS) of the flicker signal (FLK). Therefore, compared to the conventional DRD display device, the size of the integrated circuit for the timing control unit 120 and the number of output pins (4) are reduced, and the size of the integrated circuit for the gate driver 140 and the number of input pins (4) are reduced. Number) decreases, and design freedom is improved.

In addition, when the gate control signal GCS of the timing controller 120 is supplied to the gate driver 140 using the wiring LOG of the display panel 150, the number of wirings LOG of the display panel 150 Decreases, and the bezel of the display device 110 decreases, thereby improving the appearance.

In the embodiment of the present invention, a liquid crystal display device or an organic light emitting diode display device has been described as an example, but in other embodiments, the driving circuit of the present invention can be applied to other flat panel display devices such as a plasma display device.

Although the above has been described with reference to preferred embodiments of the present invention, those skilled in the art will variously modify and change the present invention within the scope not departing from the spirit and scope of the present invention described in the following claims. You will understand that you can do it.

110: DRD type display device 120: timing control unit
130: data driving unit 140: gate driving unit
141: GOE descend detection unit 143: GOE rise detection unit
145: FLK fall detection unit 149: multiple output units
150: display panel

Claims (9)

A GOE falling detection unit for detecting a falling edge of the gate output enable of the timing control unit;
A GOE rise detection unit for detecting a rising edge of the gate output enable;
A counter for counting the gate shift clock of the timing control unit and dividing the pulse of the gate output enable into two groups according to a count result;
A plurality of output units each outputting a plurality of gate signals overlapping each other in the high level section under the control of the counter
Including,
The counter controls the plurality of outputs by independently using pulses of the gate output enable of two groups,
The plurality of output units include n-th and (n+1)-th output units respectively outputting n-th and (n+1)-th gate signals,
The counter, after the count of the gate shift clock,
The output of the n-th output unit is started (ON) at the falling edge of the first odd-numbered pulse of the gate output enable, and the output of the n-th output unit is stopped at the rising edge of the next odd-numbered pulse of the gate output enable ( OFF), the n-th gate signal has a high level section between the falling edge of the first odd-numbered pulse of the gate output enable and the rising edge of the next odd-numbered pulse of the gate output enable,
The output of the (n+1)th output unit is started (ON) at the falling edge of the first even-numbered pulse of the gate output enable, and the (n+1)th output is started at the rising edge of the next even-numbered pulse of the gate output enable. 1) By stopping the output of the output unit (OFF), the (n+1)th gate signal is between the falling edge of the first even-numbered pulse of the gate output enable and the rising edge of the next even-numbered pulse of the gate output enable. A driving circuit for a display device having a high level section in.
delete The method of claim 1,
Further comprising a FLK falling detection unit for detecting a falling edge of the flicker signal of the timing control unit,
The counter modulates the output of the n-th output unit at the falling edge of the first even-numbered pulse of the flicker signal after counting the gate shift clock, and the n-th output at the falling edge of the next odd-numbered pulse of the flicker signal. A drive circuit for a display device that modulates a negative output.
A timing control unit for generating a gate control signal, a data control signal, and image data;
A data driver for generating a data signal using the data control signal and the image data;
A gate driver for dividing the pulses of the gate control signal into two groups, and generating a plurality of gate signals in which high-level sections overlap each other by independently using the pulses of the two separated gate control signals;
Display panel displaying an image using the plurality of gate signals and the data signals
Including,
The gate control signal includes a gate output enable and a gate shift clock,
The gate driver,
A GOE falling detection unit for detecting a falling edge of the gate output enable;
A GOE rise detection unit for detecting a rising edge of the gate output enable;
A counter for counting the gate shift clock and dividing the pulse of the gate output enable into two groups according to a count result;
A plurality of output units respectively outputting the plurality of gate signals under the control of the counter
Including,
The plurality of output units include n-th and (n+1)-th output units respectively outputting n-th and (n+1)-th gate signals,
The counter, after the count of the gate shift clock,
The output of the n-th output unit is started (ON) at the falling edge of the first odd-numbered pulse of the gate output enable, and the output of the n-th output unit is stopped at the rising edge of the next odd-numbered pulse of the gate output enable ( OFF), the n-th gate signal has a high level section between the falling edge of the first odd-numbered pulse of the gate output enable and the rising edge of the next odd-numbered pulse of the gate output enable,
The output of the (n+1)th output unit is started (ON) at the falling edge of the first even-numbered pulse of the gate output enable, and the (n+1)th output is started at the rising edge of the next even-numbered pulse of the gate output enable. 1) By stopping the output of the output unit (OFF), the (n+1)th gate signal is between the falling edge of the first even-numbered pulse of the gate output enable and the rising edge of the next even-numbered pulse of the gate output enable. A display device having a high-level section in.
delete delete The method of claim 4,
The gate control signal further includes a flicker signal,
The gate driving unit further includes an FLK falling detection unit for detecting a falling edge of the flicker signal,
The counter modulates the output of the n-th output unit at the falling edge of the first even-numbered pulse of the flicker signal after the count of the gate shift clock, and the n-th output at the falling edge of the next odd-numbered pulse of the flicker signal. A display device that modulates the negative output.
The method of claim 1,
The driving circuit for a display device in which a high-level section overlaps between a falling edge of a first even-numbered pulse of the gate output enable and a rising edge of a next odd-numbered pulse of the n-th and (n+1)-th gate signals.
The method of claim 4,
The n-th and (n+1)-th gate signals overlap a high-level section between a falling edge of a first even-numbered pulse and a rising edge of a next odd-numbered pulse of the gate output enable.

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