KR20140038240A - Liquid crystal display and undershoot generation circuit thereof - Google Patents

Abstract

A liquid crystal display device is disclosed. More specifically, the present invention relates to a liquid crystal display device for solving the malfunction problem due to the reduced charging time of a gate line when a single data line is shared among neighboring pixels in a double rate driving type (DRD) structure. The liquid crystal display device according to a preferable embodiment of the present invention comprises a liquid crystal panel which has a plurality of gate lines and a plurality of data lines formed in a matrix form and defines a pixel in a cross point therebtween; a gate driving unit and a data driving unit for respectively providing the gate lines and the data lines with a gate driving voltage and a data voltage; a level shift unit which has a gate high voltage and a gate low voltage and provides the gate driving unit with a gate clock signal for generating the gate driving voltage; and an undershoot generation unit for providing the level shift unit with the gate low voltage to have two or more different voltage levels and inserting an undershoot section into the gate driving voltage. Therefore, the liquid crystal display device of the present invention provides the discharging time point of the gate line with the voltage of the lower level than at least existing gate low voltage in the voltages supplied to the gate driving unit from a power supply unit, thereby minimizing gate discharging time delay to be stably driven. [Reference numerals] (110) Timing control unit; (120) Gate driving unit; (130) Data driving unit; (140) Level shifter unit; (150) Undershoot generation unit

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY AND UNDERSHOOT GENERATION CIRCUIT THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display that improves a malfunction problem caused by a charging time of a gate wiring which is reduced by sharing one data line between neighboring pixels, such as a double rate driving type. Relates to a device.

Recently, various portable devices such as mobile phones and laptop computers, and information electronic devices that implement high resolution and high quality images such as HDTVs have been developed. The demand for display devices is gradually increasing. As such flat panel display devices, a liquid crystal display (LCD), a plasma display panel (PDP), a field emission display (FED), and an organic light emitting diode (OLED) have been actively studied. However, And realization of a large area screen, a liquid crystal display (LCD) is in the spotlight at present.

In particular, an active matrix type liquid crystal display device in which a thin film transistor (TFT) is used as a switching element is suitable for displaying dynamic images.

FIG. 1 schematically illustrates a structure of a conventional active matrix type liquid crystal display device, wherein an active matrix type liquid crystal display device includes a plurality of switches provided at intersections of a plurality of gate lines GL and data lines DL. A liquid crystal panel 1 composed of an element T, a timing controller 2, gates, and data drivers 3, 4; and a digital video signal applied from an external system as an analog data voltage using a reference voltage. By converting and supplying the data line DL and the gate driving voltage to the gate line GL, the data voltage is charged in the liquid crystal cell LC.

In detail, the gate electrode of the switching element T is connected to the gate wiring GL, the source electrode is connected to the data wiring DL, and the drain electrode of the switching element T is connected to the liquid crystal capacitor LC. Connected. The liquid crystal capacitor LC includes a pixel electrode and a common electrode. When the gate driving signal is applied from the gate driver 3 to the gate wiring GL under the control of the timing controller 2, the switching element is turned on and the source electrode is turned on. A channel is formed between the drain electrode and the drain electrode. When a data voltage is applied from the data driver 4 through the data line DL, the channel is supplied to the pixel electrode of the liquid crystal cell LC. In this case, the liquid crystal molecules of the liquid crystal cell LC change an arrangement by an electric field between the pixel electrode and the common electrode to display an image according to incident light.

Here, the gate driver 3 supplies a voltage of a gate high voltage VGH for turning on the switching element T as a gate driving signal and a gate low voltage VGL for turning off the power supply (not shown). It is supplied from the gate line and is output to the gate wiring GL. The gate high voltage VGH and the gate low voltage VGL are provided to the gate driver 3 in a form VG_M in which phases are inverted at predetermined intervals from a power supply unit (not shown) via a level shifter 5. The gate driver 3 sequentially outputs the gate driving voltage to each gate line GL as the gate driving voltage every one horizontal period 1H of the gate high voltage VGH, and the gate line GL to which the gate high voltage VGH is not applied. ) Outputs a gate low voltage VGL.

Meanwhile, in the conventional liquid crystal display, as shown in FIG. 1, one gate line GL and data line DL are allocated to each switching element T and included on one horizontal line for one horizontal period. Structure or a DRD structure that reduces the unit cost by reducing the number of output terminals of the data wiring DL and the data driver 4 by sharing the data wiring DL between neighboring switching elements T. A liquid crystal display device has been proposed.

2 is a view illustrating some pixels of a liquid crystal display device having a conventional DRD structure.

As shown in the drawing, a conventional DRD liquid crystal display device is shown. In the DRD structure liquid crystal display device, the switching elements T1 and T2 of pixels arranged on one horizontal line have two gate lines GL1 and GL2. The switching elements T3 and T4 of the pixels connected to one data line DL2 and arranged on the next horizontal line are connected to two gate lines GL3 and GL4 and the data line DL2.

According to this structure, the DRD structure liquid crystal display is driven by column Z-inversion when a data voltage of the same polarity is applied to one data line for one frame.

However, as shown, since the switching elements T1 and T2 of the pixels disposed on one horizontal line are operated by different gate wirings GL1 and GL2, the pixels of one horizontal line are driven during one horizontal period 1H. In order to apply the gate driving voltage to the two gate lines GL1 and GL2, the gate lines GL1 to GLn are driven by 1/2 horizontal period (1 / 2H), respectively.

This means that the switching elements of each pixel have half the charging and discharging time of the gate lines GL1 to GLn than in the prior art. Therefore, malfunctions due to insufficient charge / discharge time are often caused in the liquid crystal display of the DRD structure. do.

Disclosure of Invention The present invention has been made to solve the above-described problem, and an object thereof is to provide a liquid crystal display device that compensates for a problem of charging and discharging of a gate wiring lacking in a DRD structure liquid crystal display device.

In order to achieve the above object, a liquid crystal display device according to a preferred embodiment of the present invention, a plurality of gate wiring and data wiring is formed in a matrix form, the liquid crystal panel defining a pixel at the intersection; A gate driver supplying a gate driving voltage to the gate wiring; A data driver supplying a data voltage to the data line; A level shift unit including a gate high voltage and a gate low voltage, and supplying a gate clock signal for generating the gate driving voltage to the gate driver; And an undershoot generator for supplying the gate low voltage to the level shift unit to have at least two different voltage levels to insert an undershoot section into the gate driving voltage.

The gate low voltage may be divided into first and second gate low voltages having different voltage levels, and the second gate low voltage may be at least lower than the first gate low voltage.

The gate driving voltage may be a voltage level of the second gate low voltage in the undershoot period.

The gate clock signal is characterized in that the high level section and the low level section correspond to the high level section and the low level section of the clock signal supplied from the timing controller.

The undershoot period may be output in correspondence with the falling edge of the gate high voltage.

The undershoot generation unit may include a switch configured to select and output one of an input terminal of the gate high voltage and the gate low voltage in response to an undershoot synchronization signal supplied from a timing controller.

The liquid crystal panel is characterized in that two adjacent pixels arranged on one horizontal line are connected to one data line.

The gate driver may include a gate-in-panel structure mounted on one side of the liquid crystal panel in the form of a plurality of thin film transistors.

The liquid crystal display according to the preferred embodiment of the present invention minimizes the delay of the gate discharge time by providing a voltage at a level lower than a conventional gate low voltage among the voltages provided from the power supply to the gate driver at the discharge point of the gate wiring. Therefore, there is an effect that can provide a liquid crystal display device to drive more stably.

FIG. 1 schematically illustrates a structure of a liquid crystal display device of a conventional active matrix type.
2 is a view illustrating some pixels of a liquid crystal display device having a conventional DRD structure.
3 is a diagram illustrating a liquid crystal display and an undershoot generation circuit included in the liquid crystal display according to the exemplary embodiment of the present invention.
4 is a diagram illustrating an undershoot generation circuit and a circuit structure connected thereto of the liquid crystal display according to the exemplary embodiment of the present invention.
5 is a diagram illustrating a signal waveform by an undershoot generation circuit of a liquid crystal display according to an exemplary embodiment of the present invention.
6 illustrates a signal waveform of a gate driving signal according to a gate clock signal of the liquid crystal display according to the exemplary embodiment of the present invention.

Hereinafter, a liquid crystal display according to a preferred embodiment of the present invention will be described with reference to the drawings.

3 is a diagram illustrating a liquid crystal display and an undershoot generation circuit included in the liquid crystal display according to the exemplary embodiment of the present invention.

As shown, the liquid crystal display device of the present invention, the liquid crystal display device according to an embodiment of the present invention, the liquid crystal panel 100 for displaying an image, and the image signal and control signal applied from an external system for each driving circuit A timing controller 110 to be supplied to the gate controller, a gate driver 120 provided on one side of the liquid crystal panel 100 to apply the gate driving voltage VG to the gate wiring GL, and a data voltage VDATA to each pixel. Is applied to the data driver 130, the level shifter 140 providing a plurality of voltages for generating the gate driving voltage VG to the gate driver 130, and the voltage applied to the level shifter 140. The undershoot generation unit 150 may switch a portion to insert an undershoot section into the gate driving voltage.

In the liquid crystal panel 100, a plurality of gate lines GL and a plurality of data lines DL are intersected in a matrix form on a substrate using a glass, and a plurality of pixels are defined at intersections. In the display area of the liquid crystal panel 100, a plurality of pixels corresponding to the three primary colors of R, G, and B are formed in a matrix form, and each pixel includes at least one thin film transistor T and a liquid crystal capacitor LC, thereby forming an image. Will be displayed.

The gate electrode of the above-described thin film transistor T is connected to the gate line GL, the source electrode is connected to the data line DL, and the drain electrode is connected to the pixel electrode opposite to the common electrode to form one pixel. define. Amorphous silicon is widely used as a material forming the active layer of the thin film transistor T, but a gate-in-panel in which a gate driver 120 to be described later is mounted on one side of the liquid crystal panel 100 is used. In the liquid crystal display (GIP) structure, the active layer of the thin film transistor T may be made of polysilicon.

In particular, in the liquid crystal display of the present invention, a DRD structure is applied, and neighboring pixels arranged on the same horizontal line in the display area are connected to different data wires on the same vertical line formed on the same data line DL. do.

The timing controller 110 may provide a digital image signal RGB transmitted from an external system and timing signals such as a horizontal sync signal Hsync, a vertical sync signal Vsync, and a data enable signal DE, although not shown. When applied, the control signals of the gate driver 120 and the data driver 130 and the clock signals of the level shifter 140 and the undershoot generator 150 are generated.

For example, the gate control signal GCS provided by the timing controller 110 to the gate driver 120 may include a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable. (Gate Output Enable, GOE).

The data control signal DCS provided to the data driver 130 by the timing controller 110 includes a source start pulse SSP, a source shift clock SSC, and a source output enable Source Output Enable (SOE).

The timing controller 110 may further include a clock signal CLK for controlling the output of the level shifter 140 and an undershoot control signal for defining a section in which an undershoot is generated in the output signal of the level shifter 140. FLK).

In addition, the timing controller 110 receives the image signal RGB through a normal interface, and supplies the input image signal RGB in a form that the data driver 130 can process.

The gate driver 120 outputs the gate driving voltage VG through the gate wiring GL formed on the liquid crystal panel 100 in response to the gate control signal GCS input from the timing controller 110 described above in the normal mode. However, the gate high voltage VGH is sequentially output for each horizontal period 1H which is reduced by 1/2 compared with the conventional art. Accordingly, the thin film transistor T connected to the corresponding gate wiring GL is turned on, and at the same time, the data driver 130 controls the data voltage VDATA of the supplied analog waveform to the data wiring DL. Through the applied to the pixels connected to the thin film transistor (T).

In addition, the gate driver 120 outputs the gate high voltage VGH to the rear gate line GL immediately after the gate high voltage VGH is applied to the predetermined gate line GL for one horizontal period 1H. Previously, the first gate low voltage VGL1 having a lower voltage level than the second gate low voltage VGL2 which is a normal voltage level is output to the front gate gate GL.

Here, the gate high voltage VGH is about 23 V and the gate low voltage VGL is about -6 V, whereas the gate low voltage VGL is at least higher than that in the above-described undershoot period. Output is at low voltage level (-10V or less). This is a voltage level at which the first gate low level VGL1 of the gate clock signal output by the level shifter 140 is lower than the second gate low voltage VGL having the same voltage level as before, and thus the front gate wiring GL As the undershoot is generated to discharge the front gate line GL at a high speed, the insufficient gate line discharge period for DRD driving can be secured.

The data driver 130 converts the sorted digital image signal RGB input in response to the data control signal DCS input from the timing controller 110 into an analog data voltage VDATA according to a reference voltage. do. The data voltage VDATA is latched by one horizontal line and is simultaneously output to the liquid crystal panel 100 through all the data lines DL in one horizontal period 1H.

The level shifter 140 receives the gate high voltage VGH and the first and second gate low voltages VGL1 and VGL2 from a power supply unit (not shown) and the undershoot generation unit 150. The gate driver 120 generates a gate clock signal GCLK that swings between the gate high voltage VGH and the first and second gate low voltages VGL1 and VGL2 in synchronization with the clock signal CLK output from the 110. )

Here, the first and second gate low voltages VGL1 and VGL2 are provided to the level shifter 140 by the undershoot generation unit 150 selectively corresponding to the undershoot synchronization clock signal FLK. The unit 140 sequentially outputs the gate high voltage VGH and the first and second gate low voltages VGL1 and VGL2 within one horizontal period 1H. Here, the first gate low voltage VGL1 is a voltage having a lower level than the second gate low voltage VGL2 and is output correspondingly within the high level section of the undershoot synchronization clock signal FLK described above.

The undershoot generator 150 receives the first and second gate low voltages VGL1 and VGL2 from the power supply unit (not shown) in synchronization with the undershoot synchronization clock signal FLK applied from the timing controller 110. The first and second gate low voltages VGL1 and VGL2 are selectively output to the level shifter 140. To this end, the undershoot generation unit 150 may include a switch for selecting any one of the two gate low voltages VGL1 and VGL2 supplied.

According to the above structure, the liquid crystal display and the undershoot generating circuit thereof according to the present invention insert the undershoot section during the period in which the gate driving voltage output from the gate driver 120 transitions from the high level to the low level. The discharge of the GL is performed quickly.

Hereinafter, an undershoot generation circuit and a circuit structure connected thereto will be described in the liquid crystal display according to the exemplary embodiment of the present invention with reference to the drawings.

4 is a diagram illustrating an undershoot generation circuit and a circuit structure connected thereto of the liquid crystal display according to the exemplary embodiment of the present invention.

Referring to the drawings, the liquid crystal display according to the present invention includes a timing controller 110 for generating various control signals, a gate driver 120 connected to gate lines GL N and GL N + 1 formed on the liquid crystal panel, and an output terminal. ), A level shifter 140 for supplying the gate clock signal GCLK to the gate driver 120, and an undershoot generator 150 for selectively supplying at least two gate low signals to the level shifter 140. ).

The timing controller 110 defines a section in which an undershoot is generated in the clock signal CLK for controlling the output of the level shifter 140 and the gate clock signal GCLK, which is an output signal of the level shifter 140. The undershoot control signal FLK is generated.

The gate driver 120 outputs the gate driving signal through the gate lines GL N and GL N + 1 in response to the gate clock signal GCLK supplied by the level shifter 140.

The gate driver 120 is a shift register formed of a plurality of thin film transistors formed on a non-display area of a liquid crystal panel. As an equivalent circuit diagram, two AND gates A1 and A2 are connected to an S input terminal and an R input terminal. Although the pull-down transistors Th and Tl may be represented as RS flip-flops 121 and 122 connected to the Q output terminal and the QB output terminal, the gates of one gate line GL N for one horizontal period rather than the illustrated structure may be represented. A shift register having any structure that outputs a high voltage and outputs a gate low voltage for the remaining gate lines GL N + 1 can be replaced.

Referring to FIG. 4, in the gate wirings G LN and GL N + 1, pull-up and pull-down transistors Th and Tl are connected, respectively, and pull-up. And gates of the pull-down transistors Th and Tl are connected to the Q output terminal and the Qb output terminal of the first flip-flop 121 and the second flip-flop 122, respectively. In addition, a first AND gate A1 and a second AND gate A2 are connected to the S and R input terminals of the first and second flip-flops 121.

Sources of the two pull-up transistors Th are respectively connected to the level shifter 140 to receive the gate clock signal GCLK, and the drain of the pull-up transistor Th and the source of the pull-down transistor Tl. Is connected to the gate lines GL N and GL N + 1. The drains of the two pull-down transistors Tl are grounded. In addition, a start signal VST and other clock signals (not shown) are input to the AND gates A1 and A2 connected to the S and R input terminals of the two flip-flops 121 and 122.

According to this structure, when the high level start signal VST and the low level other clock signal are inputted to the first AND gate A1 of the gate driver 120, the S and R input terminals of the flip-flop 121 are respectively provided. Since the low signal is applied, the flip-flop 121 maintains the previous state and outputs a high level signal at the Q output terminal and a low level signal at the Qb terminal. Accordingly, the pull-up transistor Th is turned on and the pull-down transistor Tl is turned off. In this case, the gate clock signal GCLK is the second gate low voltage VGL2 and the gate driving voltage of the Nth gate line GL N is the second gate low voltage VGL2.

Next, when the gate clock signal GCLK becomes the gate high voltage VGH while the start signal VST maintains the high level, the gate clock signal GCLK is output through the turned-on pull-up transistor Th. The gate driving voltage VG applied to the gate line GL N becomes the gate high voltage VGH.

Subsequently, when the gate clock signal GCLK reaches the first gate low voltage VGL1, the Nth gate line GL N starts to be discharged, and the first gate low voltage VGL1 is a normal low level voltage. Since the voltage level is lower than the two-gate low voltage VGL2, the battery discharges faster.

Next, a low level signal is output from the Q output terminal and a low level signal is output from the Qb terminal to maintain the N + 1 gate line GL N + 1 in a low level state, and the second flip-flop 122 The Q output stage outputs a high level signal, and the Qb stage outputs a low level signal. Accordingly, the pull-up transistor Th is turned on and the pull-down transistor Tl is turned off. When the gate clock signal GCLK becomes the gate high voltage VGH again, the gate clock signal GCLK is output through the turned-on pull-up transistor Th, so that the gate driving applied to the N + 1 th gate line GL N + 1 is performed. The voltage VG becomes the gate high voltage VGH.

The level shifter 140 receives the gate high voltage VGH directly from a power supply (not shown), and selectively selects the first and second gate low voltages VGL1 and VGL2 from the undershoot generator 150. Supplied by. The level shifter 140 swings a gate clock between the gate high voltage VGH and the first and second gate low voltages VGL1 and VGL2 in synchronization with the clock signal CLK output from the timing controller 110. The signal GCLK is generated and output to the gate driver 120.

The undershoot generator 150 may input a second gate low voltage VGL2 of a normal gate low voltage level and a first gate low voltage VGL1 of at least a lower voltage level from a power supply unit (not shown). Each one is supplied through the switch and outputs to the level shifter 140 through a switch for selectively outputting any one of the voltages applied to the input terminal according to the undershoot synchronization clock signal FLK.

Hereinafter, the driving method of the liquid crystal display device of the present invention will be described with reference to the signal waveform by the undershoot generation circuit described above. 5 is a diagram illustrating a signal waveform by an undershoot generation circuit of a liquid crystal display according to an exemplary embodiment of the present invention.

4 and 5, the timing controller 110 generates a clock signal CLK for controlling the level shifter 140 and an undershoot synchronization clock signal FLK for controlling the undershoot generator 150. The clock signal CLK is a signal defining one horizontal period 1H, which is a high level gate driving signal VG output period of the gate wirings GL N and GL N + 1, and an undershoot synchronization clock signal ( FLK is a signal defining the time of generation of the first gate low signal VGL1.

Here, since the gate high voltage VGH and the first gate low voltage VGL1 are signals having a large difference in voltage level, the gate high voltage VGH and the gate high voltage VGL1 may be delayed when switching between them. Thus, the undershoot synchronization clock signal FLK is clocked. Rather than the point at which the signal CLK transitions to the falling edge at the rising edge, it must be applied at a high level before this point in time. Accordingly, sufficient time is ensured when switching to the first gate low voltage VGL1.

In addition, the undershoot generation unit 150 supplies the first and second gate low voltages VGL1 and VGL2 to the level shifter 140 alternately in synchronization with the undershoot synchronization clock signal FLK. As shown in FIG. 5, when the undershoot synchronization clock signal FLK is at a high level, the gate low voltage applied to the level shifter 140 outputs the first gate low voltage VGL1, and the undershoot synchronization clock signal. When FLK is at the low level, the second gate low voltage VGL2 is alternately modulated and output as a signal VGLM.

Accordingly, the level shifter 140 outputs the gate high voltage VGH in the high level section of the clock signal CLK, and the first gate low voltage VGL1 and the first gate in the low level section of the clock signal CLK. The two gate low voltage VGL2 is sequentially output.

Here, the second gate low voltage VGL2 is output in synchronization with the falling edge of the undershoot synchronization clock signal FLK.

6 illustrates a signal waveform of a gate driving signal according to a gate clock signal of the liquid crystal display according to the exemplary embodiment of the present invention.

As shown in the drawing, when the first gate low voltage VGL1 is -10 V and the second gate low voltage VGL2 is -6 V, the gate clock signal GCLK has an undershoot period c at the falling edge. ) Is inserted. Accordingly, after the undershoot period c, the gate driving signal reduces the discharge time by a maximum d as compared with the conventional art.

While a number of embodiments have been described in detail above, it should be construed as being illustrative of preferred embodiments rather than limiting the scope of the invention. Therefore, the invention should not be construed as limited to the embodiments described, but should be determined by equivalents to the appended claims and the claims.

100: liquid crystal panel 110: timing control unit
120: gate driver 130: data driver
140: level shifter 150: undershoot generating unit
GL: Gate wiring DL: Data wiring
VGH: Gate high voltage VGL1: First gate low voltage
VGL2: Second Gate Low Voltage

Claims (8)

A liquid crystal panel in which a plurality of gate wirings and data wirings are formed in a matrix form and define pixels at intersection points;
A gate driver supplying a gate driving voltage to the gate wiring;
A data driver supplying a data voltage to the data line;
A level shift unit including a gate high voltage and a gate low voltage, and supplying a gate clock signal for generating the gate driving voltage to the gate driver;
An undershoot generator for supplying the gate low voltage to the level shift unit to have two or more different voltage levels to insert an undershoot section into the gate driving voltage;
And the liquid crystal display device. The method according to claim 1,
The gate low voltage is divided into first and second gate low voltages having different voltage levels,
And the second gate low voltage is at least lower than the first gate low voltage. 3. The method of claim 2,
The gate driving voltage is,
And wherein the voltage level is the second gate low voltage in the undershoot period. 3. The method of claim 2,
The gate clock signal is,
And a high level section and a low level section correspond to the high level section and the low level section of the clock signal supplied from the timing controller. The method according to claim 1,
The undershoot section,
And a corresponding output point corresponding to the falling edge of the gate high voltage. The method according to claim 1,
The undershoot generating unit,
And a switch for selecting and outputting any one of input terminals of the gate high voltage and the gate low voltage in response to an undershoot synchronization signal supplied from a timing controller. The method according to claim 1,
In the liquid crystal panel,
And two adjacent pixels arranged on one horizontal line are connected to one data line. The method according to claim 1,
And the gate driver is a gate-in-panel structure mounted on one side of the liquid crystal panel in the form of a plurality of thin film transistors.

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