KR20170061590A - Display device and driving method of the same - Google Patents

Abstract

A display device according to the present invention includes a timing controller, a level shifter, and an output enable signal control unit.
The timing controller is turned on by the first logic voltage VCC25 and is switched from the floating state to the normal operation state by the reset signal RST after the switching period Tc Thereby generating timing control signals Tsig.
The level shifter receives the first logic voltage VCC25 and the second logic voltage VCC33 and level-shifts the timing control signals Tsig to the second logic voltage VCC33.
The output enable signal control unit is synchronized with the reset signal to output the output enable signal OE as the activation level LOW or the inactive level HIGH.
The level shifter receives the output enable signal OE as the deactivation level during the switching period Tc to stop level shifting.

Description

DISPLAY DEVICE AND DRIVING METHOD OF THE SAME [0002]

The present invention relates to a display device and a driving method thereof.

Display devices include liquid crystal displays (LCDs) including liquid crystals, and OLED display devices including organic light emitting diodes (OLEDs). OLED displays and LCDs are used in many fields ranging from small to large, such as mobile phones, notebooks, monitors, and TVs.

The display device includes a display panel in which a plurality of pixels are arranged in a matrix form, a gate driver for driving gate lines of the display panel, a data driver for driving data lines of the display panel, a timing controller And the like. Here, the gate driver may be embedded in the display panel to reduce its volume and weight, which is referred to as a GIP (Gate In Panel) type display device.

In the GIP type display device, the timing control section includes a timing controller (TCON) for generating timing control signals and a level shifter (LS) for outputting a plurality of gate drive control signals to be supplied to the gate driver using timing control signals. timing

1, the timing controller TCON receives the first logic voltage VCC25, generates timing control signals, and supplies the timing control signals to the level shifter LS. For example, the first logic voltage VCC25 may be 2.5V. The timing control signals are always supplied to the level shifter LS until the first logic voltage VCC25 input to the timing controller TCON falls to 2.5 V or less.

The timing controller TCON is supplied with a reset signal RST output from a reset IC (Integrated Circuit). The reset signal RST is input to the timing controller TCON at the initial stage of driving to switch the timing controller TCON from the floating state to the normal operation state. Specifically, at the beginning of the driving, the timing controller TCON receives the first logic voltage VCC25 of 2.5 V and turns on. However, unstable timing control signals remain in a floating state output from the timing controller TCON. Then, the timing controller TCON receives the reset signal RST after a predetermined period of time to prevent the output signals of the floating state from operating in an abnormal state.

This period is a period during which the timing controller TCON is turned on after inputting the first logic voltage VCC25 of 2.5 V until the reset signal RST is received Period Tc "). This switching period Tc is a period of time taken for switching from the floating state to the normal operating state of the timing controller TCON.

The level shifter LS uses the first logic voltage VCC25 as the input power source and the second logic voltage VCC33 as the output power source to generate the timing control signals Tsig input from the timing controller TCON Level-shifted to 3.3V and then output. Further, the level shifter LS receives the output enable signal OE and activates level shifting.

The output enable signal OE serves as an input and an output for activating the level shifter LS normally (that is, the output enable signal OE is low) and the level shifter LS (I.e., the output enable signal OE is in a high state).

Since the output enable signal OE in the conventional level shifter LS is fixed at the activation level LOW (that is, the enable terminal EN is connected to the base power supply), the input power supply VCC25, And the output power supply VCC33 are normally applied, there is a problem of level shifting to an abnormal signal outputted from the Floating state of the timing controller TCON.

In addition, an abnormal signal outputted from the floating state of the timing controller TCON at the initial stage of driving is coupled with adjacent signals to cause a glitch. At this time, since the level shifter LS is always in the output-enabled state, the level shifter LS performs level shifting to an abnormal signal due to the glitch. If an abnormal signal is input to the system or the panel driving circuit, the display device malfunctions.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a display device and a method of driving the same that can remove an abnormal signal generated in a floating state of a timing controller at the initial stage of driving, from a level shift.

According to an aspect of the present invention, a display apparatus includes a timing controller, a level shifter, and an output enable signal controller.

The timing controller is turned on by the first logic voltage VCC25 and is switched from the floating state to the normal operation state by the reset signal RST after the switching period Tc Thereby generating timing control signals Tsig.

The level shifter receives the first logic voltage VCC25 and the second logic voltage VCC33 and level-shifts the timing control signals Tsig to the second logic voltage VCC33.

The output enable signal control unit is synchronized with the reset signal to output the output enable signal OE as the activation level LOW or the inactive level HIGH.

The level shifter receives the output enable signal OE as the deactivation level during the switching period Tc to stop level shifting.

The display device according to another embodiment of the present invention includes a timing controller which is operated according to the reset signal RST to generate timing control signals Tsig of the first logic voltage VCC25 level, timing control signals Tsig (VCC33) level higher than the first logic voltage (VCC25) level, and outputs a level shifter and a second logic voltage (VCC33) in which a level shifting operation is activated according to an output enable signal The output enable signal OE is controlled to the inactive level HIGH during the switching period Tc from when the reset signal RST is applied to the ON level until the reset signal RST is applied to the ON level, And an output enable signal control unit for controlling the output enable signal OE to the activation level LOW after the output enable signal Tc.

The driving method of the display device according to the embodiment of the present invention further includes the steps of generating timing control signals Tsig of the first logic voltage (VCC25) level by being operated according to the reset signal RST, Shifting the second logic voltage (Tsig) to a second logic voltage (VCC33) level higher than the first logic voltage (VCC25) level and activating a level shifting operation according to an output enable signal (OE) The output enable signal OE is controlled to the inactivation level HIGH during the switching period Tc after the voltage VCC33 is applied at the ON level until the reset signal RST is applied at the ON level, And controlling the output enable signal OE to the activation level LOW after a predetermined period of time Td.

The present invention controls an output enable signal input to a level shifter for a predetermined period during which an abnormal signal (glitch or the like) can be generated to a non-active level, thereby stopping the operation of the level shifter during the predetermined period and outputting an abnormal signal Prevent in advance. Accordingly, it is possible to prevent an erroneous operation of the display device by removing an abnormal waveform generated in a floating state of the timing controller at the initial stage of driving.

FIG. 1 is a waveform diagram showing an abnormal signal outputted from a level shifter in a floating state of a timing controller in a conventional display device. FIG.
2 is a block diagram showing a display device according to an embodiment of the present invention;
FIG. 3 is a waveform diagram showing signals input to the timing controller and level shifter of the present invention, and output signals of the level shifter accordingly. FIG.
FIG. 4 shows an output enable signal control unit for outputting an output enable signal OE in an active level (LOW) or inactive level (HIGH) in synchronization with a reset signal.
5 is a flowchart showing a driving method of a display device according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In the following description, the display device will be described mainly on the liquid crystal display device, but it should be noted that the technical idea of the present invention is not limited to the liquid crystal display device but can be applied to other display devices.

Specific examples of such a display device include a liquid crystal display device (LCD), a plasma display panel (PDP), a field emission display device (FED), an organic light emitting display device Organic Light Emitting Display Device (OLED).

In particular, an organic light emitting display includes a plurality of pixels, each of the plurality of pixels includes an organic light emitting element composed of an organic light emitting layer between the anode and the cathode, and a pixel driving circuit independently driving the organic light emitting element. The pixel driving circuit includes a switching thin film transistor (hereinafter referred to as TFT), a driving TFT, and a capacitor. Here, the switching TFT charges the data voltage in the capacitor in response to the scan pulse, and the driving TFT controls the amount of current supplied to the organic light emitting element according to the data voltage charged in the capacitor to control the amount of light emitted from the organic light emitting element.

The display device of the present invention may be implemented in any known liquid crystal mode such as TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In Plane Switching) mode, FFS (Fringe Field Switching) In addition, the display device of the present invention can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, a reflective liquid crystal display device, and the like. FIG. 2 shows a display device according to an embodiment of the present invention. FIG. 3 shows waveforms of signals input to the timing controller and the level shifter of the present invention, and output signal waveforms of the level shifter. 4 shows an output enable signal control unit for outputting an output enable signal OE in an active level LOW or inactive level HIGH in synchronization with a reset signal.

2 to 4, a display device 10 according to the present invention includes a display panel 11, a data driving circuit 12, a gate driving circuit 13, a timing controller 14, a level shifter 16, And an output enable signal control unit (OECP) 17.

The display panel 11 includes data lines and gate lines which intersect with each other, and pixels arranged in a matrix form.

The display panel 11 includes an upper substrate and a lower substrate opposed to each other with the liquid crystal cell Clc therebetween. In the display panel 11, a pixel array including pixels arranged in a matrix form is formed, and an input image is displayed on the pixel array. The pixel array includes a TFT array formed on the lower substrate and a color filter array formed on the upper substrate. In a TFT array, TFTs (Thin Film Transistors) are formed at intersections of data lines and gate lines. The TFT supplies the data voltage from the data line to the pixel electrode 1 of the liquid crystal cell Clc in response to the gate pulse from the gate line. Each of the liquid crystal cells Clc realizes a desired gradation by controlling the light transmittance by the potential difference between the data voltage charged in the pixel electrode 1 and the common voltage Vcom applied to the common electrode 2. [ In the liquid crystal cell Clc, a storage capacitor Cst for holding the data voltage charged in the pixel electrode 1 for one frame period is connected. The color filter array includes a color filter and a black matrix. On the upper glass substrate and the lower glass substrate of the display panel 11, a polarizing plate is attached and an alignment film for setting a pre-tilt angle of the liquid crystal is formed.

The data drive circuit 12 may be implemented as a source drive IC. The data driving circuit 120 receives the digital video data RGB from the timing controller 14. The data driving circuit 12 converts the digital video data RGB to a gamma compensation voltage in response to the data driving control signals DDC from the timing controller 14 to generate a data voltage, And supplies them to the data lines DL of the display panel 11 in synchronization with the pulses. The data driving circuit 12 may be connected to the data lines DL of the display panel 11 by a COG (Chip On Glass) process or a TAB (Tape Automated Bonding) process.

The gate driving circuit 13 may be formed directly on the lower substrate of the display panel 11 by a GIP (Gate In Panel) method. The gate drive circuit 13 may be formed in a non-display area outside the pixel area where an image is displayed on the display panel 11. [ The gate drive circuit 13 may be implemented as a gate drive IC and connected to the gate lines of the display panel 11 by a TAB (Tape Automated Bonding) process. The gate drive circuit 13 generates gate pulses in response to the gate drive control signals GDC from the timing controller 14 and supplies the gate pulses to the gate lines GL in a line sequential manner. One horizontal line to be charged with the data voltage according to the gate pulse is selected.

2, the timing controller 14 receives digital video data RGB from the host system 15 and receives a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, a data enable signal Data Enable, DE, and a dot clock (CLK). The timing controller 14 transmits the digital video data RGB to the source drive ICs of the data driving circuit 120. The timing controller 14 uses the timing signals Vsync, Hsync, DE and CLK to control the data drive control signals DDC for controlling the operation timings of the source drive ICs and the operation timing of the gate drive circuit 13 And generates gate drive control signals (GDC) for control.

The data driving control signals DDC include a source start pulse SSP, a source sampling clock SSC and a source output enable SOE, a polarity control signal < RTI ID = 0.0 > POL) and the like. The source start pulse SSP and the source sampling clock SSC control the sampling timing of the data. The polarity control signal POL controls the polarity inversion timing of the data voltage output from the data driving circuit 12. [ The source output enable signal SOE controls the output timing of the data driving circuit and the charge share timing.

The gate drive control signals GDC include a gate start pulse (GSP), a gate shift clock (GSC), and the like. The gate start pulse (GSP) controls the timing of the first gate pulse. The gate shift clock GSC is a clock signal for shifting the gate start pulse GSP.

The timing controller 14 receives the first logic voltage VCC25 and generates timing control signals Tsig and supplies the timing control signals Tsig to the level shifter 16. [ The timing control signals Tsig include a gate modulation signal (FLK in Fig. 4) for controlling the modulation timing of the gate pulse, a power supply enable signal (DPM in Fig. 4) for controlling generation timings of various power supplies applied to the panel driving circuit, A ready signal (DPX in FIG. 4) for informing the host system 15 that the data is ready to be transmitted, and the like.

Referring to FIGS. 2 and 3, the timing controller 140 receives the first logic voltage VCC25 and is turned on at the initial stage of the driving. However, unstable timing control signals remain in a floating state output from the timing controller 14. [ Then, the timing controller 14 receives the reset signal RST from the reset IC (Integrated Circuit) after the switching period Tc and is switched to the normal operation state. That is, the timing controller 14 maintains the floating state at the initial stage of driving until the reset signal RST is turned on. The operation of the timing controller TCON is normally performed after the reset signal RST is turned on.

 The timing at which the timing controller 14 actually starts generating the timing control signals Tsig is not the timing at which the first logic voltage VCC25 is applied at the ON level but the reset signal RST is at the ON level . The timing controller 14 is in the floating state until the reset signal RST is applied to the on level even if the first logic voltage VCC25 is applied at the ON level.

The reset signal RST output from the reset IC may be embedded in the host system 15 or may be mounted on the control board 18. [

The level shifter 16 uses the first logic voltage VCC25 as the input power and the second logic voltage VCC33 higher than the first logic voltage VCC25 as the output power source, (Level shifting) the timing control signals Tsig to the second logic voltage (VCC33) level higher than the first logic voltage (VCC25) level. The level shifter 16 supplies gate driving control signals GDC among the boosted timing control signals Tsig to the gate driving circuit 13 and the remaining boosted timing control signals Tsig are supplied to the host system 15 . The first logic voltage VCC25, which is the input power of the level shifter 16 and the timing controller 14, may be 2.5 V, but is not limited thereto. The second logic voltage VCC33, which is the output power of the level shifter 16, may be 3.3 V, but is not limited thereto.

The operation of the level shifter 16 is controlled in accordance with the output enable signal OE input to the enable terminal EN of the level shifter 16. [ The output enable signal OE is an enable signal for enabling the level shifter 16 to operate normally (that is, the output enable signal OE is in a low state) and the level shifter 16 serving as inputs and outputs (I.e., the output enable signal OE is in a high state).

2, the output enable signal OE applied from the output enable signal controller 17 is fixed to the activation level LOW (that is, the enable terminal EN is connected to the base power source .

The output enable signal OE applied from the output enable signal controller 17 is set to a logic level after the second logic voltage VCC33 is applied at the ON level as shown in FIG. 3 until the reset signal RST is applied to the ON level The output enable signal OE is controlled to the inactive level HIGH and the output enable signal OE is controlled to the activation level LOW after the switching period Tc during the switching period Tc . The output enable signal control unit 17 controls the output enable signal OE to the inactive level HIGH during the switching period Tc during which an abnormal signal (glitch or the like) The operation of the level shifter 16 is stopped and the output of the abnormal signal is prevented in advance. Therefore, the switching period Tc can be an abnormal signal output preventing period.

When the first logic voltage VCC25 is raised to the on level within the switching period Tc in which the timing controller 14 is in the floating state at the beginning of the driving, the unstable timing control signals Tsig are output from the timing controller 14 And then the Abnormal Signal may cause a glitch by coupling with other nearby signals. At this time, the level shifter 16 is controlled to the deactivation level (High) by the output enable signal OE, and becomes the output disable state. Therefore, the unstable timing control signals Tsig output from the timing controller 14 are cut off from the level shifter 16 by an abnormal signal due to glitch or the like. Here, the timing at which the second logic voltage VCC33 is applied at the ON level (the start timing of the switching period Tc) is set so that the timing at which the first logic voltage VCC25 is applied at the ON level (the glitch induction Timing may be faster than the predetermined time Tx.

Under the control of the output enable signal controller 17, the level shifter 16 outputs the timing control signals Tsig during the switching period Tc in response to the output enable signal OE of the inactive level HIGH Stops the level shifting operation and the output operation. The level shifter 16 starts the level shifting operation and the output operation for the timing control signals Tsig after the switching period Tc in response to the output enable signal OE of the activation level LOW.

Referring to FIG. 4, the output enable signal controller 17 can control the logic level of the output enable signal OE based on the reset signal RST. To this end, the output enable signal controller 17 includes a switch element SS and a resistor R as shown in FIG.

The switch element SS includes a control electrode Ea connected to the input terminal of the reset signal RST, a first electrode Eb connected to the first node N1 outputting the output enable signal OE, And a second electrode Ec connected to the ground GND. The switch element SS may be implemented as a field effect transistor (FET) or a bipolar junction transistor (BJT).

The resistor R is connected between the input terminal of the second logic voltage VCC33 and the first node N1.

The output enable signal controller 17 blocks the electrical flow between the first node N1 and the ground voltage source GND by using the switch element SS when the reset signal RST is input at the off level, 2 logic voltage VCC33 to the output enable signal OE. That is, the output enable signal controller 17 outputs the output enable signal OE at the inactive level HIGH during the switching period Tc during which the reset signal RST is input at the off level.

The output enable signal controller 17 allows the electric current flow between the first node N1 and the ground voltage source GND using the switch element SS when the reset signal RST is input at the ON level, And outputs the logic voltage VCC33 as the base voltage. That is, the output enable signal controller 17 outputs the output enable signal OE to the activation level LOW after the switching period Tc in which the reset signal RST is input to the ON level.

2, the timing controller 14, the level shifter 16, and the output enable signal controller 17 may be mounted on the control board 18. [

5 shows a method of driving a display device according to an embodiment of the present invention.

Referring to FIG. 6, a method of driving a display device according to an embodiment of the present invention includes generating timing control signals Tsig of a first logic voltage (VCC25) level by being operated according to a reset signal RST, Shifting the timing control signals Tsig to a second logic voltage (VCC33) level that is higher than the first logic voltage (VCC25) level and outputting the shifted timing control signals (Tsig), and activating the level shifting operation according to the output enable signal , The output enable signal OE is set to the inactive level HIGH during a certain period of time Td after the second logic voltage VCC33 is applied at the ON level until the reset signal RST is applied at the ON level (S1, S2, S5) the output enable signal OE to the activation level LOW after the switching period Tc after the control (S1, S2, S3).

Here, the step of activating the level shifting operation in accordance with the output enable signal OE may be performed in response to the output enable signal OE of the inactive level HIGH during the switching period Tc, (Step S4).

The step of activating the level shifting operation in accordance with the output enable signal OE may include switching the timing control signals Tsig from the switching period Tc in response to the output enable signal OE of the activation level LOW The level shifting operation and the outputting operation are started (S6).

As described above, the present invention controls the output enable signal input to the level shifter during the switching period Tc during which the abnormal signal (glitch, etc.) can be induced to the inactive level, The operation of the shifter is stopped and the output of the abnormal signal is prevented in advance. Accordingly, it is possible to prevent the malfunction of the display device by removing an abnormal signal generated in the floating state of the timing controller at the initial stage of driving.

The technical idea of the present invention can be applied to other ICs that operate normally after a floating state is maintained for a certain period of time in the initial stage of driving in addition to the timing controller.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: Display panel TCON: Timing controller
12: data driving circuit 13: gate driving circuit
14: Control board 15: Host system
LS: Level shifter SWP:

Claims (17)

Is turned on by the first logic voltage VCC25 and is switched from the floating state to the normal operation state by the reset signal RST after the switching period Tc, A timing controller 14 for generating control signals Tsig;
A level shifter receiving the first logic voltage VCC25 and the second logic voltage VCC33 and level-shifting the timing control signals Tsig to the second logic voltage VCC33, 16); And
And an output enable signal controller (17) for outputting an output enable signal (OE) in synchronization with the reset signal at an activation level (LOW) or a deactivation level (HIGH)
Wherein the level shifter receives the output enable signal (OE) as a deactivation level during the switching period (Tc) and stops level shifting. The method according to claim 1,
The timing controller 14 outputs an Abnormal signal during the switching period Tc and is coupled with (coupled to) peripheral signals to generate a glitch. The method according to claim 1,
The level shifter 16 receives the output enable signal OE at an activation level after the switching period Tc and level-shifts the timing control signals to the second logic voltage and outputs the shifted level control signals. The method of claim 3,
Wherein a part of the level shifted timing control signals are supplied to the gate driving circuit and the remaining control signals are supplied to the host system 15. [ The method according to claim 1,
The output enable signal controller 17 includes a switching element and a resistor for controlling the level of the output enable signal. 6. The method of claim 5,
Wherein the switching element includes a first electrode receiving the reset signal, a second electrode outputting the output enable signal, and a third electrode coupled to the base voltage source. The method according to claim 6,
And the second electrode is connected in series with the resistor and the second logic voltage (VCC33) input. A timing controller which is operated in accordance with a reset signal RST to generate timing control signals Tsig of a first logic voltage (VCC25) level;
Shifting the timing control signals Tsig to a second logic voltage (VCC33) level that is higher than the first logic voltage (VCC25) level, and outputting the shifted logic level according to an output enable signal (OE) Level shifter; And
The output enable signal OE is set to the inactive level HIGH during the switching period Tc from when the second logic voltage VCC33 is applied to the ON level until the reset signal RST is applied to the ON level And an output enable signal control unit for controlling the output enable signal OE to an activation level LOW after the switching period Tc. 9. The method of claim 8,
The level shifter LS stops level shifting and outputting the timing control signals Tsig during the switching period Tc in response to the output enable signal OE of the inactivation level HIGH Display device. 9. The method of claim 8,
Wherein the level shifter starts level shifting and outputting for the timing control signals Tsig after the switching period Tc in response to the output enable signal OE of the activation level LOW. 9. The method of claim 8,
The timing at which the second logic voltage VCC33 is applied to the on level is faster than the timing when the first logic voltage VCC25 is applied to the on level. 9. The method of claim 8,
The output enable signal controller 17,
A control electrode Ea connected to an input terminal of the reset signal RST and a first electrode Eb connected to a first node N1 outputting the output enable signal OE, A switch element SS including a second electrode Ec connected thereto, and
And a resistor (R) connected between an input terminal of the second logic voltage (VCC33) and the first node (N1). 13. The method of claim 12,
The switching device SS is implemented by a field effect transistor (FET) or a bipolar junction transistor (BJT). Operating in accordance with a reset signal (RST) to generate timing control signals (Tsig) at a first logic voltage (VCC25) level;
Shifting the timing control signals Tsig to a second logic voltage (VCC33) level that is higher than the first logic voltage (VCC25) level, and outputting the shifted logic levels according to an output enable signal (OE) step; And
The output enable signal OE is set to the inactive level HIGH during the switching period Tc from when the second logic voltage VCC33 is applied to the ON level until the reset signal RST is applied to the ON level ), And controlling the output enable signal (OE) to an activation level (LOW) after the switching period (Tc). 15. The method of claim 14,
The step of activating the level shifting operation in accordance with the output enable signal (OE)
And stops the level shifting operation and the output operation for the timing control signals Tsig during the switching period Tc in response to the output enable signal OE of the inactive level HIGH. 15. The method of claim 14,
The step of activating the level shifting operation in accordance with the output enable signal (OE)
And starts a level shifting operation and an output operation for the timing control signals (Tsig) after the predetermined period (Td) in response to the output enable signal (OE) of the activation level (LOW). 15. The method of claim 14,
The timing at which the second logic voltage VCC33 is applied to the on level is faster than the timing when the first logic voltage VCC25 is applied to the on level.

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