KR20080046934A - Liquid crystal display and method of driving the same - Google Patents

Abstract

An LCD device and a driving method thereof are provided to prevent overcurrent by synchronizing an analog driving voltage with an output voltage through time delaying. An LCD(Liquid Crystal Display) device includes an LCD panel for displaying images and an LCD driver for driving the LCD panel. The LCD driver includes gate and data drivers(112,114), a timing controller(108), a DC/DC converter(106), and a time delay unit. The gate and data drivers supply gate and data signals to drive the LCD panel. The timing controller supplies output signals. The DC/DC(Direct Current) converter generates an analog driving voltage. The time delay unit delays the analog driving voltage so as to synchronize with the output signals from the DC/DC converter.

Description

Liquid crystal display and its driving method {LIQUID CRYSTAL DISPLAY AND METHOD OF DRIVING THE SAME}

1 is a block diagram illustrating a liquid crystal display according to the present invention.

2 is a detailed circuit diagram illustrating a DC-DC converter according to the present invention.

3 is a view showing an analog drive signal and an output signal according to the present invention.

<Brief description of the drawings of the main parts of the drawings>

102: system 104: power supply

106: DC-DC converter 108: timing controller

110: liquid crystal display panel 112: gate driver

114: data driver 120: time delay circuit

122: pulse generator 124: driving voltage generator

126: PWM IC AVDD: analog drive voltage

TP: Output signal

The present invention relates to a liquid crystal display device and a driving method thereof, and more particularly, to a liquid crystal display device and a driving method thereof for preventing overcurrent from flowing.

In general, a liquid crystal display (LCD) applies an electric field to a liquid crystal material having an anisotropic dielectric constant injected between two substrates, and adjusts the intensity of the electric field to control the amount of light transmitted through the substrate. It is a device that displays an image.

The liquid crystal display device includes a liquid crystal display panel for displaying an image through a liquid crystal cell matrix, a backlight unit for supplying light to the liquid crystal display panel, and a driving circuit for driving the liquid crystal display panel. In the liquid crystal display panel, each liquid crystal cell displays an image by controlling the light transmittance by driving the liquid crystal according to the charging voltage.

The DC-DC converter of the liquid crystal display generates an analog driving voltage, a source voltage, a common voltage, a gamma voltage, a gate-on voltage, and a gate-off voltage by input power and supplies them to each circuit block.

Here, when the output signal provided from the timing controller is not input to the data driver, when the analog driving voltage is input to the data driver first, the data driver continuously latches up and the overcurrent flows. Accordingly, the liquid crystal display has a problem in that a sequential and rising slop of the liquid crystal display may be shaken due to a malfunction, and a burnt may occur.

Accordingly, an aspect of the present invention is to provide a liquid crystal display device and a driving method thereof for preventing overcurrent from flowing.

In order to achieve the above technical problem, a liquid crystal display device according to the present invention includes a liquid crystal display panel for implementing an image, a liquid crystal display device driver for driving the liquid crystal display panel, the liquid crystal display device driver is a liquid crystal display panel Respective gate drivers and data drivers for providing gate and data signals for driving; A timing controller providing an output signal; DC-DC converter for generating an analog drive voltage; And a time delay unit configured to delay an analog driving voltage to synchronize the output signal with the DC-DC converter.

The time delay unit is connected to each other in parallel to the first and second resistors for distributing the reference voltage of the analog driving voltage; A capacitor for stabilizing an input voltage supplied to the second resistor; And a transistor turned on in response to an input voltage input to the second resistor.

The first resistance value is greater than the second resistance value.

The reference voltage is 8 to 13V.

The input voltage input to the second resistor is 0.7V.

In order to achieve the above technical problem, the driving method of the liquid crystal display device according to the present invention comprises the steps of generating an output signal through the timing controller; Generating a plurality of analog driving voltages having different voltages through a DC-DC converter; And delaying the analog driving voltage to be input to the data driver at the same time as the output signal.

The delaying of the analog driving voltage may include distributing a reference voltage using first and second resistors; And turning on in response to the reference voltage when an input voltage input to the second resistor is a reference voltage.

Other technical problems and advantages of the present invention in addition to the above technical problem will be apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 1 to 3.

Referring to FIG. 1, a liquid crystal display according to the present invention includes a liquid crystal display panel 110, a data driver 114 for supplying data to data lines DL1 to DLm of the liquid crystal display panel 110, and a gate. A gate controller 112 for supplying a scan signal to the lines GL1 to GLn, a timing controller for controlling the data driver 114 and the gate driver 112 by using a synchronization signal supplied from the system 102 ( 108, a liquid crystal display driver including a DC-DC converter 108 for generating a voltage supplied to the liquid crystal display panel 110, a power supply 104 providing a driving signal, and transmitting a signal from the outside. System 102 is provided.

The system 102 uses red (R), green (G), and blue (B) data, a clock (CLK), a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), and a Vcc power supply from an image processing apparatus (not shown). Red (R), Green (G), Blue (B) data, clock (CLK), vertical sync signal (Vsync), horizontal sync signal (Hsync), etc. are transmitted to the timing controller. Forward to 103. In this case, a signal transmitted through the system 102 may be a low voltage differential signaling (LVDS) scheme or a retarded swing differential signaling (RSDS) scheme.

The liquid crystal display panel 110 includes a plurality of liquid crystal cells Clc disposed in a matrix at the intersections of the data lines DL1 to DLm and the gate lines GL1 to GLn. Each of the thin film transistors TFT formed in the liquid crystal cell Clc supplies a data signal supplied from the data lines DL1 to DLm to the liquid crystal cell Clc in response to a scan signal supplied from the gate line GL. In addition, a storage capacitor Cst is formed in each of the liquid crystal cells Clc. The storage capacitor Cst is formed between the pixel electrode of the liquid crystal cell Clc and the front gate line, or is formed between the pixel electrode of the liquid crystal cell Clc and the common electrode line to uniformly charge the voltage charged in the liquid crystal cell Clc. Keep it.

The power supply unit 104 receives an input power supply Vcc and supplies power for operating the timing control unit 108 or each driving circuit, as well as a gate-on voltage Von and a gate-off voltage Voff for gate driving. , The common electrode voltage Vcom and the driving voltage VDD are generated.

The data driver 114 converts the digital video data R, G, and B into analog voltages corresponding to the gray scale values in response to the data control signals DCS from the timing controller 108 and the DC-DC converter 106. The analog voltage and the output signal are supplied to the data lines DL1 to DLm. At this time, the analog voltage AVDD and the output voltage TP input to the data driver 114 are synchronized with each other and input at the same time.

The gate driver 112 sequentially supplies scan pulses to the gate lines GL1 to GLn in response to the gate control signal GCS from the timing controller 108 to supply horizontal data to the liquid crystal display panel 110. Select a line.

The timing controller 108 controls the gate control signal GDC and the data driver 114 for controlling the gate driver 112 by using the vertical / horizontal synchronization signal and the clock signal input from the graphic controller of the system 102. A data control signal DCS is generated. Here, the gate control signal GCS for controlling the gate driver 112 includes a gate start pulse (GSP), a gate shift clock (GSC), and a gate output signal (GOE). Etc. are included. The data control signal DCS for controlling the data driver 114 includes a source start pulse (SSP), a source shift clock (SSC), a source output signal (SOC), and a polarity. Signal (Polarity: POL) is included.

The DC-DC converter 106 uses the input voltage VIN input through the system 102 to output the analog driving voltage AVDD, the source voltage VSS, the turn-on voltage VON, and the turn-off voltage. Generate and output (VOFF). The driving and source voltages VDD and VSS are supplied to a common voltage / gamma voltage generator (not shown), and the turn-on voltage VON and the turn-off voltage VOFF are supplied to the gate driver 108.

FIG. 2 shows a detailed circuit of the DC-DC converter 106 shown in FIG. 1.

The DC-DC converter 106 shown in FIG. 2 generates a drive voltage for generating an analog drive voltage AVDD using the pulse generator 122 and the first pulse signal generated from the pulse generator 122. The generation unit 124 and a time delay unit 120 for delaying the time of the analog driving voltage generated from the driving voltage generation unit 124 to synchronize with the output signal.

The pulse generator 122 includes a PWM IC 126, a reactance L connected between a switch terminal of the PWM IC 126 and an input voltage source through the first node N1, an input voltage source VIN, and a base. A first capacitor C1 connected between the voltage sources GND is provided.

The PWM IC 126 is driven by an input voltage VIN supplied from an input voltage source to pulse width modulate the pulse signal oscillated therein to generate a modulated pulse signal.

The reactance L stores the current from the input voltage source during the conduction time of the output switch connected to the switch terminal and switched by the modulated pulse signal, and supplies the current stored at the interruption time of the output switch to the first node N1. do.

The first capacitor C1 stabilizes the input voltage VIN supplied to the reactance L.

The driving voltage generator 124 generates an analog driving voltage AVDD having a plurality of voltages. The driving voltage generator 124 may include the first and second diodes D1 and D2 connected in series in the forward direction between the first node N1 and the second node N2, and the second node N2. A second capacitor C2 connected between the base voltage sources is provided.

The first and second diodes D1 and D2 rectify the current emitted from the pulse generator (not shown) and block the reverse current. The first and second diodes D1 and D2 are formed of Schottky diodes capable of high speed operation.

The second capacitor C2 stores the voltage output through the second diode D2 and outputs the stored voltage value.

The time delay unit 120 compares the analog driving voltage AVDD having a plurality of voltages provided from the driving voltage generation unit 124 with the reference voltage and turns it on to provide the data driving unit when the reference voltage is higher than the reference voltage. If it is below the reference voltage, turn it off. The time delay unit 120 includes the first and second resistors R1 and R2 connected in parallel, the third capacitor C3 and the third capacitor formed between the first and second resistors R1 and R2. A transistor Q connected to C3 is provided.

The first and second resistors R1 and R2 distribute the analog driving voltage AVDD generated from the driving voltage generator 124. Specifically, the first and second resistors R1 and R2 distribute the analog driving voltage AVDD having a plurality of voltages provided from the driving voltage generator 124. At this time, the first resistance value is greater than the second resistance value. That is, the second resistor R2 has an analog driving voltage AVDD of 0.7V at maximum, and the first resistor R1 has an analog driving voltage AVDD of 0.7V or more. Accordingly, the sum of the analog driving voltages AVDD distributed by the first and second resistors R1 and R2 is 8 to 12V, and preferably 8V is used.

The third capacitor C3 charges the analog driving voltage AVDD input to the second resistor R2 to stabilize the analog driving voltage AVDD.

The transistor Q is turned on when the reference voltage is higher than the reference voltage from the second resistor R2 and is provided to the data driver 114. That is, when the analog voltage AVDD input to the second resistor R2 is 0.7, the transistor Q is turned on to provide the analog driving voltage AVDD to the data driver 114.

Referring to the operation of the DC-DC converter 106, the PWM IC 126 is driven by an input voltage VCC supplied to an input voltage source to pulse width modulate a pulse signal oscillated therein. Occurs. The PWM IC 126 switches the output switch connected to the output terminal by the modulated pulse signal to cause the reactance L to charge / discharge the current so that the first pulse signal amplified at the first node N1 is generated. To be. In this case, the first pulse signal is a voltage (VDD + 2VFD) to which the analog driving voltage AVDD is added to the sum 2VFD of the threshold voltages of the plurality of diodes D1 and D2 positioned in the driving voltage generator 124. Swing between the high voltage base and the low voltage base voltage.

When the first pulse signal P1 is supplied to the driving voltage generator 124, the first pulse signal P1 is connected to the first and second diodes D1 and D2 and the second capacitor C2 connected in series. After rectifying through the configured rectifier (not shown), the rectifier is output as an analog driving voltage AVDD through the second node N2. Specifically, when the high voltage VDD + 2VFD of the first pulse signal P1 is supplied to the first node N1, the first and second diodes D1 and D2 are subjected to forward bias, so that the first and the second voltages are applied. The two diodes D1 and D2 are turned on. Accordingly, the second node N2 drops by the sum level 2VFD of the threshold voltages of the first and second diodes D1 and D2 at the high voltage VDD + 2VFD of the first pulse signal P1. The analog drive voltage AVDD, which is a voltage, is supplied. At this time, the second capacitor C2 is charged with the analog driving voltage AVDD supplied to the second node N2. Subsequently, when the low voltage GND of the first pulse signal P1 is supplied to the first node N1, the first and second diodes D1 and D2 are subjected to reverse bias so that the first and second diodes are reversed. D1 and D2 are turned off. At this time, the analog driving voltage AVDD charged in the second capacitor C2 is discharged so that the second node N2 maintains the analog driving voltage AVDD for a predetermined time.

The analog driving voltage AVDD is distributed to the first and second resistors R1 and R2 of the time delay unit 120 and turned on through the transistor Q when a predetermined voltage is input to the second resistor R2. It is provided to the data driver 114. In this case, when the voltage input to the second resistor R is turned on through the transistor Q, the third capacitor C3 is adjusted to prevent the sudden input and to stably input the voltage. The analog voltage AVDD input to the data driver 114 through the transistor Q is transferred to the data driver 114 at the same time as the control signal PT input from the timing controller 114 as shown in FIG. 3. This prevents burnt problems caused by overcurrent.

On the other hand, the DC-DC converter 106 according to the present invention is provided with a time delay unit 120 when the analog drive voltage (AVDD) is less than the reference voltage can be always maintained at 0V by turning off. Accordingly, the data driver 114, which should be aware of a voltage of 8V or more due to the reactance L by switching the output switch connected to the output terminal by a pulse signal, applies 3.3v first to cause an overcurrent. Can be solved.

In addition, by turning on only when the analog driving voltage AVDD is greater than or equal to the reference voltage, an overcurrent may be generated to prevent a burnt.

As described above, the liquid crystal display and the driving method thereof according to the present invention distribute the analog driving voltage through the first and second resistors to supply the analog driving voltage through a transistor for turning on the reference voltage input to the second resistor. . Accordingly, the liquid crystal display device and the driving method thereof according to the present invention delay the time of the analog driving voltage to synchronize with the output voltage, thereby preventing the existing analog driving voltage from being input before the output voltage and causing the overcurrent to flow. Can prevent a problem from occurring.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the description of the specification but should be defined by the claims.

Claims (8)

A liquid crystal display panel for implementing an image, and a liquid crystal display device driver for driving the liquid crystal display panel; The liquid crystal display driving unit A gate driver and a data driver for providing a gate and a data signal to drive the liquid crystal display panel; A timing controller providing an output signal; DC-DC converter for generating an analog drive voltage; And And a time delay unit for delaying an analog driving voltage to synchronize the output signal with the DC-DC converter. The method of claim 1, The time delay unit First and second resistors connected in parallel to each other to distribute a reference voltage of the analog driving voltage; A capacitor for stabilizing an input voltage supplied to the second resistor; And a transistor turned on in response to an input voltage input to the second resistor. The method of claim 2, Wherein the first resistance value is greater than the second resistance value. The method of claim 3, wherein The reference voltage is a liquid crystal display device, characterized in that 8 ~ 13V. The method of claim 4, wherein And an input voltage input to the second resistor is 0.7V. Generating an output signal through the timing controller; Generating a plurality of analog driving voltages having different voltages through a DC-DC converter; And delaying the analog driving voltage to be input to the data driver at the same time as the output signal. The method of claim 6, Delaying the analog drive voltage is Dividing a reference voltage using the first and second resistors; And And turning on in response to the reference voltage if the input voltage input to the second resistor is a reference voltage. The method of claim 7, wherein And the first resistance value is greater than the second resistance value.

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