KR20140087594A - Power circuit of display device and method of driving the same - Google Patents

Power circuit of display device and method of driving the same Download PDF

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Publication number
KR20140087594A
KR20140087594A KR1020120158085A KR20120158085A KR20140087594A KR 20140087594 A KR20140087594 A KR 20140087594A KR 1020120158085 A KR1020120158085 A KR 1020120158085A KR 20120158085 A KR20120158085 A KR 20120158085A KR 20140087594 A KR20140087594 A KR 20140087594A
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South Korea
Prior art keywords
signal
masking
gate
level
timing controller
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KR1020120158085A
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Korean (ko)
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KR102050442B1 (en
Inventor
김재혁
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엘지디스플레이 주식회사
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0871—Several active elements per pixel in active matrix panels with level shifting
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Abstract

The present invention relates to a power supply circuit of a display device, capable of preventing an abnormal display by masking an output of a timing controller in a section where a power supply is unstable so as to block an output of a level shifter, and to a method for driving the same. The power supply circuit of the display device comprises: a voltage generation unit for generating and outputting a plurality of driving voltages by using an input voltage; a control logic for generating and outputting a gate control signal which controls a drive timing of a gate driver by using a timing signal inputted from a timing controller; a level shifting unit for shifting a level of the timing signal from the timing controller and the gate control signal from the control logic and outputting the level-shifted signals to the gate driver; and a masking logic unit for blocking an output of the level shifting unit in a section where the driving voltage is stable by using an input masking signal and the timing signal inputted from the timing controller.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a power supply circuit of a display device,

The present invention relates to a display device, and more particularly, to a power supply circuit of a display device and a driving method thereof that can prevent an abnormal display by masking the output of a timing controller and shutting off the output of a level shifter, particularly when power is unstable.

2. Description of the Related Art Recently, flat panel display devices that are widely used as display devices include a liquid crystal display (LCD) using a liquid crystal, a plasma display panel (PDP) using an inert gas discharge, an organic light emitting diode OLED display device using a diode (OLED). PDPs are applied to large-sized TVs, OLED display devices are mainly applied to small-sized products, and LCDs are applied to various fields such as mobile phones, notebooks, monitors, and TVs.

The flat panel display includes a display panel for displaying an image through a pixel matrix, a panel drive circuit for driving the display panel, and a timing controller for controlling the panel drive circuit.

For example, an LCD includes a liquid crystal panel in which a plurality of pixels are arranged in a matrix form, a gate driver for driving gate lines of the liquid crystal panel, a data driver for driving the data lines of the liquid crystal panel, And a power supply circuit for generating and supplying various driving voltages required for the gate driver, the data driver, the timing controller, and the liquid crystal panel.

Recently, a power supply circuit generates a gate control signal by using a basic timing signal from a timing controller, generates a gate control signal, and level-shifts it to a necessary gate driving voltage, in addition to a DC-DC converter that generates and supplies various driving voltages. And a level shifter unit for supplying the signal to the driver.

The conventional power supply circuit generates and outputs the digital driving voltage VCC and the gate high voltage VGH using the input voltage VIN as shown in the power-on sequence shown in FIG. In addition, the conventional power supply circuit generates a gate start pulse (GST) and a gate clock (GCLK) by using a start pulse (VST) and a basic clock from a timing controller, and level-shifts and outputs the generated signal.

However, before the driving voltages VCC and VGH are stabilized in the conventional power supply circuit, a glitch, which is an unstable signal, is introduced from the timing controller. At this time, the level shifter operates the glitch from the timing controller Signal, and an abnormal level shifter output is generated. As a result, an abnormal image is displayed on the display panel.

On the other hand, the abnormal driving of the power supply circuit described above may occur not only in the liquid crystal display but also in the OLED display.

It is an object of the present invention to provide a display device capable of preventing an abnormal display by blocking the output of a level shifter by masking the output of a timing controller in an unstable section of the power supply, And a driving method thereof.

According to an aspect of the present invention, there is provided a power supply circuit for a display device, comprising: a voltage generator for generating and outputting a plurality of driving voltages using an input voltage; A control logic for generating and outputting a gate control signal for controlling the driving timing of the gate driver using a timing signal input from the timing controller; A level shifter for level-shifting a timing signal from the timing controller and a gate control signal from the control logic and outputting the level-shifted signal to the gate driver; And a masking logic unit for blocking the output of the level shifting unit in a period in which the driving voltage is stable using the input masking signal and the timing signal input from the timing controller.

Wherein the control logic generates and outputs a plurality of gate shift clocks using an on-clock and an off-clock from the timing controller; Wherein the level shifter comprises: a first level shifter for level-shifting a plurality of gate shift clocks from the control logic and outputting the level shifted clock to the gate driver; a second level shifter for level shifting a gate start pulse from the timing controller and outputting the gate start pulse to the gate driver A level shifter; Wherein the masking logic unit performs a NOR logic operation on the input masking signal and an on clock and an off clock from the timing controller to output a first enable signal for disabling the first level shifter in a masking interval of the input masking signal. 1 masking logic; And a second masking logic for performing NOR logic operation on the input masking signal and the gate start pulse from the timing controller to output a second enable signal for disabling the second level shifter in a masking interval of the input masking signal.

Wherein the level shifting unit further comprises a third level shifter for separating the even-odd pulse from the timing controller into even pulses and odd pulses and level-shifting the odd pulses and outputting them to the gate driver; Wherein the masking logic unit performs a NOR logic operation on the input masking signal and an even-odd pulse from the timing controller to output a third enable signal for disabling the third level shifter in a masking period of the input masking signal, And further includes masking logic.

The power supply circuit of the display device of the present invention further includes a gate pulse modulation section for modulating a polling interval of the gate shift clock output from the first level shifter in response to the off clock and outputting the modulated gate shift clock to the gate driver Respectively.

The input masking signal is supplied from the voltage generator, the timing controller, or an external system, and a masking interval of the input masking signal is set in advance based on a voltage stabilization period of a gate high voltage generated in the voltage generator.

A driving method of a power supply circuit of a display device according to an embodiment of the present invention includes generating and outputting a plurality of driving voltages using an input voltage; A control signal generation step of generating and outputting a gate control signal for controlling a timing of driving the gate driver by using a timing signal input from the timing controller; A level shifting step of level-shifting a timing signal from the timing controller and a gate control signal from the control logic and outputting the level-shifted signal to the gate driver; And masking the output of the level shifting unit in a period in which the driving voltage is stable using the input masking signal and the timing signal input from the timing controller.

Generating the control signal includes generating and outputting a plurality of gate shift clocks using an on-clock and an off-clock from the timing controller; The level shifting step includes level shifting and outputting the plurality of gate shift clocks and the gate start pulse from the timing controller; Wherein the masking step performs a level shifting operation on the plurality of gate shift clocks in a masking interval of the input masking signal in response to a result of performing a NOR logic operation on the input masking signal and the ON clock and the OFF clock from the timing controller, And a step of disabling the level shifting operation for the gate start pulse in the masking interval of the input masking signal in response to a result of performing a NOR logic operation on the input masking signal and the gate start pulse from the timing controller, .

The level shifting step further comprises a step of dividing the even and odd pulses from the timing controller into odd pulses and odd pulses and level shifting and outputting; Wherein the masking logic step includes a step of performing a level shifting operation for the even and odd pulses in a masking interval of the input masking signal in response to a result of performing a NOR logic operation on the input masking signal and the even- Further comprising the step of slaving.

The method of driving a power supply circuit of the present invention further includes modulating the polling interval of the level shifted gate shift clock in response to the off clock and outputting the modulated gate shift clock to the gate driver.

The power supply circuit and the driving method thereof according to the present invention disables the level shifter unit in response to a masking signal from the outside until the power on sequence is stabilized so that the output of the level shifter is cut off even if glitch is introduced from the timing controller It is possible to prevent an abnormal image from being displayed on the display panel.

1 is a waveform diagram showing a power-on sequence of a conventional power supply circuit.
2 is a block diagram schematically showing a liquid crystal display device having a power supply circuit according to an embodiment of the present invention.
3 is a waveform diagram showing a power-on sequence of the power supply circuit shown in Fig.
4 is a circuit diagram showing the configuration of the power supply circuit shown in Fig.
5 is an input / output waveform diagram of the power supply circuit shown in Fig.
Fig. 6 is a circuit diagram showing the internal structure of the masking logic shown in Fig. 4, for example.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to FIGS. 2 to 6 attached hereto.

1 is a circuit block diagram schematically showing a liquid crystal display device including a power supply circuit according to an embodiment of the present invention.

The liquid crystal display device shown in Fig. 1 includes a timing controller 12, a data driver 14, a gate driver 18, and a display panel 20.

The timing controller 12 corrects the data input from the outside by using various data processing methods for improving image quality and power consumption, and outputs the corrected data to the data driver 14. [ For example, in order to improve the response speed of the liquid crystal, the timing controller 12 applies an overshoot value or an undershoot value selected from the look-up table according to the data difference between adjacent frames, (Overdriving) data.

The timing controller 12 generates a data control signal for controlling the driving timing of the data driver 14 using the timing synchronization signals and the timing control information from the outside, and supplies the data control signal to the data driver 14. For example, the data control signal includes a source start pulse and a source sampling clock for controlling latches of data, a source output enable signal for controlling an output period of the data signal, and the like.

The timing controller 12 generates a simple timing signal used for generating a gate control signal for controlling the driving timing of the gate driver 16 using timing synchronization signals and timing control information from the outside, 30). For example, the simple timing signal includes a gate start pulse (GST), an on clock (ONCLK), an off clock (OFFCLK), and the like.

The power supply circuit 30 includes a DC / DC converter unit and a level shifter unit.

The DC / DC converter unit of the power supply circuit 30 uses the input voltage VIN from the outside to drive the timing controller 12, the data driver 14, the gate driver 16 and the liquid crystal panel 20 And generates and outputs various driving voltages. For example, the power supply circuit 30 uses the input voltage VIN to adjust the digital driving voltage VCC supplied to the timing controller 12 and the data driver 14 and the common voltage VCC supplied to the liquid crystal panel 20 A gate high voltage VGH and a gate low voltage VGL supplied to the gate driver 16 and outputs the gate high voltage Vcom and the gate low voltage VGL.

The level shifter unit of the power supply circuit 30 generates a gate control signal for controlling the driving timing of the gate driver 16 using the simple timing signal from the timing controller 12, . For example, the power supply circuit 30 controls the start timing of the gate driver 16 using the gate start pulse GST, the ON clock ONCLK, and the off clock OFFCLK from the timing controller 12, The gate driver 16 generates a pulse VST and n gate shift clocks GCLKn and the like so that the swing width of the start pulse VST and the gate shift clock GCLKn increases. .

In particular, the power supply circuit 30 supplies the masking signal MS input from the external system or the timing controller 12 or generated internally until the various driving voltages generated from the input voltage VIN are stabilized, And disables the output of the level shifter unit when the driving voltage is unstable by disabling the level shifter unit. Then, when the driving voltages are stabilized, the level shifter unit is enabled in response to the masking signal MS to generate a normal gate control signal according to a control signal from the timing controller 12, and supplies the normal gate control signal to the gate driver 16. At this time, the masking period of the masking signal MS is preset by the designer.

For example, the driving voltages generated in the power supply circuit 30 have a power-on sequence in which the input voltage VIN, the digital driving voltage VCC, and the gate high voltage VGH are stabilized in the order shown in FIG. Thus, by experimentally measuring the stabilization period of the gate high voltage (VGH) with the longest rising time and converging to the gate high voltage (VGH) (i.e., the end point of the soft-start period) The stabilization period can be set as the masking period of the masking signal MS.

Accordingly, the power supply circuit 30 disables the level shifter unit by using the masking signal MS until the power-on sequence is stabilized, so that the output of the level shifter unit is cut off even if the glitch is introduced from the timing controller 12 It is possible to prevent an abnormal image from being displayed on the liquid crystal panel 20.

The data driver 14 supplies video data from the timing controller 12 to a plurality of data lines DL of the liquid crystal panel 20 in response to a data control signal from the timing controller 12. [ The data driver 14 converts the digital data input from the timing controller 12 into a positive / negative analog data signal by using a gamma voltage, and outputs a data signal to the data line (DL). The data driver 14 includes at least one data IC and is mounted on a circuit film such as a tape carrier package (TCP), a chip on film (COF), or a flexible printed circuit (FPC) Or may be mounted on the liquid crystal panel 20 by a COG (Chip On Glass) method.

The gate driver 16 sequentially drives the gate line GL of the liquid crystal panel 20 in response to the gate control signal from the power supply circuit 30. [ The gate driver 16 is composed of a shift register and sequentially supplies the scan pulse to the gate line GL while sequentially shifting the start pulse VST using the gate shift clock GCLKn. Therefore, the gate driver 16 supplies the gate-on voltage VGH of the scan pulse to each gate line GL for the corresponding scan period and the gate-off voltage VGL during the remaining period of the other gate line GL, . The gate driver 20 is composed of at least one gate IC and is mounted on a circuit film such as TCP, COF, FPC or the like to be attached to the liquid crystal panel 20 in a TAB manner or mounted on the liquid crystal panel 20 in a COG manner . Alternatively, the gate driver 16 may be formed on the thin film transistor substrate in the same process as the thin film transistor array of the liquid crystal panel 20 by a GIP (Gate In Panel) method and incorporated in the liquid crystal panel 20.

The liquid crystal panel 20 includes a color filter substrate on which a color filter array is formed, a thin film transistor substrate on which a thin film transistor array is formed, a liquid crystal layer between the color filter substrate and the thin film transistor substrate, And a polarizing plate attached thereto. The liquid crystal panel 20 displays an image through a pixel matrix in which a plurality of pixels are arranged. Each pixel implements a desired color by a combination of red / green / blue (R / G / B) sub-pixels that control light transmittance by varying a liquid crystal array according to a data signal, As shown in FIG. Each sub pixel includes a thin film transistor TFT connected to the gate line GL and the data line DL, a liquid crystal capacitor Clc connected in parallel with the thin film transistor TFT, and a storage capacitor Cst. The liquid crystal capacitor Clc charges the difference voltage between the data signal supplied to the pixel electrode through the thin film transistor TFT and the common voltage Vcom supplied to the common electrode, drives the liquid crystal according to the charged voltage, . The storage capacitor Cst stably maintains the voltage charged in the liquid crystal capacitor Clc. The liquid crystal layer is driven by a vertical electric field such as a TN (Twisted Nematic) mode or VA (Vertical Alignment) mode, or by a horizontal electric field such as an IPS (In-Plane Switching) mode or an FFS (Fringe Field Switching) mode.

2, the liquid crystal display further includes a backlight unit for supplying light to the liquid crystal panel 20 and a backlight driver for driving the backlight unit. The backlight unit uses a fluorescent lamp such as Cold Cathode Fluorescent Lamp (CCFL) or External Electrode Fluorescent Lamp (EEFL) driven by a backlight driver or a direct type or edge type backlight including a light emitting diode (LED) as a light source. The direct-type backlight includes a light source disposed on the entire display region and a plurality of optical sheets disposed on the light source so as to face the back surface of the liquid crystal panel 20, and the light emitted from the light source is transmitted through the plurality of optical sheets to the liquid crystal panel 20). The edge type backlight includes a light guide plate facing the back surface of the liquid crystal panel 20, a light source arranged to face at least one edge of the light guide plate, and a plurality of optical sheets arranged on the light guide plate, Converted into a planar light source through a light guide plate, and irradiated onto the liquid crystal panel 20 through a plurality of optical sheets. The backlight driver drives the backlight unit in response to the duty ratio of the pulse width modulation (PWM) signal from the outside, and controls the luminance.

4 is a circuit block diagram showing the internal configuration of the level shifter unit 32 according to the embodiment of the present invention among the power supply circuits 30 shown in Fig. 2, Fig. 5 is a circuit block diagram of the level shifter unit 32 shown in Fig. Fig.

In the level shifter unit 32 of the power supply circuit 30 shown in Fig. 4, the control logic CL controls the ON and OFF clocks OFFCLK and OFFCLK from the timing controller 12 as shown in Fig. To generate four gate shift clocks (GLCK1 to GCLK4) and outputs them to the first level shifter LS1. The four gate shift clocks GCLK1 to GCLK4 are sequentially rising in response to the rising time of the ON clock ONCLK and are sequentially polled in response to the polling time of the OFF clock OFFCLK, Are overlapped with each other.

The first level shifter LS1 level shifts the high voltage of the gate shift clocks GCLK1 to GCLK4 from the control logic CL to the gate high voltage VGH and the low voltage to the gate low voltage VGL .

The gate pulse modulation unit GPM controls the gate shift clocks GCLK1 to GCLK4 output from the first level shifter LS1 to be synchronized with the rising time of the off- (GLK1 to GCLK4) are modulated and output.

The second level shifter LS2 level shifts the high voltage of the gate start pulse GST from the timing controller 12 to the gate high voltage VGH and the low voltage to the gate low voltage VGL.

The third level shifter LS3 separates the even-odd pulse E0 from the timing controller 12 into an even pulse EVEN and an odd pulse ODD as shown in Fig. 5 (b) ) And the odd pulse (ODD) to the gate high voltage (VGH) and the low voltage to the gate low voltage (VGL). The even pulse EVEN and the odd pulse ODD are generated when the gate driver 16 is located at both sides of the liquid crystal panel 20 and the odd gate line and the gate driver for driving the odd gate line when separately driving the even gate line , And alternately enables the gate driver driving the even gate line.

The first masking logic ML1 generates a first enable signal EN1 by a logic operation using an input masking signal MS and an ON clock ONCLK and an off clock OFFCLK and outputs the first enable signal EN1 to the first level shifter LS1 Thereby disabling or enabling the first level shifter LS1.

The second masking logic ML2 generates the second enable signal EN2 by the logic operation using the input masking signal MS and the gate start pulse GST and supplies the second enable signal EN2 to the second level shifter LS2, Disables or enables the shifter LS2.

The third masking logic ML3 generates the third enable signal EN3 by the logic operation using the input masking signal MS and the even-odd pulse EO and supplies the third enable signal EN3 to the third level shifter LS3, The level shifter LS3 is disabled or enabled.

Each of the first to third masking logic ML1 to ML3 is implemented as a NOR gate for ORing all the input signals as shown in FIG. As shown in FIG. 6, the NOR gate NOR outputs an enable signal EN in a high state only in a period in which all inputs are in a low state.

As shown in FIG. 3, during the period during which the gate high voltage VGH is stabilized, the masking signal MS remains high, so that the NOR gate NOR is turned on in response to the low enable signal EN So that the level shifter is disabled. Accordingly, even when glitches are introduced from the timing controller in the unstable period in which the driving voltages are stabilized, the output of the level shifter is cut off, thereby preventing abnormal images from being displayed.

Then, when the gate high voltage VGH is stabilized and the masking signal MS is brought to the low state, the output of the timing controller 12 is also all in the low state, so that the NOR gate NOR becomes the high state enable signal EN, So that the level shifter can be enabled to perform the normal level shifting operation.

As described above, the power supply circuit and the driving method of the display device according to the present invention disable the level shifter unit in response to the masking signal until the power-on sequence is stabilized, so that even if glitches are introduced from the timing controller, It is possible to prevent an abnormal image from being displayed on the display panel.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

12: timing controller 14: data driver
16: gate driver 20: liquid crystal panel
30: power supply circuit 32: level shifter unit
CL: Control logic LS1, LS2, LS3: Level shifter
ML1, ML2, ML3: Masking logic GPM: Gate pulse modulation section

Claims (10)

A voltage generator for generating and outputting a plurality of driving voltages using an input voltage;
A control logic for generating and outputting a gate control signal for controlling the driving timing of the gate driver using a timing signal input from the timing controller;
A level shifter for level-shifting a timing signal from the timing controller and a gate control signal from the control logic and outputting the level-shifted signal to the gate driver;
And a masking logic unit for blocking an output of the level shifting unit in a period in which the driving voltage is stable using the input masking signal and the timing signal input from the timing controller. The method according to claim 1,
Wherein the control logic generates and outputs a plurality of gate shift clocks using an on clock and an off clock from the timing controller,
The level shifting unit
A first level shifter for level-shifting a plurality of gate shift clocks from the control logic and outputting the level shift signals to the gate driver,
And a second level shifter for level-shifting a gate start pulse from the timing controller and outputting the level-shifted pulse to the gate driver,
The masking logic portion
A first masking logic for performing a NOR logic operation on the input masking signal and an on clock and an off clock from the timing controller to output a first enable signal for disabling the first level shifter in a masking interval of the input masking signal, ;
And a second masking logic for NORing the input masking signal and the gate start pulse from the timing controller to output a second enable signal for disabling the second level shifter in a masking interval of the input masking signal And the power supply circuit of the display device. The method of claim 2,
The level shifting unit
Further comprising a third level shifter for separating even-odd pulses from the timing controller into odd pulses and odd pulses and level-shifting the odd pulses and outputting them to the gate driver,
The masking logic portion
And a third masking logic for outputting a third enable signal for disabling the third level shifter in a masking interval of the input masking signal by NOR logic operation of the input masking signal and the even-odd pulse from the timing controller And the power supply circuit of the display device. The method of claim 2,
Further comprising a gate pulse modulator for modulating a polling interval of the gate shift clock output from the first level shifter in response to the off clock and outputting the modulated gate shift clock to the gate driver. Of the power circuit. The method according to any one of claims 1 to 4,
The input masking signal
A timing controller, or an external system,
Wherein a masking period of the input masking signal is set in advance based on a voltage stabilization period of a gate high voltage generated by the voltage generator. Generating and outputting a plurality of driving voltages using an input voltage;
A control signal generation step of generating and outputting a gate control signal for controlling a timing of driving the gate driver by using a timing signal input from the timing controller;
A level shifting step of level-shifting a timing signal from the timing controller and a gate control signal from the control logic and outputting the level-shifted signal to the gate driver;
And masking the output of the level shifting unit in an interval in which the driving voltage is stable using the input masking signal and the timing signal input from the timing controller. The method of claim 6,
Wherein the generating of the control signal includes generating and outputting a plurality of gate shift clocks using an on clock and an off clock from the timing controller,
Wherein the level shifting step includes level shifting and outputting the gate shift clock and the gate start pulse from the timing controller,
Wherein the masking step performs a level shifting operation on the plurality of gate shift clocks in a masking interval of the input masking signal in response to a result of performing a NOR logic operation on the input masking signal and the ON clock and the OFF clock from the timing controller, And a step of disabling the level shifting operation for the gate start pulse in the masking interval of the input masking signal in response to a result of performing a NOR logic operation on the input masking signal and the gate start pulse from the timing controller, And a driving circuit for driving the power supply circuit. The method of claim 7,
Wherein the level shifting step further comprises separating the even-odd pulse from the timing controller into even pulses and odd pulses, level-shifting and outputting the even-
Wherein the masking logic step includes a step of performing a level shifting operation for the even and odd pulses in a masking interval of the input masking signal in response to a result of performing a NOR logic operation on the input masking signal and the even- The method comprising the steps of: driving the power supply circuit of the display device; The method of claim 7,
Shifting the level shifted gate shift clock in response to the off-clock, and outputting the modulated gate shift clock to the gate driver. The method according to any one of claims 6 to 9,
Wherein the input masking signal has a masking period of the input masking signal set in advance based on a voltage stabilization period of a gate high voltage.
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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160074164A (en) * 2014-12-18 2016-06-28 주식회사 실리콘웍스 Level shifter and display device comprising the same
KR20160077254A (en) * 2014-12-22 2016-07-04 엘지디스플레이 주식회사 A crystal dispplay device
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