CN106875903A

CN106875903A - Display device and its driving method

Info

Publication number: CN106875903A
Application number: CN201611044029.5A
Authority: CN
Inventors: 李度坤; 柳连泽
Original assignee: LG Display Co Ltd
Current assignee: LG Display Co Ltd
Priority date: 2015-11-25
Filing date: 2016-11-23
Publication date: 2017-06-20
Anticipated expiration: 2036-11-23
Also published as: KR102556962B1; CN106875903B; KR20170061590A

Abstract

A kind of display device and its driving method are disclosed, the display device includes：Timing controller, it connects and enters floating state by the first logic voltage, and after switching cycle, normal operating state is switched to generate timing controling signal from floating state by reset signal；Level translator, it receives the first logic voltage and the second logic voltage, and by timing controling signal level conversion is to the second logic voltage and exports；And output enables signal control part, it synchronously outputs the output in level " low " or disabling level " height " is enabled and enables signal with reset signal, wherein, during switching cycle, the output that level translator receives disabling level " height " enables signal and stops level conversion.

Description

Display device and its driving method

Technical field

The present invention relates to a kind of display device and its driving method.

Background technology

Major type of display device includes liquid crystal display (LCD) and the OLED comprising Organic Light Emitting Diode (OLED) Display.OLED display and LCD have a big and small various sizes, and for many applications in, such as mobile phone, Notebook computer, monitor, television set etc..

Display device includes：Display panel with multiple pixels in a matrix；Gate drivers, it drives display Gate line on panel；Data driver, it drives the data wire on display panel；Timing control part, its control gate drives Device and data driver, etc..Gate drivers can be embedded in display panel to reduce volume and weight, and this species The display of type is referred to as GIP (panel inner grid) display.

In GIP displays, timing control part includes the timing controller TCON of generation timing controling signal and by making The level translator LS of the multiple gate driving control signals that be fed to gate drivers is exported with timing controling signal.

Specifically be described reference picture 1 by this.Timing controller TCON receives the first logic voltage VCC25, and generation is fixed When control signal and feed them into level translator LS.For example, the first logic voltage VCC25 can be 2.5V.Timing control Timing controling signal is constantly fed to level translator LS by device TCON processed, until the first logic voltage VCC25 for being received Untill dropping to 2.5V or lower.

In addition, timing controller TCON receives the reset signal RST from reset IC (integrated circuit) outputs.Reset signal RST is imported into timing controller TCON in the starting stage of operation, and for by timing controller TCON from floating state It is switched to normal operating state.More specifically, in the starting stage of operation, timing controller TCON is receiving what it was applied Connected during the first logic voltage VCC25 of 2.5V.However, timing controller TCON exports unstable timing control still in from it The floating state of signal processed.After a certain period of time, then, timing controller TCON receives reset signal RST, so as to prevent Output signal abnormal operation in floating state.

The time period can be defined as first logic electricity of the timing controller TCON in the 2.5V in response to applying to it Pressure VCC25 and until receiving the time (hereinafter referred to as " switching cycle Tc ") that reset signal RST is spent after turning on.This is cut It is that timing controller TCON is switched to the time that normal operating state is spent from floating state to change cycle T c.

Level translator LS uses the first logic voltage VCC25 as input electric power and uses the second logic voltage VCC33 as output power, and the timing controling signal Tsig that will be input into from timing controller TCON level conversion to 3.3V, then exports.Level translator LS carries out level conversion when output enable signal OE is received.

Output enables signal OE, and there is the enable level for making level translator LS normal operatings (that is, to export and enable signal OE In low state) and prevent level translator LS from the disabling level that is input into and exports.

However, the problem of conventional level converter LS is, because output enables signal OE, and to be fixed on enable level " low (LOW) " (that is, Enable Pin EN is connected to earthing power supply), therefore once suitably apply input electric power VCC25 and output power VCC33, or even timing controller TCON is in the abnormal signal exported during floating state also by level conversion.

Additionally, in the starting stage of operation, when timing controller TCON is in floating state, output abnormality signal, so Abnormal signal is coupled with adjacent signals afterwards, so as to cause burr.In this case, because level translator LS always can be used for Output, therefore abnormal signals of the level translator LS even to being caused by burr is also carried out level conversion.In abnormal signal input In the case of in system or panel drive circuit, this may cause display device failure.

The content of the invention

Therefore, removal is allowed to be given birth to when the starting stage timing controller of operation is in floating state the present invention relates to a kind of Into abnormal signal display device and its driving method.

Illustrative embodiments of the invention provide a kind of display device, and it includes：Timing controller, it passes through first Logic voltage and connect and enter floating state, and after switching cycle, be switched to just from floating state by reset signal Normal mode of operation is generating timing controling signal；Level translator, it receives the first logic voltage and the second logic voltage, and By timing controling signal level conversion is to the second logic voltage and exports；And output enables signal control part, itself and reset are believed The output enable signal in level " low " (LOW) or disabling level " height " (HIGH) is enabled number is synchronously outputted, wherein, cutting During changing the cycle, the output that level translator receives disabling level HIGH enables signal and stops level conversion.

Another exemplary implementation method of the invention provides a kind of display device, and it includes：Timing controller, its in response to Reset signal and operate and generate the timing controling signal of the first logical voltage level；Level translator, it is by timing controlled Signal is transformed into the second logical voltage level higher than the first logical voltage level and exports, and enables signal in response to output And carry out level conversion；And output enable signal control part, its from apply conducting (ON) level the second logic voltage to During the switching cycle of the reset signal for applying conduction level, output is enabled into signal control in disabling level HIGH, Ran Hou Output is enabled signal control and is enabling level LOW by switching cycle after terminating.

Another exemplary implementation method of the invention provides a kind of driving method of display device, and the method includes：Response The timing controling signal of the first logical voltage level is generated in reset signal；Timing controling signal is transformed into higher than the first logic Second logical voltage level of voltage level is simultaneously exported, and is enabled signal in response to output and carried out level conversion；From applying Plus the second logic voltage of conduction level to apply conduction level reset signal switching cycle during, will output enable signal Then output is enabled signal control and is enabling level LOW by control in disabling level HIGH after switching cycle terminates.

Brief description of the drawings

For providing a further understanding of the present invention and being merged in this specification and constitute the part of this specification Accompanying drawing show embodiments of the present invention, and be used to illustrate principle of the invention together with the description.In the accompanying drawings：

Fig. 1 is to show to turn from level when timing controller is in floating state in the display device according to prior art The oscillogram of parallel operation output abnormality signal；

Fig. 2 is the block diagram for showing display device according to an illustrative embodiment of the invention；

Fig. 3 is to be shown input into the signal of timing controller of the invention and level translator and from level translator The oscillogram of gained output signal；

Fig. 4 is to show that synchronously outputting the output in level LOW or disabling level HIGH is enabled with reset signal enables The output of signal enables the figure of signal control part；And

Fig. 5 is the flow chart of the driving method for showing display device according to an illustrative embodiment of the invention.

Specific embodiment

Hereinafter, illustrative embodiments of the invention are described in detail with reference to the accompanying drawings.Through whole explanation In book, identical reference represents essentially identical element.In the following description, if it is considered to public affairs related to the present invention Know that function or the detailed description of configuration can unnecessarily obscure subject of the present invention, then will omit known work(related to the present invention The detailed description that can or configure.

Although it should be noted that the liquid crystal display device on the example as display device is given into following description, Technological thought of the invention is not limited to liquid crystal display, but goes for other kinds of display device.

The specific example of display device can include liquid crystal display device (LCD), plasma display panel device (PDP), field emission display device (FED), organic light-emitting display device (OLED) etc..

Organic light-emitting display device includes multiple pixels.Each pixel includes organic by formed between the anode and the cathode The Organic Light Emitting Diode of emission layer composition and the independently pixel-driving circuit of driving Organic Light Emitting Diode.Pixel driver electricity Road includes switching thin-film transistor (hereinafter referred to as TFT), drives TFT and capacitor.Switch TFT utilizes number in response to scanning impulse Capacitor is charged according to voltage, and drives TFT to pass through to be controlled to provide to having according to charged in the capacitor data voltage The magnitude of current of machine light emitting diode come adjust by Organic Light Emitting Diode launch light quantity.

Display device of the invention can be implemented as such as TN (twisted-nematic) pattern, VA (vertical orientated) pattern, IPS The all known liquid crystal mode of (in-plane switching) pattern, FFS (fringing field switching) pattern etc..In addition, display dress of the invention Put and can be implemented as any kind of display device, such as transmissive type liquid crystal display, semi permeable type liquid crystal display or reflection Formula liquid crystal display.

Fig. 2 is the block diagram for showing display device according to an illustrative embodiment of the invention.Fig. 3 is to show input to originally The oscillogram of the timing controller of invention and the signal of level translator and the gained output signal from level translator.Fig. 4 It is to show that the output for synchronously outputting the output enable signal in level LOW or disabling level HIGH is enabled with reset signal makes The figure of energy signal control part.

To Fig. 4, display device of the invention 10 includes display panel 11, data drive circuit 12, grid to reference picture 2 Drive circuit 13, timing controller 14, level translator 16 and output enable signal control part (OECP) 17.

Display panel 11 includes data wire and gate line and pixel in a matrix intersected with each other.

Display panel 11 includes upper substrate and infrabasal plate facing with each other, has liquid crystal cell between upper substrate and infrabasal plate (liquid crystal cell)Clc.The pel array including pixel in a matrix is formed with display panel 11, And input picture is displayed on pel array.Pel array includes the tft array being formed on infrabasal plate and is formed in base Color filter array on plate.In tft array, TFT (thin film transistor (TFT)) is formed in the infall of data wire and gate line.TFT The data voltage from data wire is provided the pixel electrode 1 to liquid crystal cell Clc in response to the grid impulse from gate line.Liquid Each liquid crystal cell in brilliant box Clc is by the data voltage according to storage in pixel electrode 1 and applying to public electrode 2 Difference between common electric voltage Vcom controls light transmittance to represent desired gray level.Exist for maintaining 1 frame period memory storage The storage Cst of the data voltage in pixel electrode 1 is connected to liquid crystal cell Clc.Color filter array includes colour filter and black Matrix.Polarizer is respectively attached to the top glass substrate and lower glass substrate of display panel 11, and is formed for setting liquid crystal Pre-tilt angle alignment films.

Data drive circuit 12 may be implemented as source drive IC.Data drive circuit 12 is received from timing controller 14 Digital of digital video data RGB.Data drive circuit 12 is in response to the data drive control signal DDC from timing controller 14 by number Word video data RGB is converted to gamma compensated voltage to generate data voltage, and with grid impulse synchronously by data voltage There is provided to the data wire DL of display panel 11.Data drive circuit 12 can be by COG (glass top chip) techniques or TAB (volumes The automatic engagement of band) technique is connected to the data wire DL of display panel 11.

Gate driving circuit 13 can be formed directly into the infrabasal plate of display panel 11 by GIP (panel inner grid) technology On.Gate driving circuit 13 can be formed in the non-display area outside the pixel region of the display image of display panel 11.Grid drives Dynamic circuit 13 may be implemented as raster data model IC, and be connected to display panel 11 by TAB (winding is engaged automatically) technique Gate lines G L.Gate driving circuit 13 generates grid in response to the gate driving control signal GDC from timing controller 14 Pole pulse, and the grid impulse is provided to gate lines G L by line sequence (line-sequential) method.According to grid arteries and veins 1 horizontal line that punching selection will be charged with data voltage.

Reference picture 2, timing controller 14 receives the digital of digital video data RGB from host computer system 15, and receives such as Vertical synchronizing signal Vsync, horizontal-drive signal Hsync, data enable the timing signal of signal DE and Dot Clock DCLK.Regularly Controller 14 transmits digital of digital video data RGB to the source drive IC of data drive circuit 12.Timing controller 14 is by making The data drive control of the operation timing for controlling source drive IC is generated with timing signal Vsync, Hsync, DE and DCLK The gate driving control signal GDC of signal DDC and the operation timing for control gate drive circuit 13.

Data drive control signal DDC includes that source electrode starting impulse SSP, source electrode sampling clock SSC, source electrode output enable letter Number SOE, polarity control signal POL etc..Source electrode starting impulse SSP and the timing of source electrode sampling clock SSC control datas sampling.Pole Property control signal POL control make the timing of the polarity inversion of data voltage from the output of data drive circuit 12.Source electrode output makes The output timing of energy signal SOE control datas drive circuit 12 and the shared timing of electric charge.

Gate driving control signal GDC is including grid starting impulse GSP, gate shift clock GSC etc..Grid starting impulse GSP controls the timing of first grid pulse.Gate shift clock GSC is that the clock for shifting grid starting impulse GSP is believed Number.

Additionally, timing controller 14 receive the first logic voltage VCC 25, generate timing controling signal Tsig and by they There is provided to level translator 16.Timing controling signal Tsig includes the grid modulation letter of the modulation timing for control gate pulse Number (for example, FLK of Fig. 4), the electric power for controlling to apply to the generation timing of various types of electric power of panel drive circuit Enable signal (DPM of Fig. 4) and for notifying that the timing controller 14 of host computer system 15 gets out receive the ready signal of data (DPX of Fig. 4) etc..

Reference picture 2 and Fig. 3, in the starting stage of operation, timing controller 14 is when the first logic voltage VCC25 is received Connect.However, timing controller 14 is still in the floating state from the unstable timing controling signal of its output.In switching cycle After Tc, timing controller 14 and then reception carry out the reset signal RST of Self-resetting IC (integrated circuit) and are switched to normal behaviour Make state.That is, timing controller 14 is maintained at floating state in the starting stage of operation, until reset signal RST leads Untill logical.Once reset signal RST is turned on, timing controller 14 is with regard to normal operating.

The actual timing of the generation timing controling signal of timing controller 14 Tsig is to apply the reset signal RST of ON level When rather than apply ON level the first logic voltage VCC25 when.Even if applying the first logic voltage VCC25's of ON level In the case of, timing controller 14 is also maintained at floating state, untill the reset signal RST of applying ON level.

Reset IC can be embedded in host computer system 15 or on control panel 18.

Level translator 16 uses the first logic voltage VCC25 as input electric power and higher than the first logic voltage VCC25 The second logic voltage VCC33 as output power, the timing controling signal Tsig that will be input into from timing controller 14 is raised Then (conversion) output it to the second logic voltage VCC33 higher than the first logic voltage VCC25.Level translator 16 can There is provided to gate driving circuit 13 with by the gate driving control signal GDC in the timing controling signal Tsig after rising, and Timing controling signal Tsig after other are raised is provided to host computer system 15.As level translator 16 and timing controller 14 The first logic voltage VCC25 of input electric power can be 2.5V but be not limited to 2.5V.As the output electricity of level translator 16 Second logic voltage VCC33 of power can be 3.3V but be not limited to 3.3V.

The operation of level translator 16 is enabled signal OE to control by the output being input into the Enable Pin EN of level translator 16 System.There is the enable level for making the normal operating of level translator 16 (that is, to export and enable signal OE in low to export enable signal OE State) and prevent level translator 16 from the disabling level that is input into and exports.

Reference picture 2, the output for enabling the applying of signal control part 17 from output enables signal OE and is consolidated as prior art It is scheduled on enable level LOW, i.e. Enable Pin EN is connected to earthing power supply.

As shown in figure 3, enabling the output that signal control part 17 applies from output enables signal OE from applying ON level Disabling level is controlled in during the switching cycle Tc of the second logic voltage VCC33 to the reset signal RST for applying ON level HIGH, is then controlled in enable level LOW after switching cycle Tc terminates.Output enables signal control part 17 and may send out Output is enabled into signal OE controls in disabling level HIGH during the switching cycle Tc of raw abnormal signal (burr etc.), so as to prevent The operation of level translator 16 and prevent the output of abnormal signal.Therefore, switching cycle Tc can be for preventing abnormal letter Number output cycle.

In the starting stage of operation, the first logic electricity in the switching cycle Tc of floating state is in timing controller 14 When pressure VCC25 rises to ON level, unstable timing controling signal Tsig is exported from timing controller 14.Then, abnormal letter Number can be coupled with adjacent signals, so as to cause burr.In this case, level translator 16 is output the OE controls of enable signal System is not useable for output in disabling level HIGH.Therefore, prevent level translator 16 from exporting to be exported from timing controller 14 The unstable timing controling signal Tsig as the abnormal signal caused by burr etc..In order to ensure the security of operation, apply Plus the timing (beginning of switching cycle Tc is regularly) of the second logic voltage VCC33 of ON level can be than applying the first of ON level Timing (timing of burr) the regular hour morning amount Tx of logic voltage VCC25.

Under the control that output enables signal control part 17, level translator 16 makes in response to the output of disabling level HIGH Can signal OE, the level conversion of stopping timing controling signal Tsig and output during switching cycle Tc.Then, level translator 16 output in response to enabling level LOW enables signal OE, and timing controling signal Tsig is started after switching cycle Tc terminates Level conversion and output.

Reference picture 4, output enables signal control part 17 and can be based on patrolling for reset signal RST controlled outputs enable signal OE Collect level.Therefore, output enables signal control part 17 includes switch element SS and resistor R, as shown in Figure 4.

Switch element SS makes including being connected to the coordination electrode Ea of the input of reset signal RST, being connected to output output Can signal OE first node N1 first electrode Eb and be connected to the second electrode Ec of ground voltage supplies GND.Switch element SS may be implemented as field-effect transistor FET or be implemented as bipolar junction transistor BJT.

Resistor R is connected between the input of the second logic voltage VCC33 and first node N1.

If reset signal RST is input into OFF level, then output enables signal control part 17 by using switch element SS makes the current interruptions between first node N1 and ground voltage supplies GND, and the second logic voltage VCC33 of output is enabled as output Signal OE.That is, during the switching cycle Tc that reset signal RST is input into OFF level, output enables signal control part The output of 17 output disabling level HIGH enables signal OE.

If reset signal RST is input into ON level, then output enables signal control part 17 by using switch element SS allows the electric current flowing between first node N1 and ground voltage supplies GND, and output ground voltage enables signal OE as output. That is, during the switching cycle Tc that reset signal RST is input into ON level, output enables the output of signal control part 17 to be made The output of energy level LOW enables signal OE.

Reference picture 2, timing controller 14, level translator 16 and output enable signal control part 17 and may be mounted at control On plate 18.

Fig. 5 shows the driving method of display device according to an illustrative embodiment of the invention.

Reference picture 5, the driving method of display device according to an illustrative embodiment of the invention includes：In response to resetting Signal RST generates the timing controling signal Tsig of the first logical voltage level VCC25；Timing controling signal Tsig is transformed into height In the first logical voltage level VCC25 the second logical voltage level VCC33 and export, and enable signal OE in response to output Carry out level conversion；And in the second logic voltage VCC33 from applying ON level to the reset signal RST's for applying ON level During switching cycle Tc, output is enabled into signal OE controls in disabling level HIGH (S1, S2 and S3), then in switching cycle Tc Output is enabled into signal OE controls after end and enables level LOW (S1, S2 and S5).

When level conversion is carried out in response to output enable signal OE, the output in response to disabling level HIGH enables signal OE, stops level conversion and the output (S4) of timing controling signal Tsig during switching cycle Tc.

When level conversion is carried out in response to output enable signal OE, the output in response to enabling level LOW enables signal OE, starts level conversion and the output (S6) of timing controling signal Tsig after switching cycle Tc terminates.

As described above, the invention allows to will be defeated during the switching cycle Tc that abnormal signal (burr etc.) may occur The output entered in level translator enables signal control in disabling level, so as to stop level conversion during switching cycle Tc The operation of device, and prevent the output of abnormal signal.Thus, the present invention can be by removing the starting stage in operation when timing The abnormal signal that generates prevents the failure of display device when controller is in floating state.

Technological thought of the invention can apply to the starting stage in operation within a predetermined period of time still in floating shape Other IC and timing controller of normal operating after state.

In whole description, it will be appreciated by those skilled in the art that in the case where know-why of the invention is not departed from, Can make various changes and modifications.Therefore, technical scope of the invention is not limited to those detailed descriptions herein, but should It is defined by the appended claims.

Embodiments of the present invention can be described as follows.

Illustrative embodiments of the invention provide a kind of display device, and it includes：Timing controller, it passes through first Logic voltage and connect and enter floating state, and after switching cycle, be switched to just from floating state by reset signal Normal mode of operation is generating timing controling signal；Level translator, it receives the first logic voltage and the second logic voltage, and By timing controling signal level conversion is to the second logic voltage and exports；And output enables signal control part, itself and reset are believed Number synchronously output the output in level LOW or disabling level HIGH is enabled and enable signal, wherein, during switching cycle, The output that level translator receives disabling level HIGH enables signal and stops level conversion.

During switching cycle, timing controller output is coupled with adjacent signals so as to cause the abnormal signal of burr.

After switching cycle terminates, level translator receives the output enable signal for enabling level LOW, and will timing Control signal level conversion is to the second logic voltage and exports.

Gate driving circuit, and other timing controlleds are provided to through some in the timing controling signal of level conversion Signal is provided to host computer system.

Output enables signal control part includes that controlled output enables the switch element and resistor of the logic level of signal.

Switch element includes：The first electrode of reset signal is received, output output enables the second electrode of signal, Yi Jilian It is connected to the 3rd electrode of ground voltage supplies.

Second electrode is connected to the input and resistor of the second logic voltage.

Another exemplary implementation method of the invention provides a kind of display device, and the display device includes：Timing controller, It operates in response to reset signal and generates the timing controling signal of the first logical voltage level；Level translator, it will Timing controling signal is transformed into the second logical voltage level higher than the first logical voltage level and exports, and in response to output Enable signal and carry out level conversion；And output enables signal control part, it is in the second logic voltage from applying ON level To the reset signal for applying ON level switching cycle during, output is enabled into signal control in disabling level HIGH, Ran Hou Output is enabled signal control and is enabling level LOW by switching cycle after terminating.

Output in response to disabling level HIGH enables signal, and level translator stops timing controlled during switching cycle The level conversion of signal and output.

Output in response to enabling level LOW enables signal, and level translator starts timing after switching cycle terminates The level conversion of control signal and output.

Timing of the timing than applying the first logic voltage of ON level for applying the second logic voltage of ON level is early.

Output enables signal control part to be included：Switch element, including the coordination electrode of the input of reset signal is connected to, It is connected to the first electrode that output output enables the first node of signal, and the second electrode for being connected to ground voltage supplies；With And it is connected to the resistor between the input of the second logic voltage and first node.

Switch element is implemented as field-effect transistor or bipolar junction transistor.

Another exemplary implementation method of the invention provides a kind of driving method of display device, and the method includes：Response The timing controling signal of the first logical voltage level is generated in reset signal；Timing controling signal is transformed into higher than the first logic Second logical voltage level of voltage level is simultaneously exported, and is enabled signal in response to output and carried out level conversion；From applying Plus the second logic voltage of ON level to apply ON level reset signal switching cycle during, will output enable signal control In disabling level HIGH, output is then enabled into signal control after switching cycle terminates and is enabling level LOW.

According to the above method, wherein, when level conversion is carried out in response to output enable signal, in response to disabling level The output of HIGH enables signal, and level conversion and the output of timing controling signal are stopped during switching cycle.

When level conversion is carried out in response to output enable signal, the output in response to enabling level LOW enables signal, Switching cycle starts level conversion and the output of timing controling signal after terminating.

Claims

1. a kind of display device, including：

Timing controller, it connects and enters floating state by the first logic voltage, and after switching cycle, by multiple Position signal is switched to normal operating state to generate timing controling signal from the floating state；

Level translator, it receives first logic voltage and the second logic voltage, and the timing controling signal is electric Flat turn is changed to second logic voltage and is exported；And

Output enables signal control part, and it is synchronously outputted in enable level " low " or disabling level with the reset signal The output of " height " enables signal,

Wherein, during the switching cycle, the level translator receives the output in disabling level " height " and enables signal And stop level conversion.

2. display device according to claim 1, wherein, during the switching cycle, the timing controller output Coupled with adjacent signals so as to cause the abnormal signal of burr.

3. display device according to claim 1, wherein, after the switching cycle terminates, the level translator Receive the output in level " low " is enabled and enable signal, and the timing controling signal level conversion is patrolled to described second Collect voltage and export.

4. display device according to claim 3, wherein, it is provided through some in the timing controling signal of level conversion To gate driving circuit, and other timing controling signals are provided to host computer system.

5. display device according to claim 1, wherein, the output enables signal control part includes the control output Enable the switch element and resistor of the logic level of signal.

6. display device according to claim 5, wherein, the switch element includes：

Receive the first electrode of the reset signal；

The output output enables the second electrode of signal；And

It is connected to the 3rd electrode of ground voltage supplies.

7. display device according to claim 6, wherein, the second electrode is connected to second logic voltage Input and the resistor.

8. a kind of display device, including：

Timing controller, it operates in response to reset signal and generates the timing controling signal of the first logical voltage level；

Level translator, timing controling signal is transformed into the second logic electricity higher than first logical voltage level for it Voltage level is simultaneously exported, and is enabled signal in response to output and carried out level conversion；And

Output enables signal control part, and it is in the second logic voltage from applying conduction level to the described multiple of applying conduction level During the switching cycle of position signal, the output is enabled into signal control in disabling level " height ", then in the switching cycle The output is enabled into signal control after end and enables level " low ".

9. display device according to claim 8, wherein, it is described in response to the output enable signal of disabling level " height " Level translator stops level conversion and the output of the timing controling signal during the switching cycle.

10. display device according to claim 8, wherein, the output in response to enabling level " low " enables signal, described Level translator starts level conversion and the output of the timing controling signal after the switching cycle terminates.

11. display devices according to claim 8, wherein, the timing ratio for applying the second logic voltage of conduction level is applied Plus the timing morning of the first logic voltage of conduction level.

12. display devices according to claim 8, wherein, the output enables signal control part to be included：

Switch element, including the coordination electrode of the input of the reset signal is connected to, it is connected to the output output and enables The first electrode of the first node of signal, and it is connected to the second electrode of ground voltage supplies；And

It is connected to the resistor between the input of the second logic voltage and the first node.

13. display devices according to claim 12, wherein, the switch element is implemented as field-effect transistor or double Pole junction transistor.

A kind of 14. driving methods of display device, methods described includes：

The timing controling signal of the first logical voltage level is generated in response to reset signal；

The timing controling signal is transformed into the second logical voltage level higher than first logical voltage level and is exported, And enable signal in response to output and carry out level conversion；

During the switching cycle from the second logic voltage of applying conduction level to the reset signal for applying conduction level, The output is enabled into signal control in disabling level " height ", then the output is enabled after the switching cycle terminates Signal control is enabling level " low ".

15. methods according to claim 14, wherein, when level conversion is carried out in response to output enable signal, response Signal is enabled in the output of disabling level " height ", the level of the timing controling signal is stopped during the switching cycle Conversion and output.

16. methods according to claim 14, wherein, when level conversion is carried out in response to output enable signal, response Signal is enabled in the output for enabling level " low ", the level of the timing controling signal is started after the switching cycle terminates Conversion and output.

17. methods according to claim 14, wherein, the timing for applying the second logic voltage of conduction level is led than applying The timing morning of the first flat logic voltage of energization.