KR102577126B1 - Display device and its driving method - Google Patents

Abstract

An example of the present invention relates to a display device and a driving method thereof that can prevent the fixed wavy phenomenon in which the backlight operation section output in the duty high section becomes slightly dark due to parasitic capacitance. The timing controller of the present invention compensates for charging time or digital video data in a region where the PWM signal controlling pulse width modulation has a high logic level. In the display device and its driving method according to an example of the present invention, when the active layer is exposed to the back light in a thin film transistor substrate formed using four masks, the parasitic capacitance increases compared to the turned-off section. As the data load increases and the charging voltage of the pixel becomes relatively low, it is possible to prevent planar luminance unevenness from occurring.

Description

Display device and driving method thereof {DISPLAY DEVICE AND ITS DRIVING METHOD}

One example of the present invention relates to a display device and a method of driving the same.

In the information society, many related technologies are being developed in the field of display devices for displaying visual information in images or images. A display device includes a display panel that has a display area provided with pixels that display images, a non-display area that is placed outside the display area and does not display images, a gate driver that supplies gate signals to the pixels, and a display panel that supplies gate signals to the pixels. It includes a data driver that supplies a data voltage, and a timing controller that supplies signals that control the gate driver and the data driver.

Among display devices, in the case of a liquid crystal display (LCD), the pixels themselves do not emit light, so a backlight that acts as a light source is required. The backlight used in the display panel of a liquid crystal display device is generally implemented as a light emitting diode (LED).

The backlight is driven by a pulse width modulation (PWM) cycle. PWM determines the brightness of the backlight within 1 frame using the duty ratio. Duty ratio refers to the rate at which the backlight is turned on based on the time within one frame.

At this time, when backlight dimming is applied, parasitic capacitance increases in the section where the backlight is turned on. Accordingly, data load increases compared to the section where the backlight is turned off. Additionally, the voltage charged to the pixels is relatively low, resulting in planar luminance unevenness. Accordingly, a fixed wavy phenomenon occurs in which the backlight operation section output in the duty high section becomes slightly dark.

An example of the present invention is to provide a display device and a driving method thereof that can prevent the fixed wavy phenomenon in which the backlight operation section output in the duty high section is slightly dark due to parasitic capacitance.

A display device according to an example of the present invention includes a display panel that displays an image whose duty ratio is differently controlled for each of a plurality of regions using a pulse width modulation method, a plurality of source drive ICs that supply data voltages to the display panel, and a plurality of source drive ICs that supply data voltages to the display panel. It includes a timing controller that controls the source drive ICs.

A method of driving a display device according to an example of the present invention includes a timing controller controlling a plurality of source drive ICs, the plurality of source drive ICs supplying a data voltage to a display panel, and a display panel displaying an image. It includes the step of controlling the duty ratio differently for each of the plurality of areas using a pulse width modulation method.

The timing controller of the present invention compensates for charging time or digital video data in a region where the PWM signal controlling pulse width modulation has a high logic level.

In summary, in the display device and its driving method according to an example of the present invention, when the active layer is exposed to the back light in a thin film transistor substrate formed using four masks, the parasitic capacitance increases and the turn-off occurs. The data load increases compared to the selected section, and the charging voltage of the pixel is relatively low, preventing surface-shaped luminance unevenness from occurring. Specifically, the display device and its driving method according to an example of the present invention identify an area with a high logic level in a PWM signal with a duty ratio set, and then change the charging time that affects pixel charging or modulate digital video data. The phenomenon of luminance unevenness can be resolved.

1 is a plan view of a display device according to an example of the present invention.
Figure 2 is a block diagram of a display device according to an example of the present invention.
3 is a circuit diagram of a pixel according to an example of the present invention.
Figure 4 is a block diagram showing existing PWM driving.
Figure 5 is a waveform diagram showing the gate pulse and data voltage during conventional PWM driving.
Figure 6 is a block diagram showing PWM driving of a display device according to an example of the present invention.
Figure 7 is a waveform diagram showing a data enable signal, a first source control signal, and a first gate control signal of the display device according to the first embodiment of the present invention.
Figure 8 is a flowchart of a method of driving a display device according to an example of the present invention.

The advantages and features of the present invention and methods for achieving them will become clear by referring to examples described in detail below along with the accompanying drawings. However, the present invention is not limited to the examples disclosed below and will be implemented in various different forms, and only the examples of the present invention are intended to ensure that the disclosure of the present invention is complete and are within the scope of common knowledge in the technical field to which the present invention pertains. It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. shown in the drawings for explaining an example of the present invention are illustrative, and the present invention is not limited to the details shown. Like reference numerals refer to like elements throughout the specification. Additionally, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

When 'includes', 'has', 'consists of', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship of two parts is described as 'on top', 'on the top', 'on the bottom', 'next to', etc., 'immediately' Alternatively, there may be one or more other parts placed between the two parts, unless 'directly' is used.

In the case of a description of a temporal relationship, for example, if a temporal relationship is described as 'after', 'successfully after', 'after', 'before', etc., 'immediately' or 'directly' Unless used, non-consecutive cases may also be included.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may also be the second component within the technical spirit of the present invention.

The “first horizontal axis direction”, “second horizontal axis direction”, and “vertical axis direction” should not be interpreted as only geometrical relationships in which the relationship between each other is vertical, and the scope in which the configuration of the present invention can function functionally It can mean having a broader direction than within.

The term “at least one” should be understood to include all possible combinations from one or more related items. For example, “at least one of the first, second, and third items” means each of the first, second, or third items, as well as two of the first, second, and third items. It can mean a combination of all items that can be presented from more than one.

Each feature of the various examples of the present invention can be combined or combined with each other, partially or entirely, and various technical interconnections and operations are possible, and each example can be implemented independently of each other or together in a related relationship. .

Hereinafter, preferred examples of the present invention will be described in detail with reference to the attached drawings.

1 is a plan view of a display device according to an example of the present invention. In FIG. 1 , for convenience of explanation, the first horizontal axis direction (X) is parallel to the gate line, the second horizontal axis direction (Y) is parallel to the data line, and the vertical axis direction (Z) is the direction of the display device. The explanation focuses on the thickness (or height) direction. A display device according to an example of the present invention includes a display panel 110, a gate driver 120, a source drive integrated circuit (hereinafter referred to as “IC”) 131, a flexible circuit film 140, and a circuit board. (150), and a timing controller (Timing Controller, T-con) (160).

A display device according to an example of the present invention relates to a display device that drives a backlight using a PWM method. Among display devices that use backlights, a representative example is a liquid crystal display. Therefore, the following description will focus on the case where the display device according to an example of the present invention is a liquid crystal display device.

When the display device according to an example of the present invention is a liquid crystal display device, the display panel 110 includes a thin film transistor substrate 111, a counter substrate 112, and a space between the thin film transistor substrate 111 and the counter substrate 112. It includes an interposed liquid crystal layer.

The thin film transistor substrate 111 includes a plurality of gate lines and a plurality of data lines arranged to cross each other.

The plurality of gate lines extend long along the first horizontal axis direction (X) of the thin film transistor substrate 111, and are spaced at regular intervals along the second horizontal axis direction (Y) that horizontally intersects the first horizontal axis direction (X). is separated from

The plurality of data lines intersect the plurality of gate lines, extend long along the second horizontal axis direction (Y), and are spaced apart at regular intervals along the first horizontal axis direction (X).

The thin film transistor substrate 111 includes a display area DA and a non-display area. In the display area DA, gate lines and data lines are arranged to cross each other. The intersection areas of the gate lines and data lines each define a pixel area.

The non-display area is placed outside the display area DA. More specifically, the non-display area refers to the remaining area of the thin film transistor substrate 111 excluding the display area DA. For example, the non-display area may be the upper, lower, left, and right edges of the thin film transistor substrate 111. The opposing substrate 112 includes a black matrix and a color filter. Color filters can be placed in openings that are not obscured by the black matrix. When the display panel 110 has a color filter on TFT (COT) structure, a black matrix and color filters may be disposed on the thin film transistor substrate 111.

A polarizing plate may be attached to each of the thin film transistor substrate 111 and the opposing substrate 112, and an alignment film may be provided to set a pre-tilt angle of the liquid crystal. A spacer may be provided between the thin film transistor substrate 111 and the opposing substrate 112 to maintain a cell gap of the liquid crystal layer.

The gate driver 120 generates a gate signal according to the gate control signal input from the panel driver and supplies it to the gate line. The gate driver 120 according to an example of the present invention is provided as a GIP (Gate in Panel) circuit in a non-display area of the thin film transistor substrate 111.

The gate driver 120 provided as a GIP circuit is built in the non-display area of the thin film transistor substrate 111 together with the transistor of the pixel. For example, the gate driver 120 provided as a GIP circuit may be provided in a non-display area on one side and/or the other side of the display area DA, but is not limited to this, and is not limited to this, and may be provided in any non-display area that can supply a gate signal to the gate line. It is provided in a non-display area.

Each of the plurality of source drive ICs 131 is mounted on the flexible circuit film 140, receives digital video data and data control signals supplied from the timing controller 160, and converts digital video data into analog data according to the data control signal. Converts it to voltage and supplies it to the data lines. When the source drive IC 131 is manufactured as a driving chip, each of the source drive ICs 131 may be mounted on the flexible circuit film 140 using a chip on film (COF) or chip on plastic (COP) method.

Each of the plurality of flexible circuit films 140 is attached to a pad provided on the thin film transistor substrate 111. At this time, each of the plurality of flexible circuit films 140 is attached to the pads using an anisotropic conducting film (antisotropic conducting film, ACF). Each of these plurality of flexible circuit films 140 supplies the data voltage supplied from the source drive IC 131 to the data line through the pad portion. Additionally, at least one of the plurality of flexible circuit films 140 supplies a gate driver control signal supplied from the timing controller 160 to the gate driver 120 .

The circuit board 150 is connected to a plurality of flexible circuit films 140. The circuit board 150 supports multiple circuits implemented with driving chips. For example, the timing controller 160 may be mounted on the circuit board 150. The circuit board 150 may be a printed circuit board or a flexible printed circuit board.

The timing controller 160 is mounted on the circuit board 150 and receives digital video data and timing synchronization signals from an external system board. Here, the timing synchronization signals include a vertical sync signal that defines one frame period, a horizontal sync signal that defines one horizontal period, and a data enable signal that indicates whether or not data is valid. ), and a dot clock, which is a clock signal with a predetermined period.

The timing controller 160 generates a gate driver control signal for controlling the operation timing of the gate driver 120 and a data driver control signal for controlling the source drive ICs 131 based on the timing synchronization signals. The timing controller 160 supplies a gate driver control signal to the gate driver 120 and a data driver control signal to the plurality of source drive ICs 131.

Figure 2 is a block diagram of a display device 100 according to an example of the present invention. The display device 100 according to an example of the present invention includes a display panel 110, a data driver 130, a gate driver 120, a timing controller 160, a system board 170, a backlight unit driver 190, and a backlight unit 200. When the display device 100 according to an example of the present invention is a liquid crystal display device, the pixels P themselves cannot emit light. Therefore, it becomes a display device using the backlight unit 200.

The display panel 110 displays an image using pixels (P). Data lines D and gate lines G are disposed on the lower substrate of the display panel 110. The data lines (D) are arranged to intersect with the gate lines (G).

3 is a circuit diagram of a pixel P according to an example of the present invention. Pixels (P) are respectively disposed at intersections of data lines (D) and gate lines (G). Each of the pixels (P) is connected to a data line (D) and a gate line (G). Each of the pixels P includes a transistor T, a pixel electrode 11, a common electrode 12, a liquid crystal layer 13, and a storage capacitor Cst. The transistor (T) is turned on by the gate signal of the gate line (G). The turned-on transistor (T) supplies the data voltage of the data line (D) to the pixel electrode 11. The common electrode 12 is connected to a common line and receives a common voltage from the common line.

Each of the pixels P drives the liquid crystal of the liquid crystal layer 13 by an electric field generated by the potential difference between the data voltage supplied to the pixel electrode 11 and the common voltage supplied to the common electrode 12. The arrangement of the liquid crystal changes depending on the presence or absence of an electric field and the intensity of the electric field, so that the amount of light transmitted from the backlight unit 200 can be adjusted. As a result, the pixels P can display an image with a set gray level. The storage capacitor Cst is disposed between the pixel electrode 11 and the common electrode 12. The storage capacitor Cst maintains the potential difference between the pixel electrode 11 and the common electrode 12 constant.

The common electrode 12 is disposed on the upper substrate in a vertical electric field driving method such as TN (Twisted Nematic) mode or VA (Vertical Alignment) mode. The common electrode 12 is disposed on the lower substrate together with the pixel electrode 11 in a horizontal electric field driving method such as IPS (In Plane Switching) mode or FFS (Fringe Field Switching) mode. The liquid crystal mode of the display panel 110 may be implemented in any liquid crystal mode in addition to the above-described TN mode, VA mode, IPS mode, and FFS mode.

The gate driver 120 receives a gate driver control signal (GCS) from the timing controller 160. The gate driver 120 generates gate signals according to the gate driver control signal (GCS). The gate driver 120 sequentially supplies gate signals to the gate lines G of the display panel 110. Accordingly, the data voltage of the data line (D) may be supplied to the pixel (P) to which the gate signals are supplied.

The data driver 130 receives a data driver control signal (DCS) and digital video data (DATA) from the timing controller 160. The data driver 130 generates analog data voltages by converting digital video data (DATA) into a positive or negative gamma compensation voltage according to the data driver control signal (DCS). The data driver outputs analog data voltages. Analog data voltages output from the data driver 130 are supplied to the data lines D of the display panel 110.

The timing controller 160 receives digital video data (DATA) and timing signals (TS) from the system board 170. Timing signals (TS) include a horizontal synchronization signal (Hsync), a vertical synchronization signal (Vsync), an input data enable signal (Input DE), and a dot clock. Dclk), etc.

The timing controller 160 generates a gate driver control signal (GCS) and a data driver control signal (DCS) based on the timing signals TS. The timing controller 160 supplies the gate driver control signal (GCS) to the gate driver 120. The timing controller 160 supplies a data driver control signal (DCS) and digital video data (DATA) to the data driver 130.

The system board 170 supplies digital video data (DATA) to the timing controller 160 through an interface such as an Embedded Point to Point Packet Protocol Interface (EPI). The system board 170 supplies timing signals TS to the timing controller 160. The system board 170 supplies a backlight unit control signal (BCD) to the backlight driver 190. The backlight unit control signal (BCD) sets the magnitude of the driving voltage (DV) supplied by the backlight driver 190 to the backlight unit 200 for each region on the display panel 110. The backlight unit control signal (BCD) may be transmitted in SPI (Serial Peripheral Interface) data format.

The backlight driver 190 receives a backlight unit control signal (BCD) from the system board 170. The backlight driver 190 provides a driving voltage (DV) of a size corresponding to the brightness of the image to be displayed for each area on the display panel 110 to the backlight unit 200, based on the information included in the backlight unit control signal (BCD). ) is supplied.

The backlight unit 200 receives a driving voltage (DV) from the backlight driver 190. The backlight unit 200 emits backlight perpendicular to the surface of the display panel 110 with brightness corresponding to the driving voltage (DV) for each area on the display panel 110. The backlight unit 200 can be implemented with any light source that can emit light. Generally, the recent backlight unit 200 is implemented as a light emitting diode array (LED Array), but can also be implemented as a fluorescent lamp or UV LED.

Figure 4 is a block diagram showing existing PWM driving.

The timing controller 160 supplies a gate driver control signal (GCS) to the gate driver 120 and digital video data (DATA) and a data driver control signal (DCS) to a plurality of source drive ICs 131. .

The timing controller 160 applies a PWM signal (PWM) to the backlight driver 190. The PWM signal (PWM) is a signal that controls the backlight driver 190 to perform PWM driving of the backlight unit 200. PWM driving is a driving method that modulates the pulse width and adjusts the duty ratio, which is the rate at which the backlight turns on within one frame.

The gate driver 120 generates gate signals GS according to the gate driver control signal GCS. The gate driver 120 supplies gate signals GS with the same timing to all gate lines on the display panel 110. The gate signals GS keep the gate electrode of the transistor in the pixel open for the same period. Accordingly, all pixels provided on the display panel 110 are turned on for the same period.

The plurality of source drive ICs 131 supply a data voltage of a size set by digital video data (DATA) to the display panel 110 during one frame period determined by the data driver control signal (DCS). Digital video data (DATA) is not related to the change in duty ratio of the backlight 200 according to PWM driving. Accordingly, each of the plurality of source drive ICs 131 generates a data voltage using digital video data (DATA) set only by image information to be implemented for each display area of the display panel 110.

The backlight driver 190 receives a PWM signal (PWM) from the timing controller 160. The backlight driver 190 supplies the backlight 200 with a driving voltage (DV) that is differently set according to the duty ratio for each region on the display panel 110, based on the PWM signal (PWM).

The backlight 200 is supplied with a driving voltage (DV) set differently according to the duty ratio for each of the plurality of areas on the display panel 110. The backlight 200 has an on state in which the PWM signal PWM has a high logic level, or an off state in which the PWM signal PWM has a low logic level. The backlight 200 supplies lighting to the display panel 110 based on the driving voltage (DV).

At this time, since the on and off states alternate within one frame in all areas depending on the duty ratio, the user cannot distinguish between on and off areas. However, when the duty ratio is large, the on state within one frame is long, so a brighter image is displayed on average, and when the duty ratio is small, the off state within one frame is long, so a darker image is displayed on average.

The instantaneous luminance when the back light 200 is off, not the average luminance, is referred to as the first luminance L1, and the instantaneous luminance when the back light 200 is on is referred to as the first luminance L1. is called the second luminance (L2). At this time, contrary to the average luminance, the first luminance (L1) is higher than the second luminance (L2). That is, in the case of instantaneous luminance, a phenomenon occurs in which the luminance on the display panel 110 becomes lower when it is in an on state than when it is in an off state.

As described above in the technology behind the invention, when backlight dimming is applied on the display panel 110, parasitic capacitance increases in the section where the backlight is turned on. Accordingly, data load increases compared to the section where the backlight is turned off. Additionally, the voltage charged to the pixels is relatively low, resulting in planar luminance unevenness. Accordingly, a fixed wavy phenomenon occurs in which the backlight operation section output in the duty high section becomes slightly dark.

Figure 5 is a waveform diagram showing the gate pulse and data voltage during conventional PWM driving.

The gate pulse (Vg) maintains the gate low voltage (VGL) state and has the size of the gate high voltage (VGH) at the beginning or end of one frame. A gate pulse (Vg) having a gate high voltage (VGH) can change the data voltage (Vd).

The level of the data voltage (Vd) changes alternately between the negative data voltage (Vn) and the positive data voltage (Vn) when the gate pulse (Vg) has the gate high voltage (VGH). The negative data voltage (Vn) is pulled up to the positive data voltage (Vp), and the positive data voltage (Vp) is pulled down to the negative data voltage (Vn). Accordingly, it is possible to prevent the liquid crystal on the display panel 110 from being tilted in a specific direction.

However, immediately after the negative data voltage (Vn) is pulled up to the positive data voltage (Vp) by the gate pulse (Vg) of the gate high voltage, the positive data voltage (Vp) decreases by △Vp. . The reason why the data voltage (Vd) decreases by △Vp is because of parasitic capacitance that interferes with charging. △Vp can be expressed by the following relational expression.

Here, Clc is the internal capacitor of the liquid crystal layer, Cst is the storage capacitor, and Cgs is the capacitance that occurs between the gate electrode and source electrode of the transistor (T) inside the pixel (P). Since pixels are crowded in a small space, the influence of Cgs cannot be ignored. Recently, as the distance from other layers becomes shorter, the size of Cgs and the capacitance with other layers, Cdp and Cdv, are added. Cdp is the capacitance between the active layer and the pixel layer, and Cdv is the capacitance between the active layer and the common electrode. In particular, in the recent manufacturing process of the thin film transistor substrate 111, four masks are used, which is a smaller number of masks than the existing case where five masks were used. Accordingly, the active layer and the source/drain layer are formed simultaneously. As a result, the active layer protrudes outside the source/drain layers. When the active layer is amorphous silicon, the characteristics of the active layer change depending on the light emitted from the backlight unit 200. Ultimately, the parasitic capacitance formed by the active layer changes, and the magnitude of the voltage charged to the liquid crystal also changes.

Figure 6 is a block diagram showing PWM driving of a display device according to an example of the present invention.

The timing controller 160 according to an example of the present invention includes a PWM driver 161, a digital video data compensation unit 162, and a gate driver control signal change unit 163.

The PWM driver 161 applies a PWM signal (PWM) to the backlight driver 190. The PWM signal (PWM) is a signal that controls the backlight driver 190 to perform PWM driving of the backlight unit 200. PWM driving is a driving method that modulates the pulse width and adjusts the duty ratio, which is the rate at which the backlight turns on within one frame.

The digital video data compensation unit 162 generates compensated digital video data (CDATA). Compensated digital video data (CDATA) is data that can compensate for a decrease in the data voltage (Vd) generated by the original digital video data (DATA) by △Vp due to parasitic capacitance. The digital video data compensation unit 162 supplies compensated digital video data (CDATA) and a data driver control signal (DCS) to the plurality of source drive ICs 131.

The gate driver control signal change unit 163 generates a changed gate driver control signal CGCS. The modified gate driver control signal (CGCS) is a control signal that allows the generation of a modified gate signal (CGS) that ensures that the amount of charged charge remains the same even if the data voltage (Vd) decreases by △Vp due to parasitic capacitance. The changed gate signal (CGS) is a signal that changes the gate signal (GS) to increase the charging time. The gate driver control signal changer 163 supplies the changed gate driver control signal CGCS to the gate driver 120.

The gate driver 120 generates gate signals GS and changed gate signals CGS according to the changed gate driver control signal GCS. The gate driver 120 supplies gate signals GS to an area of the gate lines on the display panel 110 where the PWM signal is in an off state. The gate driver 120 supplies changed gate signals CGS to an area of the gate lines on the display panel 110 where the PWM signal is in an on state. That is, the changed gate signal CGS is supplied to an area where the data voltage Vd decreases by △Vp due to parasitic capacitance. Accordingly, among all pixels provided on the display panel 110, the area where the data voltage Vd decreases by ΔVp due to parasitic capacitance is turned on for a longer period of time.

The plurality of source drive ICs 131 supply a data voltage of a size set by the compensated digital video data (CDATA) to the display panel 110 during one frame period determined by the data driver control signal (DCS). Compensated digital video data (CDATA) is related to the change in duty ratio of the backlight 200 according to PWM driving. Accordingly, each of the plurality of source drive ICs 131 displays image information to be implemented for each display area of the display panel 110 and a compensated digital video set based on the logic level of the PWM signal (PWM) in the corresponding display area. Data voltage is generated using data (CDATA).

More specifically, compensated digital video data (CDATA) is a data voltage (Vd+) increased by the amount (△Vp) by which the positive data voltage (Vp) decreases due to parasitic capacitance in an area where the PWM signal (PWM) has a high logic level. Digital video data (DATA) is corrected to supply △Vp). Compensated digital video data (CDATA) supplies an increased data voltage (Vd+△Vp) to an area where the data voltage (Vd) decreases by △Vp due to parasitic capacitance.

In FIG. 6, the digital video data compensation unit 162 inside the timing controller 160 supplies compensated digital video data (CDATA) to the source drive IC 131 and changes the control signal of the gate driver inside the timing controller 160. A case in which the changed gate driver control signal (CGCS) is supplied from the unit 163 to the gate driver 120 is shown. However, the timing controller 160 is not limited to this, and if it is not necessary to apply both methods, the timing controller 160 may apply only one method. That is, the timing controller may supply only compensated digital video data (CDATA) or generate only the changed gate driver control signal (CGCS).

The backlight driver 190 receives a PWM signal (PWM) from the timing controller 160. The backlight driver 190 supplies the backlight 200 with a driving voltage (DV) that is differently set according to the duty ratio for each region on the display panel 110, based on the PWM signal (PWM).

The backlight 200 is supplied with a driving voltage (DV) set differently according to the duty ratio for each of the plurality of areas on the display panel 110. The backlight 200 has an on state in which the PWM signal PWM has a high logic level, or an off state in which the PWM signal PWM has a low logic level. The backlight 200 supplies lighting to the display panel 110 based on the driving voltage (DV).

At this time, since the on and off states alternate within one frame in all areas depending on the duty ratio, the user cannot distinguish between on and off areas. However, when the duty ratio is large, the on state within one frame is long, so a brighter image is displayed on average, and when the duty ratio is small, the off state within one frame is long, so a darker image is displayed on average.

Accordingly, the luminance can be the same in all areas. This means not only the average luminance during the day, but also the same luminance over all hours. Both the instantaneous luminance when the backlight 200 is off and the instantaneous luminance when the backlight 200 is on become the first luminance L1. That is, even in the case of instantaneous luminance, there is no difference in luminance on the display panel 110 when it is in an on state and when it is in an off state.

Accordingly, even if backlight dimming is applied on the display panel 110, luminance is uniform in all areas and no planar luminance unevenness occurs. Accordingly, the fixed wavy phenomenon in which the backlight operation section output in the duty high section becomes slightly dark can be prevented.

FIG. 7 is a waveform diagram showing the data enable signal (DE), the first source control signal (SCS1), and the first gate control signal (GCS1) of the display device according to the first embodiment of the present invention.

The display device according to the first embodiment of the present invention is a display device that increases the charging time in the area where the data voltage (Vd) decreases by △Vp due to parasitic capacitance by using the changed gate driver control signal (CGCS).

The data enable signal (DE) is a signal that repeats one cycle every frame and signals the start of one frame. 1 frame starts the moment the data enable signal (DE) changes from the high logic level to the low logic level.

The first source control signal (SCS1) is a signal that indicates when the data voltage begins to be charged. The moment the first source control signal (SCS1) changes from a low logic level to a high logic level, the data voltage begins to be charged. When the data voltage begins to be charged, the transistors (T) inside the pixel (P) are turned on.

The first gate control signal (GCS1) is a signal that indicates when charging of the data voltage ends. The moment the first gate control signal (GCS1) changes from the high logic level to the low logic level, charging of the data voltage ends. When the data voltage stops being charged, the transistors T inside the pixel P are turned off.

When the PWM signal (PWM) has a low logic level, the charging time is the first charging time (Cha), and when the PWM signal (PWM) has a high logic level, the charging time is the second charging time (Chb). am. At this time, the second charging time (Chb) is longer than the first charging time (Cha).

When the PWM signal (PWM) has a high logic level, the influence of parasitic capacitance is greater than when the PWM signal (PWM) has a low logic level. When the PWM signal (PWM) has a high logic level, the size of the data voltage is lower than when the PWM signal (PWM) has a low logic level. However, when the PWM signal (PWM) has a high logic level and the charging time within one frame is lengthened, a decrease in data voltage due to parasitic capacitance can be compensated for.

Specifically, the second charging time (Chb) is lengthened by delaying the pulse of the first gate control signal (GCS1) when having the second charging time (Chb) compared to when having the first charging time (Cha). You can. If the timing of the first gate control signal (GCS1) input to the area where the PWM signal (PWM) has a high logic level is delayed, the area where the PWM signal (PWM) has the high logic level is delayed by 1 frame. It can be charged for a longer period of time. Accordingly, even though the data voltage decreases due to the influence of parasitic capacitance while the PWM signal (PWM) has a high logic level, the same amount of data voltage can be charged to all pixels.

The display device according to the second embodiment of the present invention is a display device that uses compensated digital video data (CDATA) to increase the data voltage in an area where the data voltage (Vd) decreases by △Vp due to parasitic capacitance.

In this case, the digital video data (DATA) itself is modulated to supply a data voltage as large as △Vp, which is reduced due to parasitic capacitance, in areas where the PWM signal (PWM) has a high logic level.

For example, assume that a data voltage of 5V is supplied to the entire area on the display panel 110. However, it is assumed that there is a voltage decrease of 0.5V in the area where the PWM signal (PWM) has a high logic level due to parasitic capacitance. In this case, digital video data (DATA) is originally set to supply a data voltage of 5V to all areas. Then, the compensated digital video data (CDATA) is set to supply a data voltage of 5V in the area where the PWM signal (PWM) has a low logic level, and 5.5V in the area where the PWM signal (PWM) has a high logic level. Even when supplied in this way, there is a voltage decrease of 0.5V in the area where the PWM signal (PWM) has a high logic level due to parasitic capacitance. Therefore, in conclusion, a data voltage of 5V is supplied to the entire area.

The display device according to the second embodiment of the present invention modulates digital video data inside the timing controller 160 to increase and supply voltage equal to the voltage decrease due to parasitic capacitance. Accordingly, the display device according to the second embodiment of the present invention can overcome the influence of parasitic capacitance existing on the display panel 110 without adding additional components.

In order to implement a display device according to the first or second embodiment of the present invention, the amount of voltage reduced due to parasitic capacitance must be measured. Typically, the amount of voltage reduced due to parasitic capacitance is determined by the physical properties of the display panel 110. Accordingly, display panels 110 of the same model with the same area, thickness, and material have substantially the same parasitic capacitance. Accordingly, the timing controller 160 applied to the same display panel 110 model may store information in advance about the amount of voltage decreased due to the parasitic capacitance of the model.

In the case of the timing controller 160 applied to various display panel 110 models, the timing controller 160 may have a measurement unit built in that measures the voltage value reduced by the parasitic capacitance when the PWM signal (PWM) is at a high logic level. You can. In this case, the timing controller 160 is designed to measure the voltage of the display panel 110. The timing controller 160 measures the voltage in the same area when the PWM signal (PWM) is at a low logic level and when the PWM signal (PWM) is at a high logic level, and measures the voltage when the PWM signal (PWM) is at a high logic level. The voltage value reduced by parasitic capacitance can be measured. Accordingly, the timing controller 160 applied to various display panel 110 models can also overcome the influence of parasitic capacitance existing on each display panel 110.

A method of driving a display device according to an example of the present invention includes the steps of the timing controller 160 controlling a plurality of source drive ICs 131, and the plurality of source drive ICs 131 transmitting data to the display panel 110. It includes supplying a voltage, and controlling the duty ratio of a display panel displaying an image differently for each of the plurality of regions using a pulse width modulation method. A method of driving a display device according to an example of the present invention compensates for charging time or digital video data (DATA) in an area where the PWM signal (PWM) controlling pulse width modulation has a high logic level.

Figure 8 is a flowchart of a method of driving a display device according to an example of the present invention.

First, the charging time or digital video data (DATA) when the PWM signal (PWM) is at a low logic level is defined. When the PWM signal (PWM) is at a low logic level, voltage reduction due to parasitic capacitance does not occur. Therefore, there is no need to compensate for voltage reduction due to parasitic capacitance. (S1 in Figure 8)

Second, define the amount of △Vp, which is the amount of voltage reduction due to parasitic capacitance in the section where the PWM signal (PWM) is at a high logic level. Defines the charging time or digital video data (DATA) when the PWM signal (PWM) is at a high logic level. Thereafter, by analyzing the difference between the charging time or digital video data (DATA) when the previously defined PWM signal (PWM) is at a low logic level, the amount of △Vp, which is the amount of voltage reduction due to parasitic capacitance, can be defined. (S2 in Figure 8)

Third, the amount of △Vp is converted into charging time or digital video data. According to the first embodiment of the present invention, how long charging must be performed to overcome the voltage decrease can be calculated according to the physical characteristics of the display panel. According to the second embodiment of the present invention, digital video data can be modulated to supply a data voltage increased by the amount of voltage decrease. (Figure S3).

Fourth, the converted charging time or digital video data is compensated. (Figure S4). According to the first embodiment of the present invention, when the pulse timing of the first gate control signal (GCS1) indicating the end of charging is delayed by the converted charging time, the charging time is increased enough to compensate for the voltage decrease. You can do it. According to the second embodiment of the present invention, by applying the modulated digital video data to a section where the PWM signal (PWM) is at a high logic level, a voltage decrease due to parasitic capacitance can be prevented from being recognized on the display panel 110. there is.

In summary, in the display device and its driving method according to an example of the present invention, when the active layer is exposed to the back light in a thin film transistor substrate formed using four masks, the parasitic capacitance increases and the turn-off occurs. The data load increases compared to the selected section, and the charging voltage of the pixel is relatively low, preventing surface-shaped luminance unevenness from occurring. Specifically, the display device and its driving method according to an example of the present invention identify an area with a high logic level in a PWM signal with a duty ratio set, and then change the charging time that affects pixel charging or modulate digital video data. The phenomenon of luminance unevenness can be resolved.

Although embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made without departing from the technical spirit of the present invention. . Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but are for illustrative purposes, and the scope of the technical idea of the present invention is not limited by these embodiments. Accordingly, the embodiments described above should be understood in all respects as illustrative and not restrictive. The scope of protection of the present invention should be interpreted in accordance with the claims, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of rights of the present invention.

100: display device 110: display panel
111: thin film transistor substrate 112: opposing substrate
120: gate driver 130: data driver
131: Source drive IC 140: Flexible circuit film
150: circuit board 160: timing controller
161: PWM driver 162: digital video data compensation unit
163: Gate driver control signal change unit
170: system board 180: PMIC
190: backlight driver 200: backlight unit
DA: Display area P: Pixels
T: Transistor 11: Pixel electrode
12: common electrode 13: liquid crystal layer
Cst: storage capacitor

Claims (10)

A display panel that displays an image whose duty ratio is differently controlled for each region using a pulse width modulation method;
a plurality of source drive ICs that supply data voltage to the display panel; and
It includes a timing controller that controls the plurality of source drive ICs,
The timing controller is,
The PWM signal controlling the pulse width modulation increases the charge amount in the area where the logic level is high,
A display device that delays the timing at which a first gate control signal input to an area where the PWM signal has a high logic level has a high logic level. The method of claim 1, wherein the timing controller:
A display device that increases the charging time of an area where the PWM signal has a high logic level. delete The method of claim 1, wherein the timing controller:
A display device that modulates digital video data in a region where the PWM signal has a high logic level into compensated digital video data to have an increased data voltage. The method of claim 1, wherein the timing controller:
A display device further comprising a measuring unit configured to measure a charging amount to compensate for a changed voltage value when the PWM signal is at a high logic level. A timing controller controlling a plurality of source drive ICs;
supplying data voltage to a display panel by the plurality of source drive ICs; and
It includes controlling the duty ratio of a display panel displaying an image differently for a plurality of areas using a pulse width modulation method,
The timing controller,
The PWM signal controlling the pulse width modulation increases the charge amount in the area where the logic level is high,
A method of driving a display device that delays the timing at which a first gate control signal input to an area where the PWM signal has a high logic level has a high logic level. The method of claim 6, wherein the timing controller:
A method of driving a display device that increases the charging time of a region where the PWM signal has a high logic level. delete The method of claim 6, wherein the timing controller:
A method of driving a display device by modulating digital video data in a region where the PWM signal has a high logic level into compensated digital video data to have an increased data voltage. The method of claim 6, wherein the timing controller controls the plurality of source drive ICs,
A method of driving a display device including measuring a charge amount to compensate for a voltage value that changes when the PWM signal is at a high logic level using a measurement unit inside the timing controller.

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