KR102571356B1 - Display device and its driving method - Google Patents

Abstract

An example of the present invention relates to a display device capable of preventing flicker from occurring even when an interface signal is lost or changed, and a method for driving the same. The DAC of the present invention has a built-in common voltage selection output unit that sets the data voltage to be equal to the common voltage when the source drive IC is supplied with blank digital video data. Accordingly, the present invention can prevent the accumulation of DC voltage components due to the difference between the data voltage and the common voltage. In addition, the present invention can reduce the level of flicker generation by eliminating the effect of the accumulation of DC stress or the tendency of liquid crystals inside the display panel to accumulate due to the same polarity accumulation.

Description

Display device and its driving method {DISPLAY DEVICE AND ITS DRIVING METHOD}

An example of the present invention relates to a display device and a method for driving the same.

BACKGROUND ART In order to more effectively deliver visual information in an information society, technology related to a display device that implements an image is being developed. The display device includes a display panel on which pixels expressing gradations according to the magnitude of supplied voltage and set color are disposed, and a source drive integrated circuit (IC) supplying data voltages to the pixels. It includes a data driver and a timing controller that controls the data driver.

The data driver control signal supplied from the timing controller causes the data driver to invert and supply positive and negative voltages at regular intervals. This is because DC stress is accumulated when either a positive voltage or a negative voltage is continuously applied. In particular, in the case of a liquid crystal display device that expresses gradation according to the arrangement of liquid crystals, when DC voltage stress is accumulated in the liquid crystal, the liquid crystal is tilted in a specific direction, resulting in a problem of not being able to express normal gradations. Therefore, in order to prevent the problem of bending the liquid crystal, the positive polarity voltage and the negative polarity voltage are alternately supplied for each frame.

When a normal interface signal (Tx clock) is input from the timing controller, the source drive IC receives a data driver control signal and digital video data from the timing controller and supplies data voltages to pixels provided on the display panel.

However, interface signals among signals supplied from the timing controller to the source drive IC may be lost or changed due to various internal or external factors. In this case, after supplying active digital video data (Active Data) displaying an image to the last line, blank digital video data (Blank Data) is output. Blank digital video data is output until a normal interface signal is input, and it is determined and outputted as one of G0 to G255, which is one of a plurality of gamma voltage values set in the timing controller.

At this time, the EPI control signal is not input from the timing controller. Accordingly, since the polarity of the data voltage output from the source driver IC is not controlled, a voltage of the same polarity is output in successive frames or, in severe cases, a DC voltage is output. When this phenomenon is repeatedly performed, flicker occurs due to an increase in a DC component inside the display panel. The cause of the flicker is that it is generated while being biased towards either one of the positive polarity and the negative polarity. If the polarity of the data voltage output is not controlled and DC components of the same polarity are output, the polarity is biased to one side continuously in the Nth and (N+1)th frames, resulting in a large voltage difference and accumulation of DC components. As a result, flicker occurs.

An object of the present invention is to provide a display device capable of preventing flicker from occurring even when an interface signal is lost or changed, and a method for driving the same.

A display device according to an exemplary embodiment of the present invention supplies a display panel for displaying an image, a plurality of source drive ICs for supplying data voltages to the display panel, and digital video data and a data driver control signal to the plurality of source drive ICs. It is provided with a timing controller that Each of the plurality of source drive ICs of the present invention includes a digital-to-analog converter that converts digital video data into data voltages.

A method of driving a display device according to an embodiment of the present invention includes supplying digital video data and a data driver control signal to a plurality of source drive ICs by a timing controller, and supplying data voltages to a display panel by the plurality of source drive ICs. step, and a step of displaying an image by the display panel. The step of supplying the data voltage to the display panel by the plurality of source drive ICs of the present invention includes converting digital video data into the data voltage using a DAC inside the source drive IC.

The DAC of the present invention has a built-in common voltage selection output unit that sets the data voltage to be equal to the common voltage when the source drive IC is supplied with blank digital video data.

The present invention adds a configuration for outputting a common voltage level in addition to digital video data of one of G0 to G255 generating DC voltages for blank digital video data output from the timing controller when an interface signal is lost or changed. Accordingly, the present invention can prevent the accumulation of DC voltage components due to the difference between the data voltage and the common voltage. In addition, the present invention can reduce the level of flicker generation by eliminating the effect of the accumulation of DC stress or the tendency of liquid crystals inside the display panel to accumulate due to the same polarity accumulation.

1 is a plan view of a display device according to an exemplary embodiment of the present invention.
2 is a block diagram of a display device according to an exemplary embodiment of the present invention.
3 is a circuit diagram of a pixel according to an exemplary embodiment of the present invention.
4 is a block diagram illustrating normal EPI interface reception of a display device according to an exemplary embodiment of the present invention.
FIG. 5 is a waveform diagram of respective voltages shown in FIG. 4 .
6 is a block diagram illustrating abnormal EPI interface reception of the display device according to the first embodiment of the present invention.
FIG. 7 is a waveform diagram of respective voltages shown in FIG. 6 .
8 is a block diagram illustrating abnormal EPI interface reception of the display device according to the second embodiment of the present invention.
9 is a block diagram according to the third embodiment of the source drive IC of the present invention.
FIG. 10 is a waveform diagram of respective voltages shown in FIG. 8 .
11 is a graph comparing degrees of flicker according to embodiments of the present invention.
12 is a flowchart of a method of driving a display device according to an embodiment of the present invention.

Advantages and features of the present invention, and methods of achieving them, will become clear with reference to the detailed description of the following embodiments taken in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only these embodiments make the disclosure of the present invention complete, and common knowledge in the art to which the present invention belongs. It is provided to fully inform the holder of the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative, so the present invention is not limited to the details shown. Like reference numbers designate like elements throughout the specification. In addition, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted.

When 'includes', 'has', 'consists', etc. mentioned in this specification is used, other parts may be added unless 'only' is used. In the case where a component is expressed in the singular, the case including the plural is included unless otherwise explicitly stated.

In interpreting the components, even if there is no separate explicit description, it is interpreted as including the error range.

In the case of a description of a positional relationship, for example, 'on top of', 'on top of', 'at the bottom of', 'next to', etc. Or, unless 'directly' is used, one or more other parts may be located between the two parts.

In the case of a description of a temporal relationship, for example, 'immediately' or 'directly' when a temporal precedence relationship is described in terms of 'after', 'following', 'next to', 'before', etc. It can also include non-continuous cases unless is used.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may also be the second component within the technical spirit of the present invention.

"X-axis direction", "Y-axis direction", and "Z-axis direction" should not be interpreted only as a geometric relationship in which the relationship between each other is made upright, and may be broader within the range in which the configuration of the present invention can function functionally. It can mean having a direction.

The term “at least one” should be understood to include all possible combinations from one or more related items. For example, "at least one of the first item, the second item, and the third item" means not only the first item, the second item, or the third item, respectively, but also two of the first item, the second item, and the third item. It may mean a combination of all items that can be presented from one or more.

Each feature of the various embodiments of the present invention can be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each embodiment can be implemented independently of each other or can be implemented together in a related relationship. may be

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view of a display device according to an exemplary embodiment of the present invention. For convenience of explanation in FIG. 1 , a first horizontal axis direction (X) is a direction parallel to the gate line, a second horizontal axis direction (Y) is a direction parallel to the data line, and a vertical axis direction (Z) is a direction of the display device. It has been described focusing on the thickness (or height) direction. A display device according to an example of the present invention includes a display panel 110, a gate driver 120, a source drive integrated circuit (hereinafter referred to as "IC") 131, a flexible circuit film 140, and a circuit board. 150, and a timing controller (T-con) 160.

A display device according to one embodiment of the present invention is an invention intended to prevent a problem in which a liquid crystal is tilted in a specific direction as a DC voltage stress is accumulated in the liquid crystal and cannot express a normal gray scale. Therefore, hereinafter, a case in which the display device according to an example of the present invention is a liquid crystal display will be mainly described.

When the display device according to an example of the present invention is a liquid crystal display device, the display panel 110 includes a thin film transistor substrate 111, a counter substrate 112, and between the thin film transistor substrate 111 and the counter substrate 112. It includes an interposed liquid crystal layer.

The thin film transistor substrate 111 includes a plurality of gate lines and a plurality of data lines disposed to cross each other.

The plurality of gate lines extend long along the first horizontal axis direction (X) of the thin film transistor substrate 111 and are spaced at regular intervals along the second horizontal axis direction (Y) horizontally crossing the first horizontal axis direction (X). separated by

The plurality of data lines cross the plurality of gate lines, extend long along the second horizontal axis direction (Y), and are spaced apart at regular intervals along the first horizontal axis direction (X).

The thin film transistor substrate 111 includes a display area DA and a non-display area. In the display area DA, gate lines and data lines are disposed to cross each other. Intersecting areas of the gate lines and data lines each define a pixel area.

The non-display area is disposed outside the display area DA. More specifically, the non-display area refers to the remaining area of the thin film transistor substrate 111 except for the display area DA. For example, the non-display area may be upper, lower, left, and right edge portions of the thin film transistor substrate 111 . The counter substrate 112 includes a black matrix and a color filter. Color filters may be disposed in openings not covered by the black matrix. When the display panel 110 has a color filter on TFT (COT) structure, the black matrix and color filters may be disposed on the thin film transistor substrate 111 .

A polarizing plate may be attached to each of the thin film transistor substrate 111 and the counter substrate 112 and an alignment layer for setting a pre-tilt angle of liquid crystal may be provided. A spacer may be provided between the thin film transistor substrate 111 and the opposite substrate 112 to maintain a cell gap of the liquid crystal layer.

The gate driver 120 generates a gate signal according to a gate control signal input from the panel driver and supplies it to the gate line. The gate driver 120 according to an example of the present invention is provided as a GIP (Gate in Panel) circuit in the non-display area of the thin film transistor substrate 111 .

The gate driver 120 provided as a GIP circuit is embedded in the non-display area of the thin film transistor substrate 111 together with the transistors of the pixels. For example, the gate driver 120 provided as a GIP circuit may be provided on one side and/or the other non-display area of the display area DA, but is not limited thereto, and may supply gate signals to gate lines. It is provided in the non-display area.

Each of the plurality of source drive ICs 131 is mounted on the flexible circuit film 140, receives digital video data and a data control signal supplied from the timing controller 160, and converts digital video data to analog data according to the data control signal. It is converted into voltage and supplied to the data lines. When the source drive IC 131 is manufactured as a driving chip, each source drive IC 131 may be mounted on the flexible circuit film 140 in a chip on film (COF) or chip on plastic (COP) method.

Each of the plurality of flexible circuit films 140 is attached to a pad portion provided on the thin film transistor substrate 111 . At this time, each of the plurality of flexible circuit films 140 is attached on the pads using an anisotropic conducting film (ACF). Each of the plurality of flexible circuit films 140 supplies the data voltage supplied from the source drive IC 131 to the data line through the pad part. In addition, at least one of the plurality of flexible circuit films 140 supplies the gate driver control signal supplied from the timing controller 160 to the gate driver 120 .

The circuit board 150 is connected to a plurality of flexible circuit films 140 . The circuit board 150 supports a plurality of circuits implemented as driving chips. For example, the timing controller 160 may be mounted on the circuit board 150 . The circuit board 150 may be a printed circuit board or a flexible printed circuit board.

The timing controller 160 is mounted on the circuit board 150 and receives digital video data and timing synchronization signals from an external system board. Here, the timing sync signals include a vertical sync signal defining one frame period, a horizontal sync signal defining one horizontal period, and a data enable signal indicating valid data. ), and a dot clock, which is a clock signal having a predetermined period.

The timing controller 160 generates a gate driver control signal for controlling the operation timing of the gate driver 120 and a data driver control signal for controlling the source driver ICs 131 based on the timing synchronization signals. The timing controller 160 supplies a gate driver control signal to the gate driver 120 and a data driver control signal to the plurality of source driver ICs 131 .

2 is a block diagram of a display device 100 according to an example of the present invention. A display device 100 according to an example of the present invention includes a display panel 110, a data driver 130, a gate driver 120, a timing controller 160, a system board 170, a backlight unit driver 190, and a backlight unit 200 . When the display device 100 according to an example of the present invention is a liquid crystal display device, the pixels P themselves cannot emit light. Accordingly, a display device using the backlight unit 200 is obtained.

The display panel 110 displays an image using the pixels P. Data lines D and gate lines G are disposed on the lower substrate of the display panel 110 . Data lines (D) are disposed to cross each other with gate lines (G).

3 is a circuit diagram of a pixel P according to an exemplary embodiment of the present invention. Pixels P are disposed at intersections of data lines D and gate lines G, respectively. Each of the pixels P is connected to a data line D and a gate line G. Each of the pixels P includes a transistor T, a pixel electrode 11, a common electrode 12, a liquid crystal layer 13, and a storage capacitor Cst. The transistor T is turned on by the gate signal of the gate line G. The turned-on transistor T supplies the data voltage of the data line D to the pixel electrode 11 . The common electrode 12 is connected to a common line and receives a common voltage from the common line.

Each of the pixels P drives the liquid crystal of the liquid crystal layer 13 by an electric field generated by a potential difference between the data voltage supplied to the pixel electrode 11 and the common voltage supplied to the common electrode 12 . The arrangement of liquid crystals is changed according to the presence or absence of an electric field and the intensity of the electric field, so that the transmission amount of light incident from the backlight unit 200 can be adjusted. As a result, the pixels P can display images in the set grayscale. The storage capacitor Cst is disposed between the pixel electrode 11 and the common electrode 12 . The storage capacitor Cst maintains a constant potential difference between the pixel electrode 11 and the common electrode 12 .

The common electrode 12 is disposed on the upper substrate in a vertical electric field driving method such as a TN (Twisted Nematic) mode or a VA (Vertical Alignment) mode. The common electrode 12 is disposed on the lower substrate together with the pixel electrode 11 in a horizontal electric field driving method such as an in plane switching (IPS) mode or a fringe field switching (FFS) mode. The liquid crystal mode of the display panel 110 may be realized in any liquid crystal mode as well as the aforementioned TN mode, VA mode, IPS mode, and FFS mode.

The gate driver 120 receives the gate driver control signal GCS from the timing controller 160 . The gate driver 120 generates gate signals according to the gate driver control signal GCS. The gate driver 120 sequentially supplies gate signals to the gate lines G of the display panel 110 . Accordingly, the data voltage of the data line D may be supplied to the pixel P to which the gate signals are supplied.

The data driver 130 receives the data driver control signal DCS and digital video data DATA from the timing controller 160 . The data driver 130 generates analog data voltages by converting the digital video data DATA into positive or negative gamma compensation voltages according to the data driver control signal DCS. The data driver outputs analog data voltages. Analog data voltages output from the data driver 130 are supplied to the data lines D of the display panel 110 .

The timing controller 160 receives digital video data DATA and timing signals TS from the system board 170 . The timing signals TS include a horizontal synchronization signal (Hsync), a vertical synchronization signal (Vsync), an input data enable signal (Input DE), and a dot clock (Dot clock). Dclk) and the like.

The timing controller 160 generates a gate driver control signal GCS and a data driver control signal DCS based on the timing signals TS. The timing controller 160 supplies the gate driver control signal GCS to the gate driver 120 . The timing controller 160 supplies the data driver control signal DCS and digital video data DATA to the data driver 130 .

The system board 170 supplies digital video data DATA to the timing controller 160 through an interface such as an Embedded Point to Point Packet Protocol Interface (hereinafter referred to as "EPI"). The system board 170 supplies timing signals TS to the timing controller 160 . The system board 170 supplies the backlight unit control signal BCD to the backlight driver 190 . The backlight unit control signal BCD sets the level of the driving voltage DV supplied to the backlight unit 200 by the backlight driver 190 for each area on the display panel 110 . The backlight unit control signal BCD may be transmitted in a serial peripheral interface (SPI) data format.

The backlight driver 190 receives the backlight unit control signal BCD from the system board 170 . Based on the information included in the backlight unit control signal (BCD), the backlight driver 190 provides the backlight unit 200 with a driving voltage (DV) corresponding to the brightness of an image to be displayed for each region on the display panel 110. ) is supplied.

The backlight unit 200 receives a driving voltage DV from the backlight driver 190 . The backlight unit 200 emits backlight perpendicular to the surface of the display panel 110 with brightness corresponding to the driving voltage DV for each area on the display panel 110 . The backlight unit 200 may be implemented with any light source capable of emitting light. In general, a recent backlight unit 200 is implemented as a light emitting diode array (LED Array), but can also be implemented as a fluorescent lamp or UV LED.

4 is a block diagram illustrating normal EPI interface (EPI) reception of a display device according to an embodiment of the present invention. In FIG. 4 , a source drive IC 131 , a timing controller 160 , and a power management integrated circuit (hereinafter referred to as “PMIC”) 180 are shown. The source drive IC 131 according to an example of the present invention includes a shift register 210, a latch 220, a digital-analog converter (hereinafter referred to as “DAC”) ( 230), an output buffer 240, and a serial-parallel converter 250.

The timing controller 160 supplies a plurality of digital video data (DATA) and an interface (Embedded Packet to Packet Interface, hereinafter referred to as "EPI interface") (EPI) according to the EPI packet protocol to the serial-to-parallel converter 250. . An EPI interface (EPI) according to an example of the present invention is an interface for transmitting between the timing controller 160 and the serial-to-parallel converter 250. The timing controller 160 supplies the data driver control signal DCS and the POL signal POL for determining the polarity of the data voltage to the latch 220 .

The PMIC 180 generates a common voltage (VCOM). The common voltage VCOM can be defined as a voltage supplied when the liquid crystal is in a reference state in which liquid crystals are arranged horizontally or vertically without bending. The common voltage (VCOM) is a voltage that holds the standard so that liquid crystals can be arranged straight without being bent. The PMIC 180 supplies the generated common voltage VCOM to the serial-parallel converter 250.

The shift register 210 generates a shift signal SHIFT and supplies it to the latch 220 . The shift signal SHIFT is a signal that controls the latch 220 to simultaneously output a plurality of sequentially supplied digital video data data.

The latch 220 sequentially receives a plurality of digital video data DATA for each data line from the serial-parallel converter 250 . The latch 220 receives the shift signal SHIFT from the shift register 210 . The latch 220 simultaneously outputs a plurality of digital video data DATA sequentially supplied using the shift signal SHIFT. The latch 220 controls the output timing of the digital video data DATA according to the start and end of a frame using the data driver control signal DCS. The latch 220 allows the digital video data DATA in each frame to have polarity information of the data voltages Vdata using the POL signal POL.

The DAC 230 receives a plurality of digital video data DATA from the latch 220 . The DAC 230 uses each digital video data DATA to generate data voltages Vdata corresponding to the digital video data DATA of each data line.

The output buffer 240 receives data voltages Vdata from the DAC 230 . The output buffer 240 supplies data voltages Vdata to data lines.

The serial-to-parallel converter 250 receives an EPI interface (EPI) and digital video data (DATA) from the timing controller 160 . The serial-parallel converter 250 receives a common voltage VCOM from the PMIC 180. The serial-parallel converter 250 sequentially supplies digital video data DATA to the latch 220 .

FIG. 5 is a waveform diagram of respective voltages shown in FIG. 4 .

When the display device according to one embodiment of the present invention receives a normal EPI interface (EPI), the polarity of the data voltage Vdata changes for each frame. Each frame starts when the vertical synchronization signal Vsync changes from the gate low voltage VGL to the gate high voltage VGH.

When the polarity of the data voltage Vdata in the Nth frame is positive, the polarity of the data voltage Vdata in the (N+1)th frame is is negative polarity.

The common voltage (Vcom) is set to the midpoint of the positive and negative polarities. Based on the common voltage Vcom, the data voltage Vdata when positive polarity has a voltage level as high as the positive voltage change amount CPos, and the data voltage Vdata when negative polarity has a voltage level equal to the negative voltage change amount CNeg. have a low voltage level. When the magnitudes of the positive voltage change amount CPos and the negative voltage change amount CNeg are the same, the alignment direction of the liquid crystal is changed while being tilted to the same extent for each frame, so that polarity drift does not occur.

6 is a block diagram illustrating abnormal EPI interface (ERR) reception of the display device according to the first embodiment of the present invention.

The timing controller 160 supplies the abnormal EPI interface (ERR) and blank digital video data (BDATA) to the serial-to-parallel converter 250. The abnormal EPI interface (EPI) is an interface transmitted in a state in which information necessary for driving the source drive IC 131 is missing due to an error between the timing controller 160 and the serial-to-parallel converter 250. The blank digital video data (BDATA) is internal to the timing controller 160 to prevent a floating state in which the output of the source drive IC 131 is not defined when information necessary for driving the source drive IC 131 is missing. It is data set in advance. The blank digital video data (BDATA) is data for outputting DC voltages (G0 to G255) corresponding to 256 gamma levels.

The timing controller 160 supplies only the data driver control signal DCS to the latch. The timing controller 160 does not supply the POL signal POL for determining the polarity of the data voltage to the latch 220 .

The PMIC 180 generates a common voltage (VCOM). The PMIC 180 supplies the generated common voltage VCOM to the serial-parallel converter 250.

The shift register 210 generates a shift signal SHIFT. The shift register 210 supplies the shift signal SHIFT to the latch 220 .

The latch 220 sequentially receives a plurality of blank digital video data (BDATA) for each data line from the serial-parallel converter 250 . The latch 220 receives the shift signal SHIFT from the shift register 210 . The latch 220 simultaneously outputs a plurality of blank digital video data BDATA sequentially supplied using the shift signal SHIFT. The latch 220 controls the output timing of the digital video data DATA according to the start and end of a frame using the data driver control signal DCS.

The DAC 230 receives a plurality of blank digital video data (BDATA) from the latch 220 . The DAC 230 uses each blank digital video data BDATA to generate DC voltages VDC corresponding to the blank digital video data BDATA of each data line.

The output buffer 240 receives DC voltages (VDC) from the DAC 230 . The output buffer 240 supplies DC voltages (VDC) to the data lines.

The serial-to-parallel converter 250 receives an abnormal EPI interface (ERR) and blank digital video data (BDATA) from the timing controller 160 . The serial-parallel converter 250 receives a common voltage VCOM from the PMIC 180. The serial-parallel converter 250 sequentially supplies blank digital video data BDATA to the latch 220 .

FIG. 7 is a waveform diagram of respective voltages shown in FIG. 6 .

When the display device according to one embodiment of the present invention receives an abnormal EPI interface (ERR), it outputs a direct current voltage (VDC) as a data voltage. Each frame starts when the vertical synchronization signal Vsync changes from the gate low voltage VGL to the gate high voltage VGH. At this time, the polarity does not change even if a certain frame is passed to the next frame, and a DC voltage (VDC) having a constant magnitude is output. In this case, as illustrated in FIG. 7 , the direct current voltage (VDC) may be higher than the common voltage (Vcom) in some cases, and conversely, the direct current voltage (VDC) may be lower than the common voltage (Vcom) in other cases.

When the DC voltage (VDC) in the Nth frame is higher than the common voltage (Vcom), the DC voltage (VDC) in the (N+1)th frame ((N+1)th frame) is also higher than the common voltage (Vcom). higher than the common voltage (Vcom). In this case, it continuously has a voltage level as high as the positive voltage change amount CPos based on the common voltage Vcom. When a direct current voltage (VDC) is continuously supplied at a voltage level as high as the positive voltage change amount (CPos), liquid crystals are continuously aligned in a tilted state, and thus a polarity bias phenomenon occurs. Accordingly, a flicker phenomenon occurs on the display panel 110 .

8 is a block diagram illustrating abnormal EPI interface reception of the display device according to the second embodiment of the present invention.

The timing controller 160 supplies an abnormal EPI interface (ERR), blank digital video data (BDATA), and a common voltage command signal (Vcom_CMD) to the serial-to-parallel converter 250 . The common voltage command signal Vcom_CMD is a signal that controls the source driver IC 131 to select and output a DC voltage having the same level as the common voltage VCOM.

The timing controller 160 supplies only the data driver control signal DCS to the latch. The timing controller 160 does not supply the POL signal POL for determining the polarity of the data voltage to the latch 220 .

The PMIC 180 generates a common voltage (VCOM). The PMIC 180 supplies the generated common voltage VCOM to the serial-parallel converter 250.

The shift register 210 generates a shift signal SHIFT. The shift register 210 supplies the shift signal SHIFT to the latch 220 .

The latch 220 sequentially receives a plurality of blank digital video data (BDATA) for each data line from the serial-parallel converter 250 . The latch 220 receives the shift signal SHIFT from the shift register 210 . The latch 220 simultaneously outputs a plurality of blank digital video data BDATA sequentially supplied using the shift signal SHIFT. The latch 220 controls the output timing of the digital video data DATA according to the start and end of a frame using the data driver control signal DCS.

The DAC 230 receives a plurality of blank digital video data (BDATA) from the latch 220 . The DAC 230 generates common voltages VCOM to be supplied to each data line.

The output buffer 240 receives common voltages VCOM from the DAC 230 . The output buffer 240 supplies common voltages VCOM to data lines.

The serial-to-parallel converter 250 receives an abnormal EPI interface (ERR) and blank digital video data (BDATA) from the timing controller 160 . The serial-parallel converter 250 receives a common voltage VCOM from the PMIC 180. The serial-parallel converter 250 sequentially supplies blank digital video data BDATA to the latch 220 .

The display device according to the second embodiment of the present invention uses the common voltage (VCOM) as a data voltage when an abnormal EPI interface (ERR) is supplied. Accordingly, the display device according to the second exemplary embodiment of the present invention supplies a DC voltage equal to the magnitude of the common voltage VCOM as the data voltage when the polarity of the data voltage cannot be changed. Therefore, even if the data voltage is a DC voltage, a DC voltage higher or lower than the common voltage VCOM is not continuously supplied, and a DC voltage having the same magnitude as the common voltage VCOM is supplied, so that the liquid crystal is tilted and the flicker phenomenon occurs. problems can be prevented.

9 is a block diagram according to the third embodiment of the source drive IC 131 of the present invention. The source drive IC 131 according to the third embodiment of the present invention includes a loss detection unit 310, a gamma voltage selection output unit 320, a common voltage selection output unit 330, a switching unit 340, and a signal transfer unit. 350, gamma voltage generator 360, common voltage generator 370, first and second gamma voltage switching units 381 and 382, first to third buffers 391 to 393, and an output multiplexer. (400).

The loss detection unit 310 detects whether the EPI interface (EPI) is lost or changed. The loss detection unit 310 may detect loss or change of the EPI interface (EPI) by analyzing a signal or transmission clock (Tx clock) included in the EPI interface (EPI). The loss detection unit 310 transmits the EPI interface (EPI) to the gamma voltage selection output unit 320, the common voltage selection output unit 330, and the switching unit 340 when the EPI interface (EPI) is lost or changed. Or, it provides a warning signal indicating that it has been changed.

When a warning signal is supplied, the gamma voltage selection output unit 320 sets the source driver IC 131 to output a DC voltage corresponding to an arbitrary gamma level among a plurality of gamma levels as a data voltage.

When a warning signal is supplied, the common voltage selection output unit 330 sets the source drive IC 131 to output a DC voltage corresponding to the common voltage level as a data voltage.

The switching unit 340 connects either the gamma voltage selection output unit 320 or the common voltage selection output unit 330 to the signal transmission unit 350 . The switching unit 340 may select the gamma voltage selection output unit 320 capable of diversifying the output of the source drive IC 131 when the flicker phenomenon caused by the DC voltage accumulation is not severe. The switching unit 340 may select the common voltage selection output unit 330 when the flicker phenomenon is severe. Accordingly, the output of the source drive IC 131 may be selected according to the degree of occurrence of flicker using the switching unit 340 .

The signal transmission unit 350 is connected to either the gamma voltage selection output unit 320 or the common voltage selection output unit 330 by the switching unit 340 . When connected to the gamma voltage selection output unit 320, the signal transfer unit 350 controls the gamma voltage generator 360 to generate a gamma voltage. When connected to the common voltage selection output unit 330, the signal transfer unit 350 controls the common voltage generator 370 to generate a common voltage.

The gamma voltage generator 360 generates a gamma voltage under the control of the signal transfer unit 350 . The gamma voltage generator 360 supplies the gamma voltage to the first and second gamma voltage switching units 381 and 382 .

The common voltage generator 370 generates a common voltage under the control of the signal transfer unit 350 . The common voltage generator 370 supplies the common voltage to the third buffer 393 .

The first and second gamma voltage switching units 381 and 382 receive the gamma voltage from the gamma voltage generator 360 . The first gamma voltage switching unit 381 supplies a gamma voltage in a first range to the first buffer 391 . The second gamma voltage switching unit 382 supplies the gamma voltage in the second range to the second buffer 392 . The gamma voltage in the first range is a gamma voltage having a magnitude greater than or equal to the ground voltage and less than or equal to the common voltage. The gamma voltage in the second range is a gamma voltage having a magnitude greater than or equal to the common voltage and less than or equal to the maximum gamma voltage.

The first to third buffers 391 to 393 receive a common voltage or gamma voltage. The first to third buffers 391 to 393 supply the common voltage or gamma voltage to the output multiplexer 400 according to timing.

The output multiplexer 400 receives a common voltage or gamma voltage from the first to third buffers 391 to 393 . The output multiplexer 400 selects one of the common voltage and the gamma voltage and outputs it as an external voltage OUT.

The timing controller 160 of the display device according to the second and third embodiments of the present invention transmits a common voltage command signal Vcom_CMD that makes the data voltage Vdata equal to the common voltage Vcom to a plurality of source drive ICs. (131). The source driver IC 131 according to the second and third embodiments of the present invention makes the data voltage Vdata equal to the common voltage VCOM when the common voltage command signal Vcom_CMD is supplied. In the case of the third embodiment, when the common voltage command signal Vcom_CMD is supplied to the source driver IC 131, the switching unit 340 may be set to select the common voltage selection output unit 330.

In the case of the first embodiment of the present invention, when the source driver IC 131 supplies a DC voltage corresponding to one of the gamma voltage levels as a data voltage, the liquid crystal according to the size difference between the common voltage and the DC voltage The tilting phenomenon of is continuously intensified, resulting in a problem of flickering. On the other hand, in the second and third embodiments of the present invention, when the common voltage command signal Vcom_CMD is supplied to prevent flicker, the source driver IC 131 outputs the common voltage as a data voltage. You can control it. Accordingly, it is possible to prevent a difference between the common voltage and the data voltage from occurring, and thus, even when the polarity of the data voltage cannot be alternated, the flicker phenomenon can be prevented from occurring.

The timing controller 160 according to an example of the present invention supplies the POL signal POL for controlling the polarity of the data voltage Vdata to the plurality of source drive ICs 131 . At this time, the source drive IC 131 according to the second and third embodiments of the present invention makes the data voltage Vdata equal to the common voltage VCOM when the POL signal POL is not supplied.

In this case, the data voltage is not limited to the case where polarity control of the data voltage is impossible due to the abnormal EPI interface (ERR), but in all cases where the polarity control is impossible because the POL signal (POL) is not supplied to the source drive IC 131. can be output with the same magnitude as the common voltage. Therefore, the occurrence of flicker can be suppressed by outputting the data voltage with the same magnitude as the common voltage in all cases where polarity control is impossible.

FIG. 10 is a waveform diagram of respective voltages shown in FIG. 8 .

Display devices according to the second and third embodiments of the present invention supply the data voltage with the same magnitude as the common voltage Vcom. Accordingly, the display devices according to the second and third embodiments of the present invention can prevent the liquid crystal from being tilted due to the difference between the data voltage and the common voltage Vcom.

11 is a graph comparing degrees of flicker according to embodiments of the present invention.

The display device according to the first embodiment of the present invention has a first flicker level F1 at an initial point in time. As time elapses, the flicker level gradually decreases, and all flicker is removed at the first time point T1. However, since the size of the first flicker level F1 is large at an initial point in time, there is a problem in that flicker is recognized by the user.

On the other hand, the display devices according to the second and third embodiments of the present invention have a second flicker level F2 at an initial point in time. As time elapses, the second flicker level F2 gradually decreases, and all flicker is removed at the first time point T1. Also, since the size of the second flicker level F2 is small at the initial point of view, flicker is not recognized by the user. As a result of the experiment, the initial flicker generation level was 5 level in the case of the display device according to the first embodiment of the present invention, and 3 level level in the case of the display device according to the second and third embodiments of the present invention. Blicker generation level was reduced by about 40%.

As a result, the timing controller 160 according to the second and third embodiments of the present invention transmits the EPI signal (EPI), which is an interface signal for controlling the plurality of source drive ICs 131, to the plurality of source drive ICs 131. ) to supply The source driver IC 131 according to the second and third embodiments of the present invention makes the data voltage Vdata equal to the common voltage VCOM when an error occurs in the EPI signal EPI. Accordingly, the timing controller 160 according to the second and third embodiments of the present invention accumulates the amount of charge according to the continuous supply of the DC voltage on the display panel 110 by the data voltage output from the source drive IC 131. Therefore, it is possible to prevent the flicker phenomenon from being visually recognized.

A method of driving a display device according to an example of the present invention includes supplying, by a timing controller 160, digital video data DATA and a data driver control signal DCS to a plurality of source drive ICs 131, a plurality of The source drive ICs 131 supply the data voltage Vdata to the display panel 110, and the display panel 110 displays an image. The step of supplying the data voltage (Vdata) to the display panel 110 by the plurality of source drive ICs 131 of the present invention is the digital video data (DATA) by using the DAC 230 inside the source drive IC 131. ) into a data voltage Vdata.

In particular, when the source drive IC 131 is supplied with blank digital video data (BDATA), the DAC 230 of the display device driving method according to the second and third embodiments of the present invention outputs an internal common voltage selection. In unit 330, the data voltage Vdata is generated equal to the common voltage Vcom. Accordingly, even when the polarity of the data voltage Vdata cannot be alternated by receiving the blank digital video data BDATA, the liquid crystal tilting phenomenon due to the difference between the data voltage Vdata and the common voltage Vcom can be prevented. there is. In addition, when the liquid crystal is continuously tilted, a flicker phenomenon seen on the display panel 110 may also be prevented.

12 is a flowchart of a method of driving a display device according to an embodiment of the present invention.

The step of converting the digital video data (DATA) into the data voltage (Vdata) using the DAC 230 inside the source drive IC 131 according to the second and third embodiments of the present invention includes the following three steps. made up of

First, it detects the loss or alteration of interface signals. The normal interface signal is the EPI signal (EPI), and the abnormal EPI signal (ERR) is an interface signal from which information necessary for driving the source drive IC 131 is missing. In particular, it is possible to detect loss or change of the EPI signal (EPI) by determining whether or not the transmission clock (Tx clock) included in the EPI signal (EPI) is abnormal. (S1 in FIG. 12)

Second, select a common voltage level output. Selecting the common voltage level output is a step of setting the data voltage Vdata to be generated equal to the gamma voltage in the gamma voltage selection output unit 320, and setting the data voltage Vdata in the common voltage selection output unit 330 to the common voltage level. Step of setting to generate the same as the voltage Vcom, and connecting to the common voltage selection output unit 330 among the common voltage selection output unit 330 and the gamma voltage selection output unit 320 by using the switching unit 340 It includes steps to

Accordingly, if necessary, the data voltage Vdata may be set equal to the gamma voltage, or the data voltage Vdata may be set equal to the common voltage Vcom. Setting the same as the gamma voltage has the advantage that information previously stored in the timing controller 160 can be used as it is and no additional circuit configuration is required. Setting it equal to the common voltage has an advantage in effectively removing a flicker phenomenon on the display panel 110 . Accordingly, an appropriate voltage may be selected to be output as the data voltage according to the degree of flicker on the display panel 110 .

In particular, in order to reduce the flicker phenomenon, the timing controller 160 supplies the common voltage command signal Vcom_CMD to make the data voltage Vdata equal to the common voltage to the plurality of source drive ICs 131 . In this case, the source drive IC 131 makes the data voltage Vdata equal to the common voltage. That is, it is connected to the common voltage selection output unit 330 . Accordingly, the timing controller 160 may supply the common voltage command signal Vcom_CMD to set the common voltage effective for reducing the flicker phenomenon as the data voltage.

Alternatively, in a normal case, the timing controller 160 supplies the POL signal POL for controlling the polarity of the data voltage Vdata to the plurality of source drive ICs 131 . Accordingly, when the POL signal POL, which is an abnormal case, is not supplied, the source drive IC 131 may set the data voltage Vdata to be equal to the common voltage Vcom. In this case, in all cases where the polarity of the data voltage Vdata does not alternate normally, the occurrence of flicker can be fundamentally prevented by setting the data voltage to be the same as the common voltage. (S2 in Fig. 12)

Thirdly, the common voltage Vcom is output as the data voltage Vdata until a normal interface signal is received. When a normal interface signal is received, the data voltage Vdata by the digital video data DATA can be output, but until then, blank digital video data BDATA is supplied. Accordingly, the second and third embodiments of the present invention continuously output the common voltage Vcom as the data voltage Vdata while the abnormal interface signal is received, thereby preventing flicker from occurring. (S3 in Fig. 12)

In summary, the present invention adds a configuration for outputting a common voltage level in addition to digital video data of one of G0 to G255 generating DC voltages for blank digital video data output from the timing controller when an interface signal is lost or changed. Accordingly, the present invention can prevent the accumulation of DC voltage components due to the difference between the data voltage and the common voltage. In addition, the present invention can reduce the level of flicker generation by eliminating the effect of the accumulation of DC stress or the tendency of liquid crystals inside the display panel to accumulate due to the same polarity accumulation.

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and may be variously modified and implemented without departing from the technical spirit of the present invention. . Therefore, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be construed according to the claims, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

100: display device 110: display panel
111: thin film transistor substrate 112: counter substrate
120: gate driver 130: data driver
131: source drive IC 140: flexible circuit film
150: circuit board 160: timing controller
170: system board 180: PMIC
190: backlight driving unit 200: backlight unit
DA: display area P: pixels
T: transistor 11: pixel electrode
12: common electrode 13: liquid crystal layer
Cst: storage capacitor 210: shift register
220: latch 230: DAC
240: output buffer 250: serial-parallel converter
300: loss detection unit 320: gamma voltage selection output unit
330: common voltage selection output unit 340: switching unit
350: signal transfer unit 360: gamma voltage generator
370: common voltage generator 381, 382: first and second gamma voltage switching units
391 to 393: first to third buffers 400: output multiplexer

Claims (10)

a display panel displaying images;
a plurality of source drive ICs supplying data voltages to the display panel; and
A timing controller supplying digital video data and a data driver control signal to the plurality of source drive ICs;
Each of the plurality of source drive ICs includes a DAC that converts the digital video data into the data voltage;
The DAC has a common voltage selection output unit configured to generate the data voltage equal to a common voltage when the source drive IC is supplied with blank digital video data,
The timing controller supplies an EPI signal, which is an interface signal for controlling the plurality of source drive ICs, to the plurality of source drive ICs;
The source drive IC equalizes the data voltage to the common voltage when an error occurs in the EPI signal. According to claim 1,
The display device of claim 1 , wherein the DAC further includes a switching unit connected to an output unit of the common voltage selection output unit and a gamma voltage selection output unit outputting one of a plurality of gamma voltage values. According to claim 1,
The timing controller supplies a common voltage command signal for making the data voltage equal to a common voltage to the plurality of source drive ICs;
The source drive IC equalizes the data voltage to the common voltage when the common voltage command signal is supplied. According to claim 1,
The timing controller supplies a POL signal for controlling the polarity of the data voltage to the plurality of source drive ICs;
The source drive IC equalizes the data voltage to the common voltage when the POL signal is not supplied. delete supplying, by a timing controller, digital video data and a data driver control signal to a plurality of source drive ICs;
supplying data voltages to a display panel by the plurality of source driver ICs; and
The display panel is provided with a step of displaying an image,
The step of supplying the data voltage to the display panel by the plurality of source drive ICs includes converting the digital video data into the data voltage using a DAC inside the source drive IC,
When the source drive IC is supplied with blank digital video data, the DAC generates the data voltage equal to the common voltage from an internal common voltage selection output unit,
The step of converting the digital video data into the data voltage using a DAC inside the source drive IC,
detecting a loss or alteration of an interface signal;
selecting a common voltage level output; and
and outputting the common voltage as the data voltage until a normal interface signal is received. delete 7. The method of claim 6, wherein selecting the common voltage level output comprises:
setting the data voltage to be equal to the gamma voltage in a gamma voltage selection output unit;
setting the data voltage to be equal to the common voltage in a common voltage selection output unit; and
and connecting a common voltage selection output unit among the common voltage selection output unit and the gamma voltage selection output unit by using a switching unit. According to claim 6,
The timing controller supplies a common voltage command signal for making the data voltage equal to a common voltage to the plurality of source drive ICs;
The source drive IC equalizes the data voltage to the common voltage when the common voltage command signal is supplied. According to claim 6,
The timing controller supplies a POL signal for controlling the polarity of the data voltage to the plurality of source drive ICs;
The source drive IC equalizes the data voltage to the common voltage when the POL signal is not supplied.

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