KR20190031938A - A display device having a power supplier - Google Patents

Abstract

The present invention relates to a display device having a power supplier capable of preventing an overcurrent protective circuit from malfunctioning due to increase in a normal peak current according to an environmental condition during normal driving of the display device. According to one embodiment of the present invention, the power supplier receives any one of a plurality of basic timing control signals from a timing controller and varies a level of a standard signal becoming the standard when an overcurrent is sensed during a specific section of a vertical blank period. The power supplier receives a blank reset signal from the timing controller and varies a first standard voltage from a first level to a second level, wherein the first standard voltage becomes the standard when an overcurrent is sensed during a specific section that the blank reset signal has a specific level according to control of the blank reset signal.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a display device having a power supply unit,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device having a power supply unit capable of preventing an overcurrent protection circuit from malfunctioning due to an increase in normal peak current according to environmental conditions during normal driving of a display device.

Recently, display devices that display images using digital data include liquid crystal displays (LCDs) using liquid crystals, OLED displays using organic light emitting diodes, electrophoretic displays using electrophoretic particles ElectroPhoretic Display (EPD).

The display device includes a panel for displaying an image through a pixel array in which each pixel is independently driven by a thin film transistor (TFT), a gate driver and a data driver for driving the panel, a gate driver and a data driver And the like.

Recently, a gate driver is formed together with a TFT array of a pixel array, and a gate-in-panel (GIP) type built in a panel is applied.

The power supply unit incorporates an overcurrent protection circuit that senses an overcurrent caused by a short-circuit failure or the like in the display device, and protects the display device from an overcurrent by shutting off the power supply when sensing the occurrence of an overcurrent.

However, when the display device is driven for a long time in a high-temperature environment, the normal peak current due to the operation of the transistors in the gate driver may increase, and the input voltage of the power supply portion may drop. At this time, there is a problem that the overcurrent protection circuit recognizes that the overcurrent is generated and that the power supply part is turned off during the normal driving of the display device.

The present invention provides a display device having a power supply unit capable of preventing a malfunction of an overcurrent protection circuit due to an increase in normal peak current according to environmental conditions during normal operation of a display device.

A display device according to an embodiment includes a timing controller, a gate driver, and a power supply unit. The power supply unit according to an exemplary embodiment receives one of the plurality of basic timing control signals from the timing controller and varies the level of the reference signal as a reference when sensing the overcurrent during a specific section of the vertical blank period.

The voltage supply unit according to an embodiment receives a blank reset signal from the timing controller and, under the control of the blank reset signal, sets the first reference voltage, which is a reference for overcurrent sensing during a specific period in which the blank reset signal has a specific level, Level to the second level.

The power supply unit according to an embodiment includes a voltage conversion unit that boosts an input voltage to a first drive voltage by using current charge and discharge of the inductor and outputs the voltage, and an overcurrent protection circuit connected to the voltage conversion unit. The overcurrent protection circuit according to an embodiment compares a voltage generated at a sensing node connected to an output terminal of a first switching transistor for controlling current charging and discharging of an inductor in a voltage converting unit and a first reference voltage generated at a reference node And a first comparator for outputting an overcurrent protection signal according to the comparison result.

In a first period in which the blank reset signal has a first voltage level, the first comparator compares the voltage of the sensing node with the first level of the first reference voltage generated at the reference node. In the second period in which the blank reset signal has the second voltage level, the first comparator compares the voltage of the sensing node with the second level of the first reference voltage generated at the reference node.

The overcurrent protection circuit according to one embodiment includes first and second current sources connected in parallel with a reference node and a switching transistor for selectively connecting either the first or the second current source to the reference node in response to the blank reset signal do.

In a first period in which the blank reset signal has a first voltage level, the first and second current sources are all connected to the reference node, and at the reference node, the combined current of the first current of the first current source and the second current of the second current source A first reference voltage having a first level is generated. In the second period in which the blank reset signal has the second voltage level, only one of the first and second current sources is connected to the reference node, and at the reference node, the second level Lt; RTI ID = 0.0 > 1 < / RTI > The second level of the first reference voltage is less than the first level.

The overcurrent protection circuit further includes a second comparator for comparing the blank reset signal and the second reference voltage to control the switching transistor.

The power supply unit of the display apparatus according to an exemplary embodiment supplies a timing control signal, which is used for controlling the gate driver in the vertical blank period, from the timing controller to vary the reference voltage (current) level of the overcurrent protection circuit, It is possible to vary the level of protection for limiting the overcurrent for at least a part of the period.

Accordingly, even if the power supply unit of the display apparatus according to the embodiment has a period in which the display apparatus is driven for a long time in a high-temperature environment and the normal peak current increases somewhat during the operation of resetting the transistors in the vertical blank period in the built- It is possible to prevent the normal peak current from being sensed as the occurrence of the overcurrent by varying the protection level in the overcurrent protection circuit during the period. As a result, it is possible to prevent the failure that the power supply portion is turned off by the overcurrent protection circuit.

1 is a system block diagram schematically showing a configuration of a display device according to an embodiment of the present invention.
2 is a block diagram showing a circuit configuration directly or indirectly connected to a gate driver in a display device according to an embodiment of the present invention.
3 is a waveform diagram illustrating output signals of a timing controller and input signals of a gate driver according to an exemplary embodiment of the present invention.
FIG. 4 is a simulation waveform diagram illustrating a change in input voltage and input current during a vertical blanking period between a power supply unit and a conventional power supply unit according to an exemplary embodiment of the present invention.
5 is a circuit diagram showing an internal configuration of a power supply unit according to an embodiment of the present invention.
6 is an operational waveform diagram of an overcurrent protection circuit according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram schematically showing a configuration of a display device according to an embodiment of the present invention.

1, a display device includes a panel 100, a gate driver 200, a data driver 300, a timing controller 400, a power supply unit 500, a level shifter 600, a gamma voltage generator 700 ) And the like.

The panel 100 displays an image through a pixel array in which subpixels SP independently connected to a gate line GL and a data line DL are arranged in a matrix form. The basic pixel can be composed of at least three subpixels capable of white representation by color mixing among white (W), red (R), green (G) and blue (B) subpixels. For example, the basic pixel may be subpixels of R / G / B combination, subpixels of W / R / G combination, subpixels of B / W / R combination, subpixels of G / Or a combination of W / R / G / B combinations of subpixels.

The panel 100 may be a variety of display panels such as an LCD panel or an OLED panel, or a touch-sensitive display panel having a touch sensing function.

The gate driver 200 individually drives the gate lines GL of the panel 100 using a plurality of gate control signals supplied from the level shifter 600. [ The gate driver 200 supplies a scan pulse of a gate on voltage VGH (gate high voltage) to the corresponding gate line GL during a scan period in which the corresponding gate line GL is driven, The gate-off voltage VGL (gate-low voltage) is supplied to the corresponding gate line GL.

The gate driver 300 is formed on the thin film transistor substrate together with the thin film transistor array constituting the pixel array of the panel 100 so as to be built in a GIP (Gate In Panel) type embedded in the non-display region of the panel 100 .

The gate driver 200 is formed of a plurality of gate ICs and is individually mounted on a circuit film such as a COF (Chip On Film) or the like to be bonded to the panel 100 by TAB (Tape Automatic Bonding) Glass or the like.

The gamma voltage generator 700 generates a reference gamma voltage set including a plurality of reference gamma voltages having different voltage levels and supplies a reference gamma voltage set to the data driver 300. [

The data driver 300 converts the pixel data supplied from the timing controller 400 into an analog data signal in response to the data control signal supplied from the timing controller 400 and supplies the analog data signal to the data lines DL of the panel 100 Supply. The data driver 300 subdivides the reference gamma voltage set supplied from the gamma voltage generator 700 into a plurality of gradation voltages corresponding to the gradation values of the data. The data driver 300 converts the digital data into analog data voltages using the subdivided gradation voltages and supplies the data voltages to the data lines DL of the panel 100. [

When the panel 100 is an OLED panel, the data driver 300 further includes a sensing unit for sensing the pixel current including the electrical characteristics of each sub-pixel SP as a voltage and providing the sensing data to the timing controller 400 .

The data driver 300 may include a plurality of data ICs, may be mounted on a circuit film such as a COF, and may be bonded to the panel 100 by a TAB method or may be mounted on the panel 100 by a COG method.

The timing controller 400 receives image data and input timing control signals from the host system. The host system can be any one of a system of a portable terminal such as a computer, a TV system, a set-top box, a tablet or a cellular phone. The input timing control signals may include a dot clock, a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, and the like.

The timing controller 400 performs various image processes such as luminance correction and image quality correction to correct the image data supplied from the system to pixel data to be supplied to each subpixel SP and supplies the pixel data to the data driver 300 do.

The timing controller 400 controls the timing of driving the data driver 300 using the input timing control signals supplied from the system and the timing setting information (start timing, pulse width, etc.) And supplies the generated data to the data driver 300. For example, the plurality of data control signals may include a source start pulse used for controlling latch timing of data, a source sampling clock, a source output enable signal for controlling an output period of the data signal, and the like.

The timing controller 400 generates a plurality of basic timing control signals to be used as a reference for generating a plurality of gate control signals in the level shifter 600 using input timing control signals and internal timing setting information supplied from the system, And supplies it to the shifter 600.

The level shifter 600 generates and level-shifts a plurality of gate control signals using the plurality of basic timing control signals supplied from the timing controller 400, and supplies the gate control signals to the gate driver 200.

The power supply unit 500 includes all the circuit configurations of the display device, that is, the panel 100, the gate driver 200, the data driver 300, the timing controller 400, the level shifter 600 ), The reference gamma voltage generator 700, and the like. For example, the power supply unit 500 may supply the digital driving voltage supplied to the timing controller 400, the data driver 300, the level shifter 600, and the like to the data driver 300 using the input voltage, The gate-on voltage VGH and the gate-off voltage VGL supplied to the gate driver 200 and the level shifter 600 and the driving voltage necessary for driving the panel 100 and the like.

The power supply unit 500 includes an overcurrent protection circuit (OCP) and monitors whether or not an overcurrent occurs due to a short circuit or the like in a circuit component connected to the power supply unit 500. [ The power supply unit 500 is shut down when it senses the occurrence of an overcurrent through the OCP circuit, thereby protecting the entire display device from an overcurrent by cutting off the power supply.

In particular, the power supply unit 500 receives one of the basic timing control signals supplied from the timing controller 400 to the level shifter 600, receives a timing control signal, It is possible to vary the level of protection for limiting the overcurrent by varying the current (current) level.

For example, during the vertical blank period, the current increases due to the reset operation of the gate driver 200, so that a peak current occurs in the input current of the power supply unit 500, and the peak current A further rising section may occur.

The power supply unit 500 receives a blank reset signal for instructing a reset operation of the gate driver 200 during the vertical blank period from the timing controller 400 and outputs the blank reset signal during the ON period of the blank reset signal, The reference voltage (current) level of the OCP circuit can be varied (decreased) from the first level to the second level.

Accordingly, even when the peak current is generated by the reset operation of the gate driver 200 during the vertical blank period and the peak current further rises in accordance with the driving environmental condition (high temperature condition), the reference voltage (current It is possible to prevent the normal peak current from being sensed as an overcurrent, and as a result, it is possible to prevent a defect that the power supply portion is turned off by the OCP circuit.

FIG. 2 is a block diagram illustrating a circuit configuration that is directly or indirectly connected to a gate driver in a display device according to an exemplary embodiment of the present invention. FIG. Fig. 8 is a waveform diagram illustrating the input signals of Fig.

2 and 3, the timing controller 400 includes a plurality of basic timing control signals, that is, ON_CLK, OFF_CLK, a start signal GST, a blank reset signal TBRST, And generates an odd control pulse EO and supplies it to the level shifter 600. In addition, the timing controller 400 may further supply a dummy reset signal TDRST to the level shifter 600.

The level shifter 600 level-shifts the start signal GST and the blank reset signal TBRST supplied from the timing controller 400 and outputs a start signal VST having the gate-on voltage VGH and the gate- And supplies the blank reset signal BRST to the gate driver 200. [ The start signal VST indicates the start of the shift operation of the gate driver 200 for each frame and the blank reset signal BRST indicates the reset operation of the gate driver 200 in the vertical blank period.

The level shifter 600 determines the phase inversion timing of the even AC voltage EVEN and the odd AC voltage ODD in response to the even and odd control pulse EO supplied from the timing controller 400, Inverts the phases of the odd AC voltage (EVEN) and the odd AC voltage (ODD) and supplies them to the gate driver (200). The odd AC voltage EVEN and the od AC voltage ODD are used as the driving voltages of the transistors alternately driven in the even frame and odd frame in the gate driver 200.

The level shifter 600 generates k-phase clocks CLK1 to CLKk whose phases are sequentially shifted by logically calculating an ON clock CLK and an OFF clock CLK from the timing controller 400, 200). 3, a rising time at which each of the k-phase clocks CLK1 to CLKk rises from the gate-low voltage VGL to the gate-high voltage VGH is determined by the rising time of each of the ON clocks ON_CLK do. Each of the k-phase clocks CLK1 to CLKk falls from the gate high voltage VGL to the intermediate voltage Vdd due to the rising time of each of the on-clocks ON_CLK and the plurality of off-clocks OFF_CLK having a phase difference The polling time is determined and the polling time at which each of the clocks CLK1 to CLKk falls from the intermediate voltage Vdd to the gate-low voltage VGL is determined by the polling time of each off-clock OFF_CLK. Each of the k-phase clocks (CLK1 to CLKk) has a form in which an adjacent clock and a certain high interval overlap each other.

The gate driver 200 starts the shift operation in response to the start signal VST supplied from the level shifter 600 and sequentially selects the k-phase clocks CLK1 to CLKk alternately to select the gate lines GL1 to GLn As a scan signal. The gate driver 200 receives the blank reset signal BRST from the level shifter 600 during the vertical blank period, and simultaneously resets the plurality of stages connected to the plurality of gate lines GL.

For example, each of the plurality of stages constituting the gate driver 200 may include a pair of pull-down transistors connected in parallel with each gate line GL to reduce gate bias stress for a pull- And a pull-down transistor. In each stage, a pair of pull-down transistors alternately operates every odd / even frame to supply a gate-off voltage VGL to the corresponding gate line GL. The gate driver 200 uses either the blank reset signal BRST supplied in the vertical blanking period and any one pull-down transistor in the turn-on state of the pair of pull-down transistors in each of the plurality of stages is turned off And a reset operation for turning on the other pull-down transistor in the turn-off state.

As a result, the current is increased by the reset operation of the gate driver 200 in the vertical blanking period, and the input current Vin by the input voltage Vin of the power supply unit 500 as shown in Figs. 4 (a) and 4 The input voltage Vin can be lowered while the peak current is generated and the peak current can be further increased when the device is driven for a long time in a high temperature environment so that the input voltage Vin can be further lowered.

However, in the conventional power supply unit, the OCP circuit senses a peak current that has risen in a high temperature environment to an overcurrent, shutting down the power supply unit, so that the power supply VDD is turned off as shown in FIG. 4 Failure may occur.

On the other hand, the power supply unit 500 according to an exemplary embodiment receives the blank reset signal TBRST from the timing controller 400 and outputs the reference voltage (current) of the OCP circuit during the ON period of the blank reset signal TBRST ) Level, it is possible to prevent an increased peak current from being sensed as an overcurrent according to a high temperature environment. As a result, as shown in FIG. 4 (b), even if the input voltage Vin is slightly lowered due to the rise of the normal peak current during the ON period of the blank reset signal TBRST, the power off failure can be prevented. On the other hand, since the falling of the input voltage Vin occurs in the vertical blanking period, it does not affect the display of the image by lighting the data signal to the panel 100 in the active period of the vertical synchronizing signal.

FIG. 5 is a circuit diagram showing an internal configuration of a power supply unit according to an embodiment of the present invention, and FIG. 6 is an operation waveform diagram of an overcurrent protection circuit according to an embodiment of the present invention.

Referring to FIG. 5, a power supply unit 500 according to an exemplary embodiment includes a voltage conversion unit 510 and an OCP circuit 520.

The voltage converting unit 510 boosts the input voltage Vin to the first driving voltage AVDD (analog driving voltage) and outputs it through the output node OUT. The power supply unit 500 further includes a plurality of voltage conversion units for generating and outputting a gate-on voltage VGH, a gate-off voltage VGL, and the like using the first driving voltage AVDD.

The voltage converting unit 510 includes an inductor L connected between the supply line of the input voltage Vin and the input node IN, a first switching transistor SW1 connected between the input node IN and the ground, A second switching transistor SW2 connected between the input node IN and the output node OUT; an output capacitor C connected between the output node OUT and the ground; And a controller 512 for controlling the first and second switching transistors SW1 and SW2 by generating a pulse width modulation (PWM) signal according to a voltage applied to the first and second switching transistors SW1 and SW2.

The voltage converting unit 510 alternately switches the first and second switching devices SW1 and SW2 according to the PWM control of the controller 512 receiving the feedback voltage. When the first switching device SW1 is turned on and the second switching device SW2 is turned off, the inductor L charges the input current, and when the first switching device SW1 is turned off, When the element SW2 is turned on, the inductor L is added to the input voltage Vin while discharging the charging current, thereby outputting the first driving voltage AVDD which is larger than the input voltage Vin.

The first and second switching transistors SW1 and SW2 may be any one of an NMOS transistor and a PMOS transistor. For example, the first switching transistor SW1 may be an NMOS transistor, and the second switching transistor SW2 may be a PMOS transistor.

The OCP circuit 520 is connected to a sensing node SN located between the source terminal of the first switching transistor SW1 and the ground to sense the occurrence of an overcurrent. When the overcurrent is sensed, the OCP circuit 520 outputs an OCP signal to the controller 512 , The control unit 512 controls the power supply unit 500 to cut off the power supply.

In particular, the OCP circuit 520 receives the blank reset signal TBRST from the timing controller 400 and varies the reference voltage (current) level according to the voltage level of the blank reset signal TBRST.

The OCP circuit 520 includes a first comparator 526 for comparing the first reference voltage VREF1 generated at the reference node RN with the input voltage Vin generated at the sensing node SN, The first and second current sources 522 and 524 connected in parallel with the timing controller 400 and the first and second current sources 522 and 524 in response to the blank reset signal TBRST supplied from the timing controller 400 And a third switching transistor SW3 for selectively connecting to the reference node RN. The OCP circuit 520 may further include a second comparator 528 for controlling the switching of the third switching transistor SW3 by comparing the blank reset signal TBRST with the second reference voltage VREF2. The third switching transistor SW3 may be an NMOS transistor or a PMOS transistor. For example, the third switching transistor SW3 may be an NMOS transistor.

The first input terminal (+) of the first comparator 526 is connected to the sensing node SN to supply the input voltage supplied to the sensing node SN via the input node IN and the first switching transistor SW1 And the second input terminal (-) is connected to the reference node RN and is supplied with the first reference voltage VREF1 generated at the reference node RN.

When an overcurrent occurs in a circuit component connected to the power supply unit 500, the voltage of the input node IN is lowered as the input current supplied through the input node IN is increased, so that the first switching transistor SW1 The voltage generated at the sensing node SN also falls. Accordingly, when the voltage on the sensing node SN is lowered due to the overcurrent generation, the first comparator 526 outputs the OCP signal indicating the overcurrent generation when the voltage on the sensing node SN becomes smaller than the first reference voltage VREF1 generated in the reference node RN. . On the other hand, if the voltage on the sensing node SN is larger than the first reference voltage VREF1, the OCP signal is not outputted because it is in a normal operating state.

The second comparator 528 receives the blank reset signal TBRST from the timing controller 400 at the first input terminal + and compares the second reference voltage VREF2 supplied to the second input terminal - The blank reset signal TBRST outputs an off signal as the control signal Vout during the high level period and outputs the on signal as the control signal Vout during the remaining low level period.

The third switching transistor SW3 selectively connects the second current source 524 to the reference node RN in response to the control signal Vout according to the blank reset signal TBRST.

Level response of the output signal Vout of the second comparator 528 when the blank reset signal TBRST is a low level period in the vertical blank period Vblank as shown in Fig. 3 switching transistor SW3 is turned on. The first current source 522 and the second current source 524 are connected to the reference node RN both of the first current source 522 and the second current source 524, The first reference voltage VREF1 of the first level corresponding to the combined current value (A1 + A2) synthesized with the second current value A2 supplied from the second current source A2 is generated. Accordingly, the OCP circuit 520 outputs the OCP signal when the input voltage dropped by the occurrence of the overcurrent becomes smaller than the first level of the first reference voltage VREF1.

In response to the off level of the output signal Vout of the second comparator 528 when the blank reset signal TBRST is a high level period in the vertical blanking period Vblank, the third switching transistor SW3 Turn off. Accordingly, only the first current source 522 is connected to the reference node RN, and the first reference voltage VREF1 corresponds to the first current value A1 supplied from the first current source 522, (Reduced) to two levels.

Accordingly, during the high-level period of the blank reset signal TBRST, the current increases due to the reset operation of the gate driver 200 and the input current of the power supply unit 500 increases, so that the voltage on the sensing node SN increases Since the reference level of the first reference voltage VREF1 of the OCP circuit 520 has decreased from the first level to the second level even if the level of the input voltage VREF1 is lower than the first level of the reference voltage VREF1, Does not output the OCP signal unless it is lowered below the second level of the first reference voltage VREF1.

Accordingly, even if the peak current is generated by the reset operation of the gate driver 200 during the vertical blank period and the peak current further rises according to the driving environmental condition (high temperature condition), the reference of the OCP circuit 520 It is possible to prevent the normal peak current from being sensed as an overcurrent as the voltage (current) level is varied, and as a result, it is possible to prevent the defect that the power supply portion is turned off by the OCP circuit.

Meanwhile, the power supply unit 500 may change the current value of the first current source 522 by adding an option, thereby changing the current value of the second current source 522 of the first reference voltage VREF1 during the high level period of the blank reset signal TBRST. The level can be varied.

As described above, the power supply unit of the display device according to the embodiment supplies a timing control signal, which is used for controlling the gate driver in the vertical blank period, from the timing controller to the reference voltage (current) level of the overcurrent protection circuit It is possible to vary the level of protection for limiting the overcurrent during at least a part of the vertical blanking period.

Accordingly, even if the power supply unit of the display apparatus according to the embodiment has a period in which the display apparatus is driven for a long time in a high-temperature environment and the normal peak current increases somewhat during the operation of resetting the transistors in the vertical blank period in the built- It is possible to prevent the normal peak current from being sensed as the occurrence of the overcurrent by varying the protection level in the overcurrent protection circuit during the period. As a result, it is possible to prevent the failure that the power supply portion is turned off by the overcurrent protection circuit.

The foregoing description is merely illustrative of the present invention, and various modifications may be made by those skilled in the art without departing from the spirit of the present invention. Accordingly, the embodiments disclosed in the specification of the present invention are not intended to limit the present invention. It is intended that the scope of the invention be interpreted by the claims appended hereto, and that all techniques within the scope of equivalents thereof should be construed as being included within the scope of the present invention.

100: panel 200: gate driver
300: Data driver 400: Timing controller
500: Power supply unit 600: Level shifter
700: gamma voltage generator

Claims (6)

A timing controller for generating and supplying a plurality of basic timing control signals,
A level shifter for generating and supplying a plurality of gate control signals using a plurality of basic timing control signals supplied from the timing controller,
A gate driver for individually driving gate lines of the panel using a plurality of gate control signals supplied from the level shifter,
And a power supply unit for generating and supplying a plurality of driving voltages required for driving the timing controller, the level shifter, and the panel and gate driver using an input voltage,
The power supply unit
Wherein the timing controller is adapted to receive any one of the plurality of basic timing control signals and vary the level of the reference signal as a reference when sensing an overcurrent during a specific period of a vertical blanking period. The method according to claim 1,
The voltage supply unit
A second reset signal is supplied from the timing controller to a first reference voltage, which is a reference for the overcurrent sensing during the specific period in which the blank reset signal has a specific level, under the control of the blank reset signal, Level. The method of claim 2,
The power supply unit
A voltage conversion unit for boosting the input voltage to a first drive voltage using the current charge / discharge of the inductor,
And an overcurrent protection circuit connected to the voltage conversion unit,
The overcurrent protection circuit
The voltage converting unit compares the voltage generated at the sensing node connected to the output terminal of the first switching transistor for controlling current charging and discharging of the inductor with the first reference voltage generated at the reference node, And a first comparator for outputting an overcurrent protection signal to the voltage converter,
Wherein the first comparator compares a first level of the first reference voltage generated at the reference node with a voltage of the sensing node in a first period in which the blank reset signal has a first voltage level,
And a second comparator for comparing a second level of the first reference voltage generated at the reference node with a voltage of the sensing node in a second period in which the blank reset signal has a second voltage level of the specific level, Device. The method of claim 3,
The overcurrent protection circuit
First and second current sources connected in parallel with the reference node,
And a switching transistor for selectively connecting any one of the first and second current sources to the reference node in response to the blank reset signal,
Wherein the first and second current sources are all connected to the reference node in the first period in which the blank reset signal has the first voltage level, The first reference voltage having the first level is generated corresponding to the combined current of the second current of the current source,
In the second period in which the blank reset signal has the second voltage level, only one of the first and second current sources is connected to the reference node, and in the reference node, any one of the first and second current sources And the first reference voltage having the second level is generated corresponding to the current. The method of claim 4,
The overcurrent protection circuit
And a second comparator for comparing the blank reset signal with a second reference voltage to control the switching transistor. The method of claim 4,
Wherein the second level of the first reference voltage is less than the first level.

Images