KR20120041453A - Scan pulse switching circuit and display device using the same - Google Patents

Abstract

PURPOSE: A scan pulse switching circuit and a display apparatus using the same are provided to apply a scan pulse only to an arbitrary pixel, thereby calculating a degradation degree of an organic light emitting diode and threshold voltage of a driving transistor of a specific pixel. CONSTITUTION: A first transistor(M1) supplies activation voltage of a scan pulse to a gate line. The scan pulse is outputted from a scan driving part. A second transistor(M2) supplies deactivation voltage of the scan pulse to the gate line. One or more pulses of a switching circuit output enable signal which are synchronized with a gate output enable signal.

Description

SCAN PULSE SWITCHING CIRCUIT AND DISPLAY DEVICE USING THE SAME}

The present invention relates to a scan pulse switching circuit and a display device using the same.

As the information society develops, the demand for a display device for displaying an image is increasing in various forms. Recently, a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting diode are being developed. Various flat panel display devices such as organic light emitting diodes (OLEDs) are utilized. Among these flat panel display devices, organic light emitting diode display devices are capable of low voltage driving, are thin, have excellent viewing angles, and have fast response speeds. As the organic light emitting diode display, an active matrix type organic light emitting diode display, in which a plurality of pixels are positioned in a matrix and displaying an image, is widely used.

1 is an equivalent circuit diagram of a pixel of a conventional active matrix type organic light emitting diode display. Referring to FIG. 1, a display panel of an active matrix type organic light emitting diode display includes a plurality of pixels defined by scan lines GLn (n is a natural number) and data lines DLm and m are a natural number. Each of the pixels generally drives a scan transistor Tscan for supplying a data voltage in response to a scan pulse of a scan line, and a drive for adjusting the amount of current supplied to the organic light emitting diode OLED according to the data voltage supplied to a gate electrode. It is implemented with a transistor Td. However, due to the deviation of the threshold voltage of the driving transistor Td generated among the plurality of pixels, the current supplied to the organic light emitting diode OLED has a value different from the desired value, so that the luminance of the emitted light is a target. Different from the value.

In addition, when a current is supplied to the organic light emitting diode OLED for a long time, the organic light emitting diode OLED is deteriorated. When the organic light emitting diode OLED is deteriorated, the luminance of emitted light is different from the target value, and the lifespan of the organic light emitting diode OLED is reduced.

In order to solve the problem caused by the deviation of the threshold voltage of the driving transistor Td generated between the plurality of pixels and the difference in the degree of deterioration of the organic light emitting diode OLED, the threshold voltage of the driving transistor Td of the pixels is solved. And deterioration of the organic light emitting diode (OLED). For this purpose, the threshold voltage of the driving transistor Td of the pixels and the degradation of the organic light emitting diode OLED should be measured. However, in order to measure the threshold voltage of the driving transistor Td of the arbitrary pixel and the degree of deterioration of the organic light emitting diode OLED, only the arbitrary pixel to be measured should be driven, and a scan pulse is applied only to the arbitrary pixel to be measured. There is no way to do it.

The present invention provides a scan pulse switching circuit capable of applying a scan pulse only to an arbitrary pixel to be measured and a display device using the same.

The scan pulse switching circuit of the present invention includes a first transistor for supplying an activation voltage of a scan pulse output from a scan driver to a gate line in response to a pulse of a switching circuit output enable signal; And a second transistor configured to supply an inactive voltage of the scan pulse to the gate line in response to a pulse of an inversion signal of a switching circuit output enable signal, wherein the switching circuit output enable signal is at least a gate output enable signal. It is characterized in that more than one pulse is synchronized.

The scan pulse switching circuit of the present invention includes: a first transistor supplying an activation voltage of a scan pulse output from a scan driver to a gate line in response to a voltage of a first node; A second transistor configured to supply an inactive voltage of the scan pulse to the gate line in response to a pulse of an inverted signal of a switching circuit output enable signal; A third transistor configured to supply an activation voltage of the first transistor to the first node in response to a pulse of the switching circuit output enable signal; And a fourth transistor configured to supply an inactive voltage of the first transistor to the first node in response to a pulse of an inversion signal of the switching circuit output enable signal, wherein the switching circuit output enable signal is a gate output enable signal. At least one pulse is synchronized with the signal.

According to an exemplary embodiment, a display device includes: an active region in which gate lines intersect data lines and includes a plurality of pixels formed in the intersected region; A scan driver which sequentially outputs scan pulses to the gate lines; A data driver supplying data voltages to the data lines; And a scan pulse switching circuit positioned between the scan driver and the active region to selectively block the scan pulse, wherein the scan pulse switching circuit is output from the scan driver in response to a pulse of a switching circuit output enable signal. A first transistor configured to supply an activation voltage of a scan pulse to a gate line; And a second transistor configured to supply an inactive voltage of the scan pulse to the gate line in response to a pulse of an inversion signal of a switching circuit output enable signal, wherein the switching circuit output enable signal is at least a gate output enable signal. It is characterized in that more than one pulse is synchronized.

According to an exemplary embodiment, a display device includes: an active region in which gate lines intersect data lines and includes a plurality of pixels formed in the intersected region; A scan driver which sequentially outputs scan pulses to the gate lines; A data driver supplying data voltages to the data lines; And a scan pulse switching circuit positioned between the scan driver and the active region to selectively block the scan pulse, wherein an activation voltage of the scan pulse output from the scan driver in response to the voltage of the first node is applied to the gate line. A first transistor to supply; A second transistor configured to supply an inactive voltage of the scan pulse to the gate line in response to a pulse of an inverted signal of a switching circuit output enable signal; A third transistor configured to supply an activation voltage of the first transistor to the first node in response to a pulse of the switching circuit output enable signal; And a fourth transistor configured to supply an inactive voltage of the first transistor to the first node in response to a pulse of an inversion signal of the switching circuit output enable signal, wherein the switching circuit output enable signal is a gate output enable signal. At least one pulse is synchronized with the signal.

The present invention forms a scan pulse switching circuit so that the scan pulse can be applied only to any pixel to be measured between the scan driver and the active region. As a result, the present invention can calculate the threshold voltage of the driving transistor of a specific pixel and the degree of deterioration of the organic light emitting diode. Furthermore, according to the present invention, the threshold voltage of the driving transistor of a specific pixel and the deterioration of the organic light emitting diode can be compensated for, thereby matching the luminance of light emitted from the organic light emitting diode with the target value.

1 is a circuit diagram of a pixel of a conventional active matrix type organic light emitting diode display.
2 is a block diagram illustrating an organic light emitting diode display according to an exemplary embodiment of the present invention.
FIG. 3 is a diagram showing a scan pulse switching circuit, a pixel circuit, and a current path in a normal mode as a first embodiment of the present invention.
FIG. 4 is a diagram showing a scan pulse switching circuit, a circuit of a pixel, and a current path in a sampling mode for sampling a current passing through a driving transistor as a first embodiment of the present invention.
FIG. 5 is a diagram illustrating a scan pulse switching circuit, a circuit of a pixel, and a current path in a sampling mode in which a current of an organic light emitting diode is sampled as a first embodiment of the present invention.
6A is a waveform diagram illustrating an output of a shift register and a gate output enable signal input to a scan pulse switching circuit in a normal mode.
6B is a waveform diagram illustrating an inverted signal of an output waveform of a scan pulse switching circuit, a switching circuit output enable signal, and a switching circuit output enable signal in a normal mode.
7A is a waveform diagram illustrating an output of a shift register and a gate output enable signal input to a scan pulse switching circuit in a sampling mode.
7B is a waveform diagram illustrating an inverted signal of an output waveform of a scan pulse switching circuit, a switching circuit output enable signal, and a switching circuit output enable signal in a sampling mode.
FIG. 8 is a diagram showing a scan pulse switching circuit, a pixel circuit, and a current path in a normal mode as a second embodiment of the present invention.
FIG. 9 is a diagram illustrating a scan pulse switching circuit, a circuit of a pixel, and a current path in a sampling mode for sampling a current passing through a driving transistor as a second embodiment of the present invention.
FIG. 10 is a diagram illustrating a scan pulse switching circuit, a circuit of a pixel, and a current path in a sampling mode for sampling a current of an organic light emitting diode as a second embodiment of the present invention.
11 is a waveform diagram illustrating scan pulses output from scan pulse switching circuits according to the first and second embodiments of the present invention.
12 is a waveform diagram illustrating a difference between an input scan pulse and an output scan pulse of the scan pulse switching circuit according to the first and second embodiments of the present invention.
13 is a block diagram illustrating in detail a data drive IC according to an embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like numbers refer to like elements throughout. In the following description, when it is determined that a detailed description of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

The display device of the present invention is a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), an organic light emitting diode (Organic Light Emitting Diode) OLED) such as a flat panel display device. Although the present invention is illustrated mainly with respect to the organic light emitting diode display device in the following embodiment, it should be noted that the present invention is not limited to the organic light emitting diode display device.

The names of the components used in the following description are selected in consideration of the ease of preparation of the specification, and may be different from the names of the actual products.

2 is a block diagram illustrating a display device including a scan pulse switching circuit according to an exemplary embodiment of the present invention. Referring to FIG. 2, the display device of the present invention includes a display panel 10, a timing controller 20, a data driving circuit, a scan driving circuit, a scan pulse switching circuit 60, and the like.

The display panel 10 includes data lines and gate lines crossing each other, and an active region 10a in which a plurality of pixels are arranged in a matrix. Each pixel of the active area 10a of the display panel 10 will be described later with reference to FIG. 3.

The data driver circuit includes a plurality of source drive ICs 30. The source drive ICs 30 receive the digital video data RGB from the timing controller 20. The source drive ICs 30 convert the digital video data RGB into a gamma compensation voltage in response to a source timing control signal from the timing controller 20 to generate a data voltage, and synchronize the data voltage with a scan pulse. The data lines of the display panel 10 are supplied. The source drive ICs 30 may be connected to data lines of the display panel 10 by a chip on glass (COG) process or a tape automated bonding (TAB) process.

In addition, referring to FIG. 3, the source drive ICs 30 may use the sampling transistor Tsamp in the pixel, the current I _TD of the driving transistor Td in the pixel, or the current I _OLED of the organic light emitting diode _OLED. ) Is inputted. The source drive ICs 30 may calculate the threshold voltage of the driving transistor Td from the current I _TD of the driving transistor Td and calculate a compensation data value according to the threshold voltage of the driving transistor Td. have. In addition, the source drive ICs 30 may calculate a compensation data value according to the current I _OLED of the organic light emitting diode OLED. The source drive ICs 30 may modulate the data voltage according to the compensation data value according to the threshold voltage of the driving transistor Td or the compensation data value according to the current I _OLED of the organic light emitting diode OLED to display the display panel 10. Supply to the data lines DL). Detailed description thereof will be described later with reference to FIG. 8.

The scan driving circuit is connected to the level shifter 40 and the gate lines connected between the timing controller 20 and the gate lines of the display panel 10 to control the scan transistor Tscan of each pixel. The shift register 50 is provided. The level shifter 40 level shifts the TTL logic level voltages of the gate shift clocks GCLKs input from the timing controller 20 to the gate high voltage VGH and the gate low voltage VGL. do. The shift register 50 shifts the gate start pulse GSP according to the gate shift clocks GCLKs, and sequentially outputs the scan pulse SP to the gate lines.

The scan driving circuit may further include a sampling driver (not shown) connected to the sampling pulse lines SPL to supply the sampling pulse SMP to the sampling transistor Tsam of each pixel. The sampling driver not shown outputs the sampling pulse SMP for controlling the sampling transistor Tsam of each pixel through the sampling pulse line SPL.

The scan pulse switching circuit 60 is positioned between the output terminal of the shift register 50 and the gate lines of the active region 10a. The scan pulse switching circuit 60 selectively blocks the scan pulse SP output from the shift register 50 under the control of the timing controller 20. A detailed description of the scan pulse switching circuit 60 will be described later with reference to FIG. 3.

The shift register 50 and the scan pulse switching circuit 60 are directly formed on the lower substrate of the display panel 10 by a gate drive-IC in panel (GIP) method. The shift register 50 and the scan pulse switching circuit 60 may be connected between the gate lines of the display panel 10 and the timing controller 20 in a TAB manner. In the GIP method, the level shifter 40 may be mounted on the PCB 80, and the shift register 50 and the scan pulse switching circuit 60 may be formed on the lower substrate of the display panel 10. In addition, the power supply unit 70 may be mounted on the PCB 80, and the power supply unit 70 supplies a power supply voltage VDD for driving the organic light emitting diode OLED to the display panel 10 and through a switch. The first sampling voltage Vsamp1 is supplied to the cathode of the organic light emitting diode OLED, and the second sampling voltage Vsamp2 is supplied to the sampling line through a switch.

The timing controller 20 receives digital video data (RGB) from an external host computer through an interface such as a low voltage differential signaling (LVDS) interface and a transition minimized differential signaling (TMDS) interface. The timing controller 20 transmits digital video data RGB input from the host computer to the source drive ICs 30.

The timing controller 20 receives timing signals such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, a main clock, and the like from a host computer through an LVDS or TMDS interface receiving circuit. The timing controller 20 generates timing control signals for controlling the operation timing of the data driving circuit, the scan driving circuit, and the switch block 60 based on the timing signal from the host computer. The timing control signals include a scan timing control signal for controlling an operation timing of the scan driving circuit, a scan pulse switching circuit 60 timing control signal for controlling an operation timing of the scan pulse switching circuit, and an operation of the source drive ICs 30. And a data timing control signal for controlling the timing and polarity of the data voltage.

The scan timing control signal includes a gate start pulse GSP, gate shift clocks GCLKs, a gate output enable signal GOE, and the like. The gate start pulse GSP is input to the shift register 50 to control the shift start timing. The gate shift clocks GCLKs are input to the level shifter 40, level shifted, and then input to the shift register 50, and are used as clock signals for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output timing of the shift register 50.

The scan pulse switching circuit 60 timing control signal includes a switching circuit output enable signal (SCOE), and an inverted signal SCOEB of the switch circuit output enable signal. The switching circuit output enable signal SCOE is synchronized with at least one pulse with the gate output enable signal GOE. The switching circuit output enable signal SCOE and the inversion signal SCOEB of the switching circuit output enable signal selectively output the scan pulse SP input to the scan pulse switching circuit 60 to the active region 10a. Block it. Detailed description thereof will be described later with reference to FIGS. 9 and 10.

The data timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (Polarity, POL), a source output enable signal (Source Output Enable, SOE), and the like. It includes. The source start pulse SSP controls the shift start timing of the source drive ICs 30. The source sampling clock SSC is a clock signal that controls the sampling timing of data in the source drive ICs 30 based on the rising or falling edge. The polarity control signal POL controls the polarity of the data voltages output from the source drive ICs. If the data transfer interface between the timing controller 20 and the source drive ICs 30 is a mini LVDS interface, the source start pulse SSP and the source sampling clock SSC may be omitted.

3 to 5 show a scan pulse switching circuit 60, a circuit of the pixel 10b, and a current path as a first embodiment of the present invention. 3 to 5, the nth (n is a natural number) scan pulse switching circuit 60 selectively blocks the nth scan pulse SPn output from the nth shift register. That is, the n th scan pulse switching circuit 60 outputs the n th scan pulse SPn or the gate high voltage VGH to the n th gate line GLn.

3 to 5, the nth scan pulse switching circuit 60 includes a first transistor M1 and a second transistor M2. In the nth scan pulse switching circuit 60, the gate electrode of the first transistor M1 is connected to the output terminal of the switching circuit output enable signal SCOE, the source electrode is connected to the output terminal of the nth shift register, and the drain The electrode is connected to the nth gate line GLn. The gate electrode of the second transistor M2 is connected to the output terminal of the inverted signal SCOEB of the switching circuit output enable signal, the source electrode is connected to the gate high voltage VGH, and the drain electrode is the nth gate line GLn. ).

In the nth scan pulse switching circuit 60, the first transistor M1 is turned on in response to the switching circuit output enable signal SCOE of the low logic voltage, thereby outputting the nth shift register SR_out (n). The n th scan pulse SPn is synchronized to the n th gate line GLn. The second transistor M2 is turned on in response to the inversion signal GOEB of the gate output enable signal of the low logic voltage to supply the gate high voltage VGH to the nth gate line GLn.

The pixel 10b supplied with the nth scan pulse SPn or the gate high voltage VGH output from the nth scan pulse switching circuit 60 may include a scan transistor Tscan, a driving transistor Td, and a sampling transistor. (Tsamp) and the like. The gate electrode of the scan transistor Tscan is connected to the nth gate line GLn, the source electrode is connected to the mth (m is a natural number) data line DLm, and the drain electrode is connected to the N1 node N1. . The gate electrode of the driving transistor Td is connected to the N1 node N1, the source electrode is connected to the power supply voltage wiring VDDL, and the drain electrode is connected to the N2 node N2. The gate electrode of the sampling transistor Tsamp is connected to the n th sampling pulse line SPLn, the source electrode is connected to the N2 node N2, and the drain electrode is connected to the m th sampling line SLm. The m th sampling line SLm is connected to the second sampling voltage Vsamp2 through the second switch SW2. The first capacitor Cst1 keeps the voltage of the N1 node N1 constant.

The first electrode of the organic light emitting diode OLED, that is, the anode electrode is connected to the N2 node N2, and the second electrode of the organic light emitting diode OLED, that is, the cathode electrode is the ground voltage GND. Or is connected to the first sampling voltage Vsamp1. The cathode electrode is selectively connected to the ground voltage GND or the first sampling voltage Vsamp1 through the first switch SW1.

First, with reference to FIG. 3, the scan pulse switching circuit 60, the circuit of the pixel 10b, and the current path in the normal mode will be described. This will be described in detail with reference to FIGS. 6A and 6B. The normal mode is a mode in which each pixel normally displays an image without measuring the current I _TD passing through the driving transistor Td or the current of the organic light emitting diode OLED.

6A and 6B, in the normal mode, the gate electrode of the first transistor M1 of the nth scan pulse switching circuit 60 has a switching circuit output enable synchronized with the gate output enable signal GOE. The signal SCOE is input. The inversion signal SCOEB of the switching circuit output enable signal is input to the gate electrode of the second transistor M2. When the first transistor M1 is turned on in response to the switching circuit output enable signal SCOE of the low logic voltage, the nth scan pulse SPn output from the nth shift register is the nth gate as shown in FIG. 6B. It is output to the line GLn.

Referring to FIG. 3, in the normal mode, the scan transistor Tscan of the pixel 10b is turned on in response to the nth scan pulse SPn of the low logic voltage, thereby causing the data voltage of the mth data line DLm. Is supplied to N1 node N1. The first capacitor Cst1 keeps the voltage of the N1 node N1 constant. The driving transistor Td differently adjusts the amount of current I _TD passing through the driving transistor Td according to the level of the data voltage applied to the gate electrode.

In the normal mode, the sampling transistor Tsamp should not be turned on because it does not measure the current I _TD passing through the driving transistor Td, or the current of the organic light emitting diode OLED. Therefore, a sampling pulse of a high logic voltage is input to the n th sampling pulse line SPLn. In addition, the cathode of the organic light emitting diode OLED is connected to the ground voltage GND through the first switch SW1. As a result, since the sampling transistor Tsamp is not turned on, the current I _TD passing through the driving transistor Td flows through the N2 node to the anode electrode of the organic light emitting diode OLED, and the organic light emitting diode ( OLED) emits light.

Secondly, as a first embodiment of the present invention with reference to FIG. 4, the scan pulse switching circuit, the circuit of the pixel, and the current path in the sampling mode for sampling the current passing through the driving transistor will be described. This will be described in detail with reference to FIGS. 7A and 7B. The sampling mode is a mode for measuring the current I _TD passing through the driving transistor Td or the current of the organic light emitting diode OLED.

7A and 7B, in the sampling mode, switching in which the gate electrode of the first transistor M1 of the nth scan pulse switching circuit 60 is synchronized with the gate output enable signal GOE for at least one pulse or more. The circuit output enable signal SCOE is input. For example, as shown in FIGS. 7A and 7B, the switching circuit output enable signal SCOE may be synchronized only with the third pulse period of the gate output enable signal GOE. The inversion signal SCOEB of the switching circuit output enable signal is input to the gate electrode of the second transistor M2.

When the scan pulse SPn output from the nth shift register is synchronized with the switching circuit output enable signal SCOE, the nth scan pulse switching circuit 60 stores the nth scan pulse SPn as shown in FIG. 7B. Output to n gate line GLn. 7A and 7B, the first, second, and fourth scan pulses SP1, SP2, and SP4 output from the first, second, and fourth shift registers are synchronized with the switching circuit output enable signal SCOE. Although not, the third scan pulse SP3 output from the third shift register is synchronized with the switching circuit output enable signal SCOE.

The first transistor M1 of the first, second, and fourth scan pulse switching circuits 60 is not turned on due to the switching logic output enable signal SCOE of the high logic voltage, but the second transistor M2 is not turned on. ) Is turned on in response to the inversion signal SCOEB of the switching circuit output enable signal of the low logic voltage. Thus, each of the first, second, and fourth scan pulse switching circuits 60 supplies a gate high voltage VGH to each of the first, second, and fourth gate lines GL1, GL2, GL4. do.

The first transistor M1 of the third scan pulse switching circuit 60 is turned on in response to the switching circuit output enable signal SCOE of the low logic voltage, but the second transistor M2 is switching of the high logic voltage. It is not turned on due to the inverted signal SCOEB of the circuit output enable signal. Therefore, the third scan pulse switching circuit 60 supplies the third scan pulse SP3 output from the third shift register to the third gate line GL3.

As a result, according to the present invention, by adjusting the switching circuit output enable signal SCOE input to the nth scan pulse switching circuit 60, the scan pulse can be output only to the gate line to which the scan pulse is to be output. The current I _TD passing through the driving transistor Td of the pixel or the current I _OLED of the organic light emitting diode OLED may be measured. One or more gate lines to output scan pulses may be selected, and any pixel may be selected to one or more.

Referring to FIG. 4, in the sampling mode in which the current I _TD passing through the driving transistor Td is measured, the scan pulse switching circuit 60 applies the nth scan pulse SPn to the nth gate line GLn. Output The scan transistor Tscan of the pixel 10b is turned on in response to the nth scan pulse SPn of the low logic voltage to supply the data voltage of the mth data line DLm to the N1 node N1. The first capacitor Cst1 keeps the voltage of the N1 node N1 constant. The driving transistor Td differently adjusts the amount of current I _TD passing through the driving transistor Td according to the level of the data voltage applied to the gate electrode.

In the sampling mode for measuring a current (I _TD) which has passed through the driving transistor (Td), it should measure a current (I _TD) through the drive transistor (Td), the sampling transistor (Tsamp) is turned to be ON. In addition, the cathode of the organic light emitting diode OLED is connected to the first sampling voltage Vsamp1 through the first switch SW1. The organic light emitting diode OLED is turned off by setting the first sampling voltage Vsamp1 equal to or higher than the voltage of the anode electrode of the organic light emitting diode OLED. As a result, since the organic light emitting diode OLED is not turned on, the current I _TD passing through the driving transistor Td is supplied to the sampling transistor Tsamp via the N2 node N2. When the sampling transistor Tsamp is turned on in response to the n th sampling pulse of the low logic voltage, the current I _TD passing through the driving transistor Td flows through the sampling transistor to the m th sampling line SLm. . The m th sampling line SLm is connected to the source drive ICs 30, and the source drive IC 30 measures the current of the m th sampling line SLm and drives the driving transistor Td from the measured current value. Calculate the threshold voltage of. The source drive IC 30 using the threshold voltage of the driving transistor Td will be described later with reference to FIG. 13.

Third, as a first embodiment of the present invention with reference to FIG. 5, in the sampling mode for sampling the current I _OLED of the organic light emitting diode OLED, a scan pulse switching circuit, a circuit of pixels, and a current path. Explain. The sampling mode is a mode for measuring the current I _TD passing through the driving transistor Td or the current of the organic light emitting diode OLED. The description of the scan pulse switching circuit 60 of FIG. 5 is as described above with reference to FIGS. 7A and 7B.

Referring to FIG. 5, in the sampling mode in which the current I _OLED of the organic light emitting diode OLED is measured, the scan pulse switching circuit 60 outputs the gate high voltage VGH to the nth gate line GLn. . The scan transistor Tscan of the pixel 10b is not turned on due to the gate high voltage VGH of the nth gate line GLn. Therefore, since no data voltage is applied to the gate electrode of the driving transistor Td, the driving transistor Td is not turned on.

In the sampling mode in which the current I _OLED of the organic light emitting diode _OLED is measured, the sampling transistor Tsamp should be turned on because the current I _OLED of the organic light emitting diode OLED should be measured. In addition, the cathode of the organic light emitting diode OLED is connected to the ground voltage GND through the first switch SW1, and the m th sampling line SLm is connected to the second sampling voltage through the second switch SW2. Vsamp2). The second sampling voltage Vsamp2 is a voltage equal to or greater than a threshold voltage at which the organic light emitting diode OLED is turned on and may be set as a voltage between the ground voltage GND and the power supply voltage VDD.

When the sampling transistor Tsamp is turned on in response to the n th sampling pulse of the low logic voltage, the second sampling voltage Vsamp2 is applied to the anode electrode of the organic light emitting diode OLED, so that the organic light emitting diode OLED is It emits light. Since the m th sampling line SLm is connected to the source drive ICs 30, the source drive IC 30 measures the current of the m th sampling line SLm, whereby the current I of the organic light emitting diode OLED is measured. _OLED ) can be measured. Data compensation of the source drive IC 30 using the current I _OLED of the organic light emitting diode OLED will be described later with reference to FIG. 13.

However, when the first transistor M1 of the n th scan pulse switching circuit 60 of FIGS. 3 to 5 is turned on, the switching circuit output enable signal GOE is input to the gate electrode, and the source electrode is provided to the source electrode. n scan pulse SPn is input. At this time, since there is no voltage difference between the gate electrode and the source electrode of the first transistor M1, the nth scan pulse SPn output from the nth scan pulse switching circuit 60 is changed by the characteristics of the first transistor M1. There is a problem of delay and voltage drop. Hereinafter, a display device including the scan pulse switching circuit 60 according to the second embodiment of the present invention which solves such a problem will be described.

8 to 10 show a scan pulse switching circuit 60, a circuit of the pixel 10b, and a current path as a second embodiment of the present invention. 8 to 10, the n th scan pulse switching circuit 60 selectively blocks the scan pulse SP output from the n th shift register. That is, the n th scan pulse switching circuit 60 outputs the n th scan pulse SPn or the gate high voltage VGH to the n th gate line GLn.

8 to 10, the nth scan pulse switching circuit 60 may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and the like. do. The gate electrode of the first transistor M1 is connected to the N3 node N3, the source electrode is connected to the output terminal of the nth shift register, and the drain electrode is connected to the nth gate line GLn. The gate electrode of the second transistor M2 is connected to the output terminal of the inverted signal SCOEB of the switching circuit output enable signal, the source electrode is connected to the gate high voltage VGH, and the drain electrode is the nth gate line GLn. ). The gate electrode of the third transistor M3 is connected to the output terminal of the switching circuit output enable signal SCOE, the source electrode is connected to the gate low voltage VGL, and the drain electrode is connected to the N3 node N3. The gate electrode of the fourth transistor M4 is connected to the output terminal of the inverted signal SCOEB of the switching circuit output enable signal, the source electrode is connected to the N3 node N3, and the drain electrode is connected to the gate high voltage VGH. Connected. The second capacitor Cst2 keeps the voltage of the N3 node N3 constant.

The third transistor M3 is turned on in response to the switching circuit output enable signal SCOE of the low logic voltage to discharge the N3 node N3 to the gate low voltage VGL. The first transistor M1 is turned on in response to the gate low voltage VGL of the N3 node N3 to transfer the nth scan pulse SPn output from the nth shift register to the nth gate line GLn. Supply.

The second transistor M2 is turned on in response to the inverted signal SCOEB of the switching circuit output enable signal of the low logic voltage to supply the gate high voltage VGH to the nth gate line GLn. The fourth transistor M4 is turned on in response to the inversion signal SCOEB of the switching circuit output enable signal of the low logic voltage to charge the N3 node N3 to the gate high voltage VGH.

First, with reference to FIG. 8, the scan pulse switching circuit 60, the circuit of the pixel 10b, and the current path in the normal mode will be described. This will be described in detail with reference to FIGS. 6A and 6B.

6A and 6B, in the normal mode, the gate electrode of the third transistor M3 of the nth scan pulse switching circuit 60 has a switching circuit output enable synchronized with the gate output enable signal GOE. The signal SCOE is input. The inversion signal SCOEB of the switching circuit output enable signal is input to the gate electrodes of the second and fourth transistors M2 and M4. When the third transistor M3 is turned on in response to the switching circuit output enable signal SCOE of the low logic voltage, the N3 node N3 is discharged to the gate low voltage VGL. Since the N3 node N3 is discharged to the gate low voltage VGL, the first transistor M1 is turned on in response to the gate low voltage VGL. Therefore, the n th scan pulse SPn output from the n th shift register is output to the n th gate line GLn as shown in FIG. 6B.

Description of the circuit of the pixel 10b of FIG. 8 is as described with reference to FIG. 3.

Secondly, as a second embodiment of the present invention with reference to FIG. 9, the scan pulse switching circuit, the circuit of the pixel, and the current path in the sampling mode for sampling the current passing through the driving transistor will be described. This will be described in detail with reference to FIGS. 7A and 7B.

7A and 7B, in the sampling mode, the gate electrode of the third transistor M3 of the nth scan pulse switching circuit 60 is partially synchronized with at least one pulse with the gate output enable signal GOE. The switching circuit output enable signal SCOE in which the section is synchronized is input. The inversion signal SCOEB of the switching circuit output enable signal is input to the gate electrodes of the second and fourth transistors M2 and M4. When the third transistor M3 is turned on in response to the switching circuit output enable signal SCOE of the low logic voltage, the N3 node N3 is discharged to the gate low voltage VGL. Since the N3 node N3 is discharged to the gate low voltage VGL, the first transistor M1 is turned on in response to the gate low voltage VGL. Therefore, the n th scan pulse SPn output from the n th shift register is output to the n th gate line GLn as shown in FIG. 7B.

For example, as shown in FIGS. 7A and 7B, the switching circuit output enable signal SCOE is only synchronized with the third pulse section of the gate output enable signal GOE. The first, second, and fourth scan pulses SP1, SP2, SP4 output from the first, second, and fourth shift registers are not synchronized with the switching circuit output enable signal SCOE, but have a third shift. The third scan pulse SP3 output from the register is synchronized with the switching circuit output enable signal SCOE.

The third transistor M3 of the first, second, and fourth scan pulse switching circuits 60 is not turned on due to the switching logic output enable signal SCOE of the high logic voltage, The four transistors M2 and M4 are turned on in response to the inversion signal SCOEB of the switching circuit output enable signal of the low logic voltage. When the fourth transistor M4 is turned on, since the N3 node N3 is charged to the gate high voltage VGH, the gate high voltage VGH is applied to the gate electrode of the first transistor M1. It is not on. In addition, since the second transistor M2 is turned on, each of the first, second, and fourth scan pulse switching circuits 60 sets the gate high voltage VGH to the first, second, and fourth gates. Supply to each of the lines GL1, GL2, GL4.

The third transistor M3 of the third scan pulse switching circuit 60 is turned on in response to the switching circuit output enable signal SCOE of the low logic voltage, but the second and fourth transistors M2 and M4 are turned on. Is not turned on due to the inverted signal SCOEB of the switching circuit output enable signal of the high logic voltage. When the third transistor M3 is turned on, since the N3 node N3 is discharged to the gate low voltage VGL, the gate electrode of the first transistor M1 is turned on in response to the gate low voltage VGL. do. Therefore, the third scan pulse switching circuit 60 supplies the third scan pulse SP3 output from the third shift register to the third gate line GL3.

As a result, according to the present invention, by adjusting the switching circuit output enable signal SCOE input to the nth scan pulse switching circuit 60, the scan pulse can be output only to the gate line to which the scan pulse is to be output. The current I _TD passing through the driving transistor Td of the pixel or the current I _OLED of the organic light emitting diode OLED may be measured. One or more gate lines to output scan pulses may be selected, and any pixel may be selected to one or more.

Description of the circuit of the pixel 10b of FIG. 9 is as described with reference to FIG. 4.

Third, as a second embodiment of the present invention with reference to FIG. 10, in the sampling mode for sampling the current I _OLED of the organic light emitting diode OLED, a scan pulse switching circuit, a circuit of a pixel, and a current path are used. Explain. The sampling mode is a mode for measuring the current I _TD passing through the driving transistor Td or the current of the organic light emitting diode OLED. The description of the scan pulse switching circuit 60 of FIG. 10 is as described above with reference to FIGS. 7A and 7B.

Description of the circuit of the pixel 10b of FIG. 10 is as described with reference to FIG. 5.

11 is a waveform diagram showing an output waveform of the scan pulse switching circuit 60 according to the first and second embodiments of the present invention. Referring to FIG. 11, the output waveform W1 of the first embodiment of the present invention does not fall to the gate low voltage VGL which is the target low logic voltage. Further, experiments show that the output waveform W1 of the first embodiment of the present invention takes approximately 830.57ns to drop to 90% of the gate low voltage (90% Voltage of VGL). The output waveform W2 of the second embodiment of the present invention drops to the gate low voltage VGL. In addition, the output waveform W2 of the second embodiment of the present invention takes approximately 306.27ns to drop to 90% (90% Voltage of VGL) of the gate low voltage. Therefore, it can be seen that the delay of the output waveform W2 of the second embodiment of the present invention is improved.

12 is a waveform diagram showing a difference between an input scan pulse and an output scan pulse of the scan pulse switching circuit 60 according to the first and second embodiments of the present invention. Referring to FIG. 12, the difference G1 between the input and output waveforms of the first embodiment of the present invention occurs around 2V. There is almost no difference G2 between the input and output waveforms of the second embodiment of the present invention. Accordingly, it can be seen that the output waveform W2 of the second embodiment of the present invention does not generate a voltage drop, and the output waveform W2 and the input waveform are almost the same.

11 and 12, the scan pulse switching circuit 60 of the second embodiment of the present invention outputs the same output waveform as the input waveform. In addition, the scan pulse switching circuit 60 of the second embodiment of the present invention outputs a scan pulse SP without a delay and without a voltage drop to the gate lines GL.

13 is a block diagram illustrating in detail a data drive IC according to an embodiment of the present invention. The data drive IC 30 of the present invention will be described in detail with reference to Figs.

The data drive IC 30 of the present invention includes a compensation controller 31, a look-up table 32, a current measuring unit 33, an analog converter 34, and the like. The current measuring unit 33 is connected to the sampling line SL to measure the current of the sampling line SL. The current measuring unit 33 may measure the current I _TD passing through the driving transistor Td or the current I _OLED of the organic light emitting diode in the sampling line SL.

First, the current measuring unit 33 may measure the current I _TD passing through two or more different driving transistors Td according to two or more different data voltages supplied to the pixel. The current measuring unit 33 may include a threshold voltage calculator (not shown) for calculating the threshold voltage of the driving transistor Td from the current I _TD passing through two or more other driving transistors Td. The current measuring unit 33 outputs the threshold voltage to the look-up table 32 in which the compensation data value according to the calculated threshold voltage is stored. The look-up table 32 stores a compensation data value according to a threshold voltage of the driving transistor Td predetermined by an experiment. The look-up table 32 receives the threshold voltage of the driving transistor Td from the current measuring unit 33 and outputs the compensation data value stored at the corresponding address to the compensation controller 31.

Second, the current measuring unit 33 outputs the current I _OLED of the organic light emitting diode to the look-up table 32 in which a compensation data value corresponding to the current I _OLED of the organic light emitting diode is stored. When the second sampling voltage Vsamp2 is connected to the anode electrode of the OLED and the ground voltage GND is connected to the cathode of the look-up table 32, the organic light emission predetermined by experiment is determined. The compensation data value according to the current I _OLED of the diode is stored. The look-up table 32 receives the current I _OLED of the organic light emitting diode from the current measuring unit 33, and outputs the compensation data value stored at the address to the compensation controller 31.

The compensation controller 31 outputs the RGB data RGB 'reflecting the compensation data value to the RGB converter RGB input from the timing controller 20 to the analog converter 34. The analog converter 34 converts the digital RGB data RGB 'reflecting the compensation data value into an analog data voltage and outputs them to the data lines DL.

However, when measuring the current I _TD passing through the driving transistor Td or the current I _OLED of the organic light emitting diode OLED, the source drive IC 30 may not compensate for the data voltage (data line). Output in DL).

The transistors exemplify a case of implementing a P-type MOS-FET, wherein the gate low voltage VGL is an activation voltage for turning on the transistors, and the gate high voltage VGH turns off the transistors. Is an inactive voltage. In addition, the voltage level of the low logic voltage is equal to the gate low voltage VGL, and the voltage level of the high logic voltage is equal to the gate high voltage VGH. Furthermore, the transistors may be implemented as an N-type MOS-FET, where the gate high voltage VGH becomes an activation voltage for turning on the transistors.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

10: display panel 10a: active area
10b: pixel 20: timing controller
30: source drive IC 31: current measurement unit
32: look-up table 33: compensation control unit
34: analog converter 40: level shifter
50: shift register 60: scan pulse switching circuit
70: power supply 80: PCB

Claims (18)

A first transistor configured to supply an activation voltage of a scan pulse output from the scan driver to the gate line in response to a pulse of the switching circuit output enable signal; And
A second transistor configured to supply an inactive voltage of the scan pulse to the gate line in response to a pulse of an inversion signal of a switching circuit output enable signal,
And the switching circuit output enable signal is synchronized with at least one pulse with a gate output enable signal. A first transistor configured to supply an activation voltage of a scan pulse output from the scan driver to the gate line in response to a voltage of the first node;
A second transistor configured to supply an inactive voltage of the scan pulse to the gate line in response to a pulse of an inverted signal of a switching circuit output enable signal;
A third transistor configured to supply an activation voltage of the first transistor to the first node in response to a pulse of the switching circuit output enable signal; And
A fourth transistor configured to supply an inactive voltage of the first transistor to the first node in response to a pulse of an inversion signal of the switching circuit output enable signal,
And the switching circuit output enable signal is synchronized with at least one pulse with a gate output enable signal. The method of claim 2,
And a capacitor connected between the output terminal of the scan driver and the first node. An active region intersecting gate lines and data lines and including a plurality of pixels formed in the intersected region;
A scan driver which sequentially outputs scan pulses to the gate lines;
A data driver supplying data voltages to the data lines; And
A scan pulse switching circuit positioned between the scan driver and the active region to selectively block the scan pulse;
The scan pulse switching circuit,
A first transistor configured to supply an activation voltage of a scan pulse output from the scan driver to the gate line in response to a pulse of the switching circuit output enable signal; And
A second transistor configured to supply an inactive voltage of the scan pulse to the gate line in response to a pulse of an inversion signal of a switching circuit output enable signal,
And the switching circuit output enable signal is synchronized with at least one pulse with a gate output enable signal. The method of claim 4, wherein
The active region,
Sampling pulse lines parallel to the gate lines; And
And sampling lines parallel to the data lines. The method of claim 5, wherein
Each of the pixels,
A scan transistor configured to receive a data voltage from the data line in response to an activation voltage of a scan pulse of the gate line;
A driving transistor configured to adjust a current supplied to an N2 node according to the level of the data voltage in response to the data voltage;
An organic light emitting diode that emits light according to the current of the N2 node;
And a sampling transistor that is turned on in response to an activation voltage of a sampling pulse of a sampling pulse line to supply a current of the N2 node to a sampling line. The method according to claim 6,
And an anode electrode of the organic light emitting diode is connected to the N2 node, and a cathode electrode of the organic light emitting diode is connected to a ground voltage or a first sampling voltage higher than the voltage of the N2 node. The method according to claim 6,
And the sampling line is connected to a second sampling voltage higher than a threshold voltage of the organic light emitting diode through a second switch. The method according to claim 6,
The data driver may include:
A current measuring unit measuring a current of the sampling line;
A threshold voltage calculator configured to calculate a threshold voltage of the driving transistor from the measured current of the sampling line;
A look-up table storing a compensation data value according to the threshold voltage;
A compensation controller which reflects a compensation data value according to the threshold voltage to digital data output from a timing controller; And
And an analog converter which converts the digital data compensated by the compensation controller into an analog data voltage and outputs the analog data to the data lines. The method according to claim 6,
The data driver may include:
A current measuring unit measuring a current of the sampling line;
A look-up table for storing a compensation data value according to the measured current of the sampling line;
A compensation controller reflecting a compensation data value according to the current of the organic light emitting diode in digital data output from a timing controller; And
And an analog converter configured to convert the digital data compensated by the compensation controller into an analog data voltage and output the analog data voltage. An active region intersecting gate lines and data lines and including a plurality of pixels formed in the intersected region;
A scan driver which sequentially outputs scan pulses to the gate lines;
A data driver supplying a data voltage to the data lines
A scan pulse switching circuit positioned between the scan driver and the active region to selectively block the scan pulse;
A first transistor configured to supply an activation voltage of a scan pulse output from the scan driver to the gate line in response to a voltage of the first node;
A second transistor configured to supply an inactive voltage of the scan pulse to the gate line in response to a pulse of an inverted signal of a switching circuit output enable signal;
A third transistor configured to supply an activation voltage of the first transistor to the first node in response to a pulse of the switching circuit output enable signal; And
A fourth transistor configured to supply an inactive voltage of the first transistor to the first node in response to a pulse of an inversion signal of the switching circuit output enable signal,
And the switching circuit output enable signal is synchronized with at least one pulse with a gate output enable signal. The method of claim 11,
The scan pulse switching circuit further comprises a capacitor connected between the output terminal of the scan driver and the first node. The method of claim 11,
The active region,
Sampling pulse lines parallel to the gate lines; And
And sampling lines parallel to the data lines. The method of claim 11,
Each of the pixels,
A scan transistor configured to receive a data voltage from the data line in response to an activation voltage of a scan pulse of the gate line;
A driving transistor configured to adjust a current supplied to an N2 node according to the level of the data voltage in response to the data voltage;
An organic light emitting diode that emits light according to the current of the N2 node;
And a sampling transistor that is turned on in response to an activation voltage of a sampling pulse of a sampling pulse line to supply a current of the N2 node to a sampling line. 15. The method of claim 14,
And an anode electrode of the organic light emitting diode is connected to the N2 node, and a cathode electrode of the organic light emitting diode is connected to a ground voltage or a first sampling voltage higher than the voltage of the N2 node. 15. The method of claim 14,
And the sampling line is selectively connected to a second sampling voltage higher than a threshold voltage of the organic light emitting diode through a second switch. 15. The method of claim 14,
The data driver may include:
A current measuring unit measuring a current of the sampling line;
A threshold voltage calculator configured to calculate a threshold voltage of the driving transistor from the measured current of the sampling line;
A look-up table storing a compensation data value according to the threshold voltage;
A compensation controller which reflects a compensation data value according to the threshold voltage to digital data output from a timing controller; And
And an analog converter which converts the digital data compensated by the compensation controller into an analog data voltage and outputs the analog data to the data lines. 15. The method of claim 14,
The data driver may include:
A current measuring unit measuring a current of the sampling line;
A look-up table for storing a compensation data value according to the measured current of the sampling line;
A compensation controller reflecting a compensation data value according to the current of the organic light emitting diode in digital data output from a timing controller; And
And an analog converter configured to convert the digital data compensated by the compensation controller into an analog data voltage and output the analog data voltage.

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