KR102247133B1 - Display Device - Google Patents

Abstract

The display device of the present invention includes a display panel, a data driver, a boost converter, a PWM control unit, and a timing controller. Data lines are arranged on the display panel. The data driver provides a data voltage to the data line. The boost converter includes a switch element and outputs a reference voltage for setting a data voltage according to a turn-on and turn-off ratio of the switch element as an output voltage. The PWM control unit varies the frequency of the switch element. The timing controller sets a section that changes from the vertical blank period to the image display period as a frequency variable section, and controls the PWM control unit to increase the switching frequency of the switch element during the frequency variable section.

Description

Display Device

The present invention relates to a display device.

Flat panel displays include Liquid Crystal Display (LCD), Field Emission Display (FED), Plasma Display Panel (PDP), and Organic Light Emitting Diode Device (OLED). ) And so on. In the flat panel display, data lines and gate lines are arranged to be orthogonal, and a region where data lines and gate lines are orthogonal is defined as one pixel. A plurality of pixels are formed in a matrix form in the panel. In order to drive each pixel, a video data voltage to be displayed is supplied to the data lines and a gate pulse is sequentially supplied to the gate lines. In addition, the video data voltage is supplied to pixels of the display line to which the gate pulse is supplied, and all display lines are sequentially scanned by the gate pulse to display the video data.

The display device displays an image during an image display period of a frame, and has a vertical blank period in which no image is displayed between frames. Therefore, the data driver does not continuously output the data voltage for displaying an image, but has a pause period for outputting the data voltage. The load of the current rapidly changes between the period in which the data driver outputs the data voltage and the period in which the data voltage is not output. The data voltage is also distorted while the current load changes rapidly. If the data voltage is distorted, there is a problem in that the display quality is deteriorated in the process of displaying an image based on this.

An object of the present invention is to provide a display device for improving a phenomenon in which a data voltage is distorted when a current load is rapidly changed.

The display device of the present invention includes a display panel, a data driver, a boost converter, a PWM control unit, and a timing controller. Data lines are arranged on the display panel. The data driver provides a data voltage to the data line. The boost converter includes a switch element and outputs a reference voltage for setting a data voltage according to a turn-on and turn-off ratio of the switch element as an output voltage. The PWM control unit varies the frequency of the switch element. The timing controller sets a section that changes from the vertical blank period to the image display period as a frequency variable section, and controls the PWM controller to increase the switching frequency of the switch element during the frequency variable section.

The present invention can improve the distortion of the output voltage by increasing the switching speed of the switch element of the boost converter in a section in which the output of the data voltage is rapidly increased. Accordingly, the present invention can improve the display quality deterioration due to distortion of the output voltage.

1 is a view showing a display device according to the present invention.
2 and 3 are diagrams showing the configuration of a data driver according to the present invention.
4 is a diagram showing a boost converter according to the present invention.
5 and 6 are waveform diagrams showing an output voltage according to a switching frequency.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numbers throughout the specification mean substantially the same elements. In the following description, when it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, a detailed description thereof will be omitted.

Although the present specification describes the present invention based on an embodiment of a liquid crystal display device, the present invention relates to a field emission display (FED), a plasma display panel (PDP), and an organic light emitting diode device ( Organic Light Emitting Diode Device, OLED), etc. can also be applied.

1 is a diagram showing a liquid crystal display device according to the present invention. 2 and 3 are diagrams showing the configuration of a source drive IC.

Referring to FIG. 1, a liquid crystal display device of the present invention includes a display panel 100, source drive ICs 500, a level shifter 410, a shift register 420, a timing controller 300, and the like.

The display panel 100 displays input image data including a pixel array in which pixels arranged in a matrix form are formed. The pixel array includes a TFT array formed on a lower substrate, a color filter array formed on an upper substrate, and liquid crystal cells Clc formed between the lower substrate and the upper substrate. The TFT array includes a data line DL, a gate line GL crossing the data line DL, TFTs formed at each intersection of the data line DL and the gate line GL, and a pixel electrode 1 connected to the TFT. ), a storage capacitor Cst, and the like are formed. A color filter array including a black matrix and a color filter is formed in the color filter array. The common electrode 2 may be formed on the lower substrate or the upper substrate. The liquid crystal cells Clc are driven by an electric field between the pixel electrode 1 supplied with the data voltage and the common electrode 2 supplied with the common voltage Vcom. A polarizing plate having an orthogonal optical axis is attached to the upper substrate and the lower substrate of the display panel 100, and an alignment layer for setting a pretilt angle of the liquid crystal is formed at an interface in contact with the liquid crystal layer. A spacer for maintaining a cell gap of the liquid crystal layer is disposed between the upper and lower substrates of the display panel 100.

The power module 200 starts to operate when the input voltage Vin supplied through the connector 5 is higher than the UVLO level, and generates an output after a predetermined time is delayed. The output of the power module 200 includes VGH, VGL, VCC, VDD, RST, and the like. VCC is a logic power voltage for driving the timing controller 300, the source drive IC 500, and the like, and may be a voltage of 3.3V. VDD is a high-potential power supply voltage to be supplied to a voltage divider circuit of a gamma reference voltage generating circuit that generates positive/negative gamma reference voltages. Positive/negative gamma reference voltages are supplied to the source drive IC 500. RST is a reset signal for resetting the timing controller 300 and may be 3.3V.

The power module 200 includes a boost circuit to generate a high potential voltage VDD. The boost circuit controls the output voltage of the boost circuit based on the control signal Sf provided from the timing controller 300. A detailed description of this will be described later.

The timing controller 300 receives digital video data (RGB) from an external host through the connector 5, a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (Data Enable, DE), It receives a timing signal such as the main clock CLK. The timing controller 300 transmits digital video data RGB to the source drive ICs 500. The timing controller 300 uses a timing signal (Vsync, Hsync, DE, CLK) to control a source timing control signal for controlling the operation timing of the source drive IC 500, and a level shifter 410 and a shift of the gate driving circuit. Gate timing control signals ST, GCLK, and MCLK for controlling the operation timing of the register 420 are generated.

The timing controller 300 generates a control signal Sf based on the vertical synchronization signal Vsync and provides the control signal Sf to the power module 200. The control signal Sf serves as a reference for the power module 200 to select a switching frequency. A detailed description of this will be described later.

The data driver includes a plurality of source drive ICs (Integrated Circuit) 24. The source drive IC 500 receives digital video data RGB from the timing controller 300. The source drive IC 500 converts digital video data (RGB) into a positive/negative analog data voltage in response to a source timing control signal from the timing controller 300, and then converts the data voltage into a gate pulse (or scan). The data lines DL of the display panel 100 are supplied to be synchronized with the pulse).

Referring to FIG. 2, each source drive IC 500 includes a register unit 510, a first latch 520, a second latch 530, and a digital to analog converter (hereinafter, a DAC). It includes 540 and an output unit 550. The register unit 510 samples the RGB digital video data bits of the input image by using the data control signals SSC and SSP provided from the timing controller 300 and provides them to the first latch 520. The first latch 520 samples and latches digital video data bits according to a clock sequentially provided from the register unit 510, and simultaneously outputs the latched data. The second latch 530 latches data provided from the first latch 520 and latches in synchronization with the second latch 530 of the other source drive ICs 500 in response to the source output enable signal SOE. Print one data at the same time. The DAC 540 converts video data input from the second latch unit 530 into a gamma compensation voltage GMA to generate an analog video data voltage. The output unit 550 provides the analog data voltage ADATA output from the DAC 540 to the data lines DL during the low logic period of the source output enable signal SOE. The output unit 550 may be implemented as an output buffer that outputs a data voltage using a driving voltage using a low potential voltage GND and a voltage input through a high potential input terminal.

Referring to FIG. 3, the gamma reference voltage generation circuit includes a resistance string and first to ninth voltage followers GMA1 to GMA9. The resistance string includes first to eighth resistors R1 to R8. The resistance string divides the low potential voltage (GND) and the high potential voltage (VDD). The high potential voltage VDD is an output voltage Vout output from the output terminal Nout of the power module 200. The first to ninth voltage followers GMA1 to GMA9 output first to ninth gamma voltages gamma1 to gamma9 by enhancing the divided voltage output from the node between the respective resistors.

The GIP type gate driving circuit includes a level shifter 410 and a shift register 420 mounted on a printed circuit board (PCB).

The level shifter 410 receives a start pulse ST, a first clock GCLK, a second clock MCLK, and the like from the timing controller 300. In addition, the level shifter 410 receives driving voltages such as a gate high voltage VGH and a gate low voltage VGL. The start pulse ST, the first clock GCLK, and the second clock MCLK swing between 0V and 3.3V. The level shifter 410 has a gate high voltage VGH and a gate low voltage VGL in response to a start pulse ST, a first clock GCLK, and a second clock MCLK input from the timing controller 300, respectively. The start pulse VST and clock signals CLK1 to CLK6 swinging between are output. The clock signals CLK output from the level shifter 410 are sequentially shifted in phase and transmitted to the shift register 420 formed on the display panel 100.

The shift register 420 is connected to the gate lines GL of the display panel 100. The shift register 420 includes a plurality of stages that are dependently connected. The shift register 420 shifts the start pulse VST input from the level shifter 410 according to the clock signal CLK, and sequentially supplies the gate pulses to the gate lines GL.

4 is a diagram showing the power module of the present invention.

Referring to FIG. 2, the power module 200 includes a boost circuit 211, a voltage divider 213 and a PWM control unit 215.

The boost circuit 211 outputs a DC voltage obtained by multiplying the input voltage VIN. The boost circuit 211 includes a boost inductor (L), a switch element (SW1), a rectifier diode (D), and an output capacitor (C).

The switch element SW1 is turned on or turned off by a control signal Sf provided from the PWM control unit 215. The switch element SW1 controls the output voltage according to the ratio of the turn-on period and the turn-off period. When the switch element SW1 is turned on, the rectifier diode D enters a reverse bias state, and a current flows through the boost inductor L and the switch element SW1 so that the voltage of the boost inductor L increases. The current flowing through the boost inductor L and the switch element SW1 increases linearly to form an electromagnetic field. While the switch element SW1 is turned on, the current path through the rectifier diode D is cut off, and the voltage stored in the output capacitor C is output as the output voltage Vout. When the switch element SW1 is turned off, a current flows from the boost inductor L to the output terminal Nout via the rectifier diode D.

The voltage distribution unit 213 provides the feedback voltage 213 obtained by distributing the output voltage Vout of the boost circuit 211 to the PWM control unit 215. The voltage divider 213 may be implemented as a resistance string connected in series between the output terminal Nout and the base power supply. The feedback voltage VFB distributed by the first and second resistors R1 and R2 of the resistance string is output through a node between the first and second resistors R1 and R2.

The PWM control unit 215 outputs the first or second switching signals PWM1 and PWM2 based on the feedback voltage Vfb provided from the voltage distribution unit 213. The PWM control unit 215 outputs the first switching signal PWM1 while not receiving the control signal Sf from the timing controller 300, and outputs the second switching signal PWM2 while receiving the control signal Sf. Print it out. The first switching signal PWM1 and the second switching signal PWM2 are each controlled to turn on and off the switch element SW1 at predetermined intervals. The second switching signal PWM2 has a higher frequency compared to the first switching signal PWM1. Since the control signal Sf is output in the vertical blank period Tb, eventually the PWM control unit 215 controls the switch element SW1 at a higher frequency in the vertical blank period Tb than in the image display period Tdp.

The second switching signal PWM2 having a high frequency compared to the first switching signal PWM1 may improve the occurrence of a voltage drop phenomenon in the vertical blank period Tb. Referring to Figs. 5 and 6, this will be described as follows.

5 is a diagram illustrating a change in output voltage in a state in which the frequency of the switching signal is not changed, for example, in the process of controlling the boost circuit using the first switching signal PWM1 having the first switching frequency fs1. .

The voltage output through the output terminal Nout of the power module 200 shown in FIG. 4 is provided to the gamma reference voltage generator circuit shown in FIG. 3. The gamma reference voltage generation circuit generates a gamma reference voltage gamma by using the output voltage Vout as a high potential voltage. The gamma reference voltage gamma becomes a reference voltage that generates a data voltage output from the data line DL.

The data line DL outputs the data voltage during the image display period Tdp, and does not output the data voltage during the vertical blank period Tb. Accordingly, the power consumption rapidly increases when the vertical blank period Tb is changed to the image display period Tdp. When the power consumption increases rapidly, the amount of charge stored in the capacitor C of the boost circuit 211 is rapidly reduced. Since the amount of charge stored in the capacitor C and the output voltage Vout are in a proportional relationship, as the amount of charge stored in the capacitor C decreases, the output voltage Vout decreases, resulting in a voltage drop phenomenon (Vdrop).

As a result, when the vertical blank period is changed to the image display period, the output voltage Vout rapidly decreases. Since the output voltage Vout is used as a reference voltage of the data voltage, the data voltage is also distorted in a section in which the output voltage Vout changes rapidly. Eventually, the voltage drop phenomenon causes the image display quality to deteriorate.

6 is a diagram showing a method of varying a switching frequency according to the present invention. In FIG. 6, the first switching frequency fs1 indicates the switching frequency of the first switching signal PWM1, and the second switching frequency fs2 indicates the switching frequency of the second switching signal PWM2. That is, the display device of the present invention increases the switching frequency in order to mitigate a decrease in the output voltage Vout at the moment when the vertical blank period Tb is changed to the image display period Tdp.

When the switching frequency of the switch element SW1 increases, the amount of current supplied from the boost inductor L to the capacitor C increases. Since the amount of charge charged in the capacitor C is proportional to the amount of change in the amount of current, the amount of charge charged in the capacitor C increases as the amount of current provided to the capacitor C increases.

That is, when the second switching frequency fs2 having a higher frequency compared to the first switching frequency fs1 is used, the amount of charge charged in the capacitor C increases. Therefore, even if the discharge of charges to the output terminal Nout through the capacitor C increases rapidly, the amount of charge in the capacitor C does not decrease rapidly. As a result, when the switch element SW1 is controlled using the second switching frequency fs2 having a high switching frequency, the output voltage Vout decreases due to a decrease in the amount of charge stored in the capacitor C. This is improved.

The frequency variable section Tfc using the second switching frequency fs2 will be described as follows. As described above, the voltage drop phenomenon Vdrop occurs when the vertical blank period Tb is changed to the image display period Tdp. Therefore, the frequency variable period Tfc starts before the vertical blank period Tb ends. The period in which the vertical synchronization signal Vsync is output is included in the vertical blank period Tb. Based on this, the timing controller 300 sets a time point at which the vertical synchronization signal Vsync is outputted after the first predetermined time Δ1 as the start of the frequency variable section Tfc. If the first predetermined time Δ1 is too long, the starting point of the frequency variable section Tfc may be after the vertical blank section Tb has elapsed. Therefore, the first predetermined time Δ1 is the vertical synchronization signal ( Vsync) is set shorter than the period corresponding to the pulse width.

In addition, the frequency variable section Tfc must be maintained until the voltage drop phenomenon Vdrop ends. The voltage drop phenomenon Vdrop occurs at the start of the image display period Tdp and is maintained for a certain time. That is, the frequency variable period Tfc is maintained until the second predetermined time Δ2 elapses after the vertical blank period Tb ends. Accordingly, the second predetermined time Δ2 is set to a range including a period in which the voltage drop phenomenon can occur.

It will be appreciated by those skilled in the art through the above description that various changes and modifications can be made without departing from the technical idea of the present invention. Accordingly, the technical scope of the present invention should not be limited to the content described in the detailed description of the specification, but should be determined by the claims.

Claims (5)

A display panel on which data lines are arranged;
A data driver providing a data voltage to the data line;
A boost converter including a switch element and outputting a reference voltage for setting the data voltage as an output voltage according to a turn-on and turn-off ratio of the switch element;
A PWM control unit for varying the frequency of the switch element; And
A timing controller configured to set a section changed from a vertical blank period to an image display period as a frequency variable section, and control the PWM control section to increase a switching frequency of the switch element during the frequency variable section,
The data driver,
Outputting the data voltage to the data line during the image display period and not outputting the data voltage to the data line during the vertical blank period,
The frequency variable section,
The display device, wherein a vertical synchronization signal is output within the vertical blank period and a first predetermined time has elapsed from a time point when the vertical blank period is ended and a second predetermined time has elapsed from the start of the image display period.
delete The method of claim 1,
The timing controller sets the first predetermined time to be shorter than a period corresponding to a pulse width of the vertical synchronization signal.
The method of claim 1,
The timing controller provides a control signal to the PWM control unit during the frequency variable period,
The PWM control unit sets the frequency of the switching frequency high in response to the control signal.
The method of claim 1,
The boost converter is
An inductor disposed between an input terminal and a node to which the switch element is connected;
A rectifier diode connected in series with the inductor; And
A display device including a capacitor for smoothing an output voltage between the diode and the output terminal.

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