KR102460262B1 - Display device and driving method thereof - Google Patents

Abstract

The present invention relates to a liquid crystal display device and a driving method thereof, comprising: a lower substrate including a plurality of pixels; A thin film transistor, a pixel electrode connected to the thin film transistor, and a dummy positioned to correspond to the gate line with respect to the pixel electrode and forming a compensation capacitor (Cco) for minimizing ΔVp of a data voltage transmitted through the data line It is characterized in that it includes a voltage supply line.

Description

Display device and its driving method

The present invention relates to a liquid crystal display device, and to an array substrate for a liquid crystal display device capable of improving storage capacitor capacity and a method for manufacturing the same.

Recently, as the information society develops, the demand for the display field is also increasing in various forms. A liquid crystal display device, a plasma display panel device, an electroluminescent display device, and the like are being studied.

Among them, a liquid crystal display (hereinafter referred to as "LCD") is one of the most widely used flat panel displays, and comprises two substrates on which a pixel electrode and a common electrode are formed, and a liquid crystal layer between the two substrates. include

A liquid crystal display displays an image by using the optical anisotropy and polarization properties of liquid crystal. The liquid crystal has a directionality in the arrangement of molecules because the structure is thin and long, and the direction of the arrangement of molecules can be controlled by artificially applying an electric field to the liquid crystal. Therefore, if the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and image information can be expressed by changing the polarization state of light in the molecular arrangement direction of the liquid crystal by optical anisotropy.

In addition, the liquid crystal display is advantageous for displaying moving images and has a high contrast ratio, replacing the existing cathode ray tube, and not only display devices of mobile terminals (notebook monitors, etc.) but also computer monitors, televisions, etc. is being used in various ways.

The liquid crystal display device is attracting attention as a next-generation high-tech display device with low power consumption, good portability, and technology-intensive, high added value. Among these liquid crystal displays, an active matrix liquid crystal display equipped with a thin film transistor, which is a switching element that can control the on and off of voltage for each pixel, has excellent resolution and video realization ability, and thus attracts the most attention. are receiving The liquid crystal display uses a storage capacitor to improve characteristics of a sustain voltage applied to the liquid crystal and to stabilize gray scale display. The storage capacitor is a 'storage on gate' method in which a portion of the n-1th gate line is used as a lower electrode of the capacitor of the nth pixel, and a 'storage on gate' method in which a lower electrode of the capacitor is separately formed and connected to the common electrode. It is classified as 'storage on common'. In particular, when the thin film transistor is turned off, the voltage of the pixel Vp charged in each pixel drops by a specific amount, and this voltage is referred to as ΔVp. Recently, various types of storage capacitors have been formed to minimize ΔVp.

In general, a liquid crystal display device forms an array substrate and a color filter substrate through an array substrate manufacturing process of forming a thin film transistor and a pixel electrode, and a color filter substrate manufacturing process of forming a color filter and a common electrode, respectively, and between the two substrates. It is completed through a liquid crystal cell process with a liquid crystal interposed therebetween.

The liquid crystal display displays an image by adjusting the light transmittance of liquid crystal cells according to a video signal. Among the liquid crystal display devices, an active matrix type in which a switching element is provided for each liquid crystal cell is suitable for displaying a moving picture. In an active matrix type liquid crystal display device, a thin film transistor (hereinafter, referred to as "TFT") is mainly used as a switching element.

1 is a diagram schematically showing an equivalent circuit of a pixel region of a general liquid crystal display device, and FIGS. 2A and 2B are reference views to explain a difference in ΔVp according to the polarity of a conventional data voltage.

FIG. 2A shows ΔVp when the data voltage has a positive polarity (+), and FIG. 2B shows ΔVp when the data voltage has a negative polarity (-). It will be described with reference to FIG. 1 .

As shown in FIG. 1 , a gate line GL and a data line DL that cross each other and define a pixel area PA are formed in the liquid crystal display.

In addition, in each pixel area PA, a thin film transistor T connected to the gate line GL and data line DL, a liquid crystal capacitor Clc connected to the thin film transistor T, a storage capacitor Cst, and a thin film A gate source capacitor Cgs, which is a parasitic capacitor of the transistor T, is formed.

Specifically, one end of the liquid crystal capacitor Clc and the storage capacitor Cst is connected to the source electrode of the thin film transistor T, and the other end is connected to a common wiring (not shown).

In addition, the gate source capacitor Cgs is formed between the source electrode of the thin film transistor T and the gate wiring GL.

The liquid crystal capacitor Clc includes a common electrode (not shown) facing each other with a liquid crystal interposed therebetween and a pixel electrode (not shown) connected to the thin film transistor T.

As described above, the arrangement state of the liquid crystal is changed according to the data signal charged to the pixel electrode through the thin film transistor T, and the light transmittance is adjusted to realize grayscale.

The storage capacitor Cst serves to maintain the data signal charged in the liquid crystal capacitor Clc until the next frame.

On/off of the thin film transistor T is controlled by a gate signal transmitted through the gate line GL.

When the gate high voltage Vgh is supplied through the gate wiring GL, the thin film transistor T is turned on, and when the gate low voltage Vgl is supplied, the thin film transistor T is is turned off (Turn-Off).

In addition, the data voltage Vd is supplied to the liquid crystal capacitor Clc through the data line DL while the thin film transistor T is turned on.

However, at the moment when the thin film transistor T is turned off, the data voltage Vd supplied to the liquid crystal capacitor Clc drops by ΔVp due to the parasitic capacitor characteristics.

Here, ΔVp is referred to as a kick-back voltage or a feed through voltage, and may be expressed as Equation (1).

[Equation 1]

In this case, ΔVgs represents the amount of change in the gate source voltage (Vgs) corresponding to the voltage difference between the gate voltage (Vg) and the data voltage (Vd), and Cgs is formed between the gate electrode and the drain electrode of the thin film transistor (T). Represents a parasitic capacitor.

It can be seen that such ΔVp is proportional to ΔVgs through Equation (1).

In other words, ΔVp is proportional to ΔVgs, which is the amount of change in the gate source voltage Vgs. Since the gate voltage Vg is supplied at the same voltage level, ΔVp is changed by the data voltage Vd as a result.

Referring to FIGS. 2A and 2B , it can be seen that ΔVp is greater when the data voltage Vd has a positive polarity (+) than when the data voltage Vd has a negative polarity (-).

To explain this in detail, at the moment when the thin film transistor T is turned off, the data voltage Vd drops by ΔVp due to the parasitic capacitor characteristics, and at the same time, the charge increases in the direction of decreasing the magnitude of ΔVp. will move

However, the higher the data voltage Vd, the shorter the period in which Vgs>threshold voltage Vth is, so the charge movement time is shortened, and the decrease in the magnitude of ΔVp is relatively reduced. (t1<t2)

Therefore, ΔVp when the data voltage Vd is positive (+) is greater than ΔVp when the data voltage Vd is negative (-), and as a result, ΔVp varies depending on the data voltage Vd. occurred.

In addition, there is a problem in that the driving voltage of the liquid crystal display is lowered by ΔVp.

In addition, since the distribution of ΔVp varies for each panel position, an in-plane deviation of ΔVp may occur, and this in-plane deviation of ΔVp causes image quality deterioration such as flicker.

In general, the liquid crystal display increases the capacitance of the storage capacitor Cst in order to improve the flicker phenomenon. In order to increase the capacitance of the storage capacitor Cst, the area of the capacitor electrode needs to be increased. In other words, in the storage-on-gate liquid crystal display device, the width of the gate line GL must be widened in order to increase the capacitance of the storage capacitor Cst.

However, when the width of the gate wiring GL is widened, the aperture ratio is decreased and the line delay effect of the gate signal is increased, so there is a limit to widening the width of the gate wiring GL.

In addition, in the storage-on-common type liquid crystal display device, the storage capacitor Cst is formed in the center of the pixel cell, so that the aperture ratio of the storage-on-gate type liquid crystal display device is lower than that of the storage-on-gate type liquid crystal display device.

Accordingly, the inventors of the present invention have invented a new structure and method of a liquid crystal display for compensating for the deviation of ΔVp.

The present invention is to solve the above-described problem, and corresponds to the gate line GL based on the pixel electrode, and a compensation capacitor Cco for minimizing ΔVp of the data voltage Vd transmitted through the data line DL. An array substrate including a dummy voltage supply line (Dummy-VSL) forming

In addition to the technical problems of the present invention mentioned above, other features and advantages of the present invention will be described below, or will be clearly understood by those skilled in the art from such description and description.

A display device according to an embodiment of the present invention includes: a lower substrate including a plurality of pixels; a gate line and a data line positioned on the lower substrate and crossing each other to define a pixel area; a thin film transistor formed in the pixel region; a pixel electrode connected to the thin film transistor; and a dummy voltage supply line positioned to correspond to the gate wiring with respect to the pixel electrode, and a dummy voltage supply line for forming a compensation capacitor Cco for minimizing ΔVp of a data voltage transmitted through the data wiring. characterized.

A liquid crystal display device according to an embodiment of the present invention includes a substrate on which a plurality of gate wirings and a plurality of data lines intersecting each other to define a plurality of pixel regions and a plurality of data wirings are formed, a gate electrode branched from the gate wiring in the pixel region, and the a thin film transistor including source and drain electrodes branched from the data line and a gate insulating layer formed on the gate line; a pixel electrode connected to the thin film transistor; and a dummy voltage supply line formed on the same layer to be spaced apart from the gate wiring, wherein the pixel electrode and the dummy voltage supply line form a compensation capacitor.

A compensation capacitor Cco corresponding to the gate line GL based on the pixel electrode according to an embodiment of the present invention is formed to minimize ΔVp of the data voltage Vd transmitted through the data line DL. There is an effect of providing an array substrate having a dummy voltage supply line (Dummy-VSL) and a liquid crystal display using the same.

1 is an exemplary diagram schematically showing an equivalent circuit of a pixel region of a conventional liquid crystal display device.
FIG. 2A is an exemplary diagram illustrating a difference in ΔVp when a conventional data voltage has a positive polarity (+); FIG.
FIG. 2B is an exemplary diagram illustrating a difference in ΔVp when a conventional data voltage is negative (-); FIG.
3 is a block diagram schematically showing a liquid crystal display device according to an embodiment of the present invention.
4A is an exemplary diagram schematically illustrating an equivalent circuit of a pixel region of a liquid crystal display according to an embodiment of the present invention;
4B is an exemplary view showing that ΔVp is compensated when the data voltage is positive (+) in the liquid crystal display according to the embodiment of the present invention.
5 is a block diagram schematically showing the GIP type gate driving circuit shown in FIG.
6 is a plan view schematically illustrating an array substrate for a liquid crystal display shown in FIG. 3 .

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings, focusing on the liquid crystal display.

Like reference numerals refer to substantially identical elements throughout. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted. Names of components used in the following description are selected in consideration of ease of writing the specification, and may be different from the names of actual products.

The display device according to an embodiment of the present invention may include any display device that sequentially supplies gate pulses (or scan pulses) to gate lines (or scan lines) to write digital video data to pixels through line sequential scanning. have. For example, the display device according to the embodiment of the present invention includes a liquid crystal display (LCD), an organic light emitting diode display (OLED), and a field emission display (FED). , may be implemented as any one of an electrophoresis display (EPD). Although the present invention has been mainly exemplified in the following embodiment in which the display device is implemented as a liquid crystal display device, it should be noted that the display device of the present invention is not limited to the liquid crystal display device. The liquid crystal display may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, and a reflective liquid crystal display.

3 is a block diagram schematically showing a liquid crystal display according to a preferred embodiment of the present invention, and FIGS. 4A and 4B are a diagram schematically showing an equivalent circuit of a pixel region of the liquid crystal display according to the present invention and a liquid crystal display It is an exemplary diagram showing that ΔVp is compensated when the data voltage is positive (+) in the device.

Referring to FIG. 3 , in the liquid crystal display 100 according to the present invention, the liquid crystal panel 110 , the data driver 120 , the level shifter 150 , the shift register 130 , and timing for controlling the respective driving timings The controller 140 may be included.

In the display panel 100 , a liquid crystal layer is formed between two substrates. On the lower substrate of the liquid crystal panel 110 , data lines DL, gate lines GL crossing the data lines, thin film transistors T formed at intersections of data lines and gate lines, and thin film transistors T ) to form a TFT array including liquid crystal cells driven by an electric field between the pixel electrode and a common electrode (not shown), and a storage capacitor (Cst). A color filter array including a black matrix and a color filter is formed on the upper substrate of the liquid crystal panel 110 .

The liquid crystal display according to an embodiment of the present invention may be implemented in a liquid crystal mode such as a twisted nematic (TN) mode, a vertical alignment (VA) mode, an in plane switching (IPS) mode, and a fringe field switching (FFS) mode. The common electrode may be formed on the upper substrate in vertical electric field driving methods such as TN mode and VA mode, and may be formed on the lower substrate together with pixel electrodes in horizontal electric field driving methods such as IPS mode and FFS mode. Polarizing plates having optical axes orthogonal to each other are attached to the upper and lower substrates of the liquid crystal panel 110 , and an alignment layer for setting a pre-tilt angle of the liquid crystal is formed at an interface in contact with the liquid crystal layer.

The data driver 120 receives digital video data RGB from the timing controller 140 . The data driver 120 converts the digital video data RGB into a gamma compensation voltage in response to the source timing control signal DCS from the timing controller 140 to generate a data voltage, and applies the data voltage to the gate pulse. It is supplied to the data lines of the liquid crystal panel 110 to be synchronized. The data driver 120 may be connected to the data lines DL of the liquid crystal panel 110 by a chip on glass (COG) process or a tape automated bonding (TAB) process.

The GIP type gate driving circuit includes a level shifter 150 mounted on a printed circuit board (PCB) 160 and a shift register 130 formed on a lower substrate of the liquid crystal panel 110 .

A timing controller 140 , a level shifter 150 , and a voltage generator (not shown) are mounted on the PCB 160 .

The timing control unit 140 includes a plurality of image signals, a vertical synchronization signal (VSY), a horizontal synchronization signal (HSY), and a data enable signal (DE) from a system such as a graphic card through a low voltage differential signal (LVDS) interface. ) can receive a number of control signals such as

In addition, the timing controller 140 uses a plurality of control signals received from a system such as a graphic card to control the operation timing of the GIP-type gate driving circuit and the source driver 120 , a plurality of gate control signals, a plurality of Each data control signal can be generated and supplied to the corresponding driver.

For example, the timing controller 140 generates a plurality of data control signals such as a source start pulse (SSP), a source shift clock (SSC), a source output enable (SOE), etc. It can be supplied with one driver IC.

In addition, the timing controller 140 supplies the image signal RGB together with the plurality of data control signals to the data driver 120 so that the data driver 120 uses the image signal RGB and the plurality of data control signals to generate data. A signal may be generated and the generated data signal may be controlled to be supplied to a plurality of data lines DL of the liquid crystal panel 110 .

The data driver 120 may include at least one driver IC that supplies a data signal to the liquid crystal panel 110 .

The data driver 120 generates a data signal using a plurality of data control signals and image signals received from the timing controller 140 , and transmits the generated data signal to the liquid crystal panel 110 through a plurality of data lines DL. supplied with

The shift register 130 constituting the GIP-type gate driving circuit generates a gate signal using a plurality of gate control signals received from the timing controller 140 , and applies the generated gate signal to a plurality of gate lines GL. It can be supplied to the liquid crystal panel 110 through the.

The shift register 130 according to the present invention transmits a ΔVp compensation signal opposite in phase to a gate signal for turning on the thin film transistor T connected to the gate line GL to a dummy voltage supply line (Dummy). -VSL). To this end, the shift register 130 may include an inverter unit. The shift register 130 will be described in detail later with reference to FIG. 5 .

The liquid crystal panel 110 may include a plurality of pixel areas PA in which a plurality of gate lines GL and a plurality of data lines DL intersect each other. In addition, the liquid crystal panel 110 is positioned to correspond to the plurality of gate wires GL with respect to the pixel electrode, and includes a plurality of dummy voltage supply lines dummy-VSL formed of the same material as the plurality of gate wires GL. can do.

4A and 4B, in each pixel area PA, a thin film transistor T connected to the gate line GL and data line DL, a liquid crystal capacitor Clc connected to the thin film transistor T, A storage capacitor Cst, a gate source capacitor Cgs, a dummy voltage supply line Dumy-VSL, and a compensation capacitor Cco connected to the pixel electrode P may be formed.

Specifically, one end of the liquid crystal capacitor Clc and the storage capacitor Cst is connected to the source electrode S of the thin film transistor T, and the other end thereof is connected to a common wiring (not shown).

In addition, one end of the gate source capacitor Cgs is formed between the source electrode S of the thin film transistor T and the gate line GL.

And, one end of the compensation capacitor Cco is connected to the dummy voltage supply line Dumy-VSL, and the other end thereof is connected to the pixel electrode P.

The on/off of the thin film transistor T is controlled by a gate signal through the gate line GL.

For example, when the gate high voltage VGH is supplied through the gate wiring GL, the thin film transistor T is turned on, and when the gate low voltage VGL is supplied, the thin film transistor T is supplied. The transistor T is turned off.

At this time, the thin film transistor (T) is turned on (Turn-On) when the threshold voltage or more.

In addition, a data signal is supplied to the liquid crystal capacitor Clc through the data line DL while the thin film transistor T is turned on.

At this time, the liquid crystal capacitor Clc includes a common electrode (not shown) facing each other with a liquid crystal interposed therebetween and a pixel electrode P connected to the thin film transistor T.

As described above, the arrangement state of the liquid crystal is changed according to the data signal charged to the pixel electrode P through the thin film transistor T, and the light transmittance is adjusted to realize grayscale.

In addition, the storage capacitor Cst serves to maintain the data signal charged in the liquid crystal capacitor Clc until the next frame.

The gate source capacitor Cgs refers to a parasitic capacitor formed between the gate electrode G and the drain electrode D of the thin film transistor T.

The gate source voltage Vgs corresponding to the difference between the gate voltage and the data voltage may be stored in the gate source capacitor Cgs.

Meanwhile, the compensation capacitor Cco according to the present invention may be formed between the pixel electrode P connected to the thin film transistor T and the dummy voltage supply line Dumy-VSL.

The compensation capacitor Cco receives a ΔVp compensation signal opposite in phase to the gate signal through the dummy voltage supply line Dumy-VSL while the gate voltage is applied to the thin film transistor T through the gate line GL. ΔVp can serve as a compensation to minimize the voltage drop.

On the other hand, as the data voltage Vd increases, the period Vgs>Vth becomes shorter, so the charge movement time becomes shorter, and the decrease in the magnitude of the ΔVp voltage drop is relatively reduced.

In other words, since Vgs applied to the thin film transistor T is different according to the data voltage at the point in time when the ΔVp voltage drop occurs, the ΔVp voltage drop varies according to the data voltage. However, the data voltage Vd is constantly supplied to the liquid crystal display.

Referring to FIG. 4B , the liquid crystal display device according to the present invention can check the pixel voltage Vp for which the voltage drop by VP that occurs at the moment when the thin film transistor T is turned off is compensated. have.

When the gate high voltage VGH is supplied to the gate line GL, the data voltage Vd supplied through the data line DL is charged to the pixel voltage Vp at the pixel electrode P. In addition, the gate low voltage VGL is supplied to the dummy voltage supply line Dumy-VSL.

When the gate low voltage VGL is continuously supplied to the gate line GL, the pixel voltage Vp charged in the pixel electrode P is affected by the voltage Vp as shown in FIG. 4B and drops by Vp. is generated That is, when the gate low voltage VGL transitions from the gate high voltage VGH, the pixel voltage Vp from which the Vp voltage has dropped is charged in the pixel electrode P. Also, when the gate low voltage VGL is supplied to the gate line GL, the gate high voltage VGH is supplied to the dummy voltage supply line Dumy-VSL. Accordingly, a Vp compensation signal having a phase opposite to that of the gate signal supplied to the gate line GL is supplied to each pixel area PA through the dummy voltage supply line Dumy-VSL. As a result, the pixel electrode P and the dummy voltage supply line Dumy-VSL connected to the thin film transistor T can form a compensation capacitor Cco, so that the voltage drop of the pixel voltage Vp is compensated for by Vp. The pixel electrode P may be charged.

As a result, in the liquid crystal display according to the present invention, the ΔVp voltage drop that may occur at the moment when the thin film transistor T is turned off is the dummy voltage supply line Dumy-VSL while the gate voltage is applied. A voltage is supplied to the compensation capacitor Cco as much as the ΔVp compensation signal that is out of phase with the gate signal through the gate signal and connected to the thin film transistor T by the compensation capacitor Cco while the gate voltage is applied through the gate wiring GL. A charge can be charged to the pixel electrode P, which can prevent a voltage drop as much as ΔVp.

The compensation capacitor Cco according to the present invention may be, for example, a capacitor having a size equivalent to or similar to that of the gate source capacitor Cgs.

5 is a block diagram schematically showing the shift register 130 of the gate driving circuit according to the present invention. The shift register 130 includes a plurality of stages ST1 to STn. The plurality of stages ST1 to STn outputs a gate signal Vg according to the input gate start signal VST and clock signals CLKs, and the output gate signal Vg is sequentially connected to a plurality of gate wirings ( GL) may be supplied to the liquid crystal panel 110 .

The inverter unit receives the gate signal Vg output from each stage ST as an input and generates a ΔVp compensation signal VInv out of phase with the gate signal Vg at each stage ST as the gate signal Vg. is outputted to the dummy voltage supply line Dummy-VSL while is outputted to the gate line GL.

As a result, the ΔVp voltage drop that may occur at the moment when the thin film transistor T is turned off is reduced by the gate signal Vg through the dummy voltage supply line Dumy-VSL while the gate signal Vg is applied. ) and a voltage equal to the ΔVp compensation signal VInv opposite in phase is supplied to the compensation capacitor Cco. Then, while the gate voltage is applied through the gate line GL, charges can be charged to the pixel electrode P connected to the thin film transistor T by the compensation capacitor Cco, thereby preventing a voltage drop by ΔVp. can do.

6 is a plan view schematically showing an array substrate for a liquid crystal display according to the present invention shown in FIG. 3 .

Referring to FIG. 6 , a gate line 210 is formed in a horizontal direction on the substrate, and a data line 220 is formed crossing the gate line 210 to form a pixel region ( PA) is being defined. In addition, a thin film transistor (TFT) is formed at the intersection of the gate line 210 and the data line 220 . The thin film transistor (TFT) includes a gate electrode 211 integrally formed with the gate line 210, an active layer (not shown), and a source electrode (not shown) made of the same material as the data line 220 and spaced apart from each other by a predetermined distance. 222) and a drain electrode 221 . The source electrode 222 is electrically connected to the pixel electrode 230 through the drain contact hole 231 .

A storage capacitor 241 positioned at the center of the pixel area PA is provided. The storage capacitor 241 is for stably maintaining the pixel voltage Vp after the data signal is applied to the pixel electrode 230 through the source electrode 222 when the gate signal is applied to the thin film transistor TFT. The capacity value must be large enough. To this end, the storage capacitor 241 is formed by the pixel electrode 230 and the capacitor electrode 240 electrically connected to the source electrode 222 . The capacitor electrode 240 is located on the upper substrate of the liquid crystal panel and may serve as a common electrode opposite to the pixel electrode 230 .

Also, a dummy voltage supply line 250 is positioned to correspond to the gate line 210 in the pixel area PA. The dummy voltage supply line 250 made of the same material as the gate line 210 is arranged parallel to the gate line 210 .

In addition, one surface of the pixel electrode 230 has a protruding portion so that a portion overlaps with the dummy voltage supply line 250 .

The dummy voltage supply line 250 may be a first compensation capacitor electrode having a predetermined width W, and the protruding portion of the pixel electrode 230 is a second compensation capacitor overlapping the first compensation storage electrode 20 . It can be an electrode. The size of the compensation capacitor 242 may be determined according to a predetermined width W of the dummy voltage supply line 250 and an overlapping area of the protruding portion of the pixel electrode 230 . Accordingly, the dummy voltage supply line 250 overlaps the pixel electrode 230 to form the compensation capacitor 242 .

The pixel electrode 230 maintains the data voltage Vd supplied from the data line 220 through the storage capacitor 241 for one frame. That is, when the gate high voltage VGH is supplied to the gate line 210 , the data voltage Vd supplied through the data line 220 is charged to the pixel voltage Vp at the pixel electrode 230 .

When the gate low voltage VGL is continuously supplied to the gate line 210 , the pixel voltage Vp charged in the pixel electrode 230 has a voltage drop of ⅿVp. That is, when the gate low voltage VGL is transitioned from the gate high voltage VGH to the gate low voltage VGL, the pixel voltage Vp, which is increased in voltage by ⅿVp, may be charged in the pixel electrode 230 , but the compensation capacitor 242 of the present invention ) compensates for the charging characteristic of the storage capacitor 241, so that the voltage increase does not occur by ⅿVp. As a result, the voltage enhancement by ⅿVp does not affect the charged pixel voltage Vp of the pixel electrode 230, and thus image quality deterioration such as flicker occurring on the screen can be improved.

Those skilled in the art to which the present invention pertains will understand that the present invention may be embodied in other specific forms without changing the technical spirit or essential characteristics thereof. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The scope of the present invention is indicated by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention. .

110: liquid crystal panel 140: timing control unit
120: data driver 130: shift register
131: inverter part 150: level shifter
210: gate line 211: gate electrode
220: data line 221: data electrode
222: source electrode 230: pixel electrode
231: contact hole 240: capacitor electrode
241: storage capacitor 242: compensation capacitor
250: dummy voltage supply line

Claims (18)

a lower substrate including a plurality of pixels;
a gate line and a data line positioned on the lower substrate and crossing each other to define a pixel area;
a thin film transistor formed in the pixel region;
a pixel electrode connected to the thin film transistor; and
and a dummy voltage supply line positioned to correspond to the gate wiring with respect to the pixel electrode,
A compensation capacitor Cco is formed between the pixel electrode and the dummy voltage supply line,
The dummy voltage supply line transmits, to the compensation capacitor (Cco), a ΔVp compensation signal having a phase opposite to that of a gate signal transmitted to the gate line while a gate voltage is applied to the gate line. The method of claim 1,
and the dummy voltage supply line is formed in a direction parallel to the gate line. The method of claim 1,
The display device of claim 1, wherein the dummy voltage supply line is made of the same material as the gate line. The method of claim 1,
and the dummy voltage supply line is a first compensation capacitor electrode. The method of claim 1,
The display device according to claim 1, wherein the protruding portion of the pixel electrode is a second compensation capacitor electrode. The method of claim 1,
A portion of the pixel electrode protrudes to have an overlapping area with the dummy voltage supply line. 7. The method of claim 6,
and a compensation capacitor (Cco) is formed in the overlapping area. 8. The method of claim 7,
The compensation capacitor (Cco) minimizes a ΔVp voltage drop of the pixel voltage (Vp) charged in the pixel electrode. delete The method of claim 1,
and a gate driving circuit unit configured to supply the ΔVp compensation signal to the dummy voltage supply line. 11. The method of claim 10,
The gate driving circuit unit of the GIP (Gate In Panel) method includes a plurality of stages that receive i (i is a natural number equal to or greater than 2) phase clocks sequentially delayed in phase and sequentially output a gate signal to the gate wiring. Display as a feature. 12. The method of claim 11,
and each of the plurality of stages includes an inverter circuit for outputting the ΔVp compensation signal having a phase opposite to that of the gate signal to the dummy voltage supply line. a substrate on which a plurality of gate wirings and a plurality of data lines crossing each other defining a plurality of pixel regions are formed;
a thin film transistor including a gate electrode branched from the gate wire, source and drain electrodes branched from the data wire, and a gate insulating layer formed on the gate wire in the pixel region;
a pixel electrode connected to the thin film transistor; and
and a dummy voltage supply line spaced apart from the gate wiring and formed on the same layer, wherein the pixel electrode and the dummy voltage supply line form a compensation capacitor (Cco);
The dummy voltage supply line transmits, to the compensation capacitor (Cco), a ΔVp compensation signal having an opposite phase to a gate signal transmitted to the gate wiring while a gate voltage is applied to the gate wiring. 14. The method of claim 13,
and the pixel electrode partially overlaps the dummy voltage supply line. 15. The method of claim 14,
The liquid crystal display device, characterized in that the overlapping area of the pixel electrode determines the size of the compensation capacitor (Cco). 14. The method of claim 13,
and a gate source capacitor (Cgs) is formed between the gate electrode and the source electrode. 17. The method of claim 16,
A size of the compensation capacitor (Cco) is the same as that of the gate source capacitor (Cgs). 14. The method of claim 13,
and the gate insulating layer is a dielectric layer of the compensation capacitor (Cco).

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