KR20150002336A

KR20150002336A - Liquid crystal display device

Info

Publication number: KR20150002336A
Application number: KR20130076045A
Authority: KR
Inventors: 최혁
Original assignee: 엘지디스플레이 주식회사
Priority date: 2013-06-28
Filing date: 2013-06-28
Publication date: 2015-01-07
Also published as: KR102016566B1

Abstract

The present invention relates to a liquid crystal display device to improve readability. The liquid crystal display device according to the present invention includes first to third sub pixels which share one data line and are charged with a data voltage in response to gate pulses from a pair of gate lines. The pair of gate lines includes a pair of vertical gate lines and a pair of horizontal gate lines which are connected to the vertical gate lines. The pair of horizontal gate lines receive the gate pulse from the pair of vertical gate lines and turn on TFTs of the first to third sub pixels.

Description

[0001] LIQUID CRYSTAL DISPLAY DEVICE [0002]

The present invention relates to a liquid crystal display device.

The flat panel display includes a liquid crystal display (LCD), a plasma display panel (PDP), an organic light emitting display (OLED), and an electrophoretic display device EPD). A liquid crystal display device displays an image by controlling an electric field applied to liquid crystal molecules in accordance with a data voltage. The active matrix type liquid crystal display device is most widely used for almost all display devices ranging from small mobile devices to large-sized televisions due to its low price and high performance due to the development of process technology and driving technology.

In order to reduce the number of source drive ICs (Integrated Circuits) of a liquid crystal display device, a triple rate driving (TRD) technique is known in which a pixel array is applied as shown in FIGS. 1 and 2 and the data driving frequency is increased to 3 times.

Referring to FIGS. 1 and 2, the TRD technique divides one pixel into a red subpixel R, a green subpixel G and a blue subpixel B arranged along the vertical direction (y-axis direction). The red subpixel R, the green subpixel G and the blue subpixel B are connected to one data line Di. The TRD technique requires one data line Di and three gate lines Gj, Gj + 1, Gj + 2 to drive one pixel. A thin film transistor (TFT) is formed at the intersection of the data line Di and the gate lines Gj, Gj + 1 and Gj + 2. The TFT is turned on according to the gate pulse from the gate lines Gj, Gj + 1, and Gj + 2 to supply the data voltage on the data line Di to the pixel electrode.

A liquid crystal display having a general pixel structure supplies RGB data voltages to one pixel subpixels in one horizontal period through three data lines. On the other hand, the TRD technique sequentially supplies RGB data voltages to RGB subpixels through one data line Di as shown in FIG. For example, the R data voltage is supplied to the red subpixel R in the first 1/3 horizontal period. Subsequently, the G data voltage is supplied to the green subpixel G in the second 1/3 horizontal period, and then the B data voltage is supplied to the blue subpixel B in the third 1/3 horizontal period. Therefore, the TRD technique can reduce the number of data lines to 1/3 compared with a general pixel structure. However, in TRD technology, the number of gate lines is tripled and the data driving frequency is tripled.

The TRD technique has a disadvantage in that the area occupied by the gate lines increases and the aperture ratio of the pixels decreases.

The horizontal direction (x) length of the subpixels (R, G, B) of the TRD technique is longer than the vertical direction (y) length. Thus, the subpixels of the TRD technique have a long structure in the horizontal direction. The horizontal long sub-pixel structure has a problem that the legibility of text is lowered as shown in FIG.

FIG. 3 shows an experiment result in which "A" is displayed by applying a clear type to a liquid crystal display device to which the TRD technique is applied. 3 (a) is a pixel structure of the TRD technique, and FIG. 3 (b) is an example of displaying "A" as a clear type in a pixel array made up of pixels as shown in FIG. ClearType is Microsoft Windows font rendering technology. As can be seen in FIG. 3, the readability is poor in the clear type due to the structure of subpixels long in the horizontal direction (x).

Manufacturers of flat panel display devices have made various attempts to implement Narrow bezels. Narrow-bezel technology can reduce the amount of bezels that do not display images at the edges of the display panel, which can make the size of the effective screen displayed on the same size display panel relatively large. Generally, gate drive ICs are disposed at the left and right edges of the display panel. Therefore, in the left and right edges of the display panel, an area where the gate drive IC is bonded, a gate link area connecting the gate drive IC and the horizontal gate lines of the pixel array, etc. must be ensured. Due to the structural problems of such a flat panel display device, it is difficult to realize a narrow bezel.

The present invention provides a liquid crystal display device capable of increasing pixel aperture ratio and improving readability in TRD technology.

The liquid crystal display of the present invention includes first to third sub-pixels that share one data line and charge a data voltage in response to gate pulses from a pair of gate lines.

The pair of gate lines includes a pair of vertical gate lines and a pair of horizontal gate lines connected to the vertical gate lines.

The pair of horizontal gate lines receives gate pulses from the pair of vertical gate lines and turns on the TFTs of the first to third sub-pixels.

The present invention drives a plurality of subpixels divided by one pixel into one data line and a pair of gate lines, and realizes a subpixel in a vertically long structure. As a result, the present invention provides a liquid crystal display device capable of increasing the pixel aperture ratio and improving the readability by reducing the number of gate lines in the TRD technology.

1 is a cross-sectional view showing a pixel structure of a long TRD technique in a transverse direction.
2 is a waveform diagram showing a driving signal of the pixel shown in FIG.
FIG. 3 is a diagram illustrating an example of displaying characters on pixels having the structure shown in FIG. 1. Referring to FIG.
4 is a view illustrating a liquid crystal display device according to an embodiment of the present invention.
5 is a view showing a first embodiment of the display panel drive circuit shown in FIG.
FIG. 6 is an enlarged view of the COF shown in FIG. 5. FIG.
7 is a view showing a second embodiment of the display panel drive circuit shown in FIG.
8 is an equivalent circuit diagram showing a pixel structure according to an embodiment of the present invention.
9 is a waveform diagram showing a driving signal of the pixel shown in FIG.
10 is a diagram illustrating an example of displaying characters on pixels having the structure of FIG.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

The names of components used in the following description are selected in consideration of ease of specification, and may be different from actual product names.

4 to 7, the liquid crystal display device of the present invention includes a display panel PNL, a display panel driving circuit 10, a timing controller (TCON) 12, and the like.

The display panel PNL may be implemented by any known liquid crystal mode such as TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In Plane Switching) mode, FFS (Fringe Field Switching)

The display panel (PNL) includes an upper substrate and a lower substrate facing each other with a liquid crystal layer interposed therebetween. In the display panel (PNL), the image data is displayed in an array of mxn (m, n is a positive integer of 2 or more) pixel array in which pixels are arranged in a matrix form. The pixel array includes an array of thin film transistors (TFT) formed on the lower substrate and a color filter array formed on the upper substrate. The bezel (BZ) outside the pixel array is a non-display area.

The TFT array includes vertical wirings and horizontal wirings. The vertical wirings are formed along the vertical direction (y-axis direction) of the display panel PNL. The horizontal wirings are formed along the horizontal direction (x-axis direction) of the display panel PNL and perpendicular to the vertical wirings. The vertical wirings include vertical data lines (VD), vertical gate lines (VG), and vertical common lines (VC). Data voltages are supplied to the vertical data lines VD, and gate pulses synchronized with the data voltages are supplied to the vertical gate lines VG. A common voltage Vcom is supplied from a power supply circuit (not shown) to the vertical common lines VC.

The horizontal wirings include horizontal gate lines (HG) receiving gate pulses through the vertical gate lines (VG). The horizontal gate lines HG are connected to the vertical gate lines VG and are supplied with gate pulses through the vertical gate lines VG. The horizontal gate lines HG may be connected to the vertical gate lines VG in the bezel BZ on the left or right side of the display panel PNL or in the pixel array.

In the TFT array, TFTs are formed at the intersections of the vertical data lines VD and the horizontal gate lines HG as shown in Fig. The TFT supplies the data voltage from the vertical data line VD to the pixel electrode 1 of the liquid crystal cell Clc in response to the gate pulse from the horizontal gate line HG. Each of the liquid crystal cells Clc is driven by the voltage difference between the pixel electrode 1 for charging the data voltage through the TFT and the common electrode 2 to which the common voltage Vcom is applied. The common voltage Vcom is applied to the common electrode 2 of all the pixels through the vertical common lines VC. The common electrode 2 and the pixel electrode 1 are formed of a transparent electrode material such as ITO. The storage capacitor Cst is connected to the pixel electrode 1 of the liquid crystal cell Clc to maintain the voltage of the liquid crystal cell Clc for one frame period.

The color filter array includes a color filter and a black matrix. On each of the upper glass substrate and the lower glass substrate of the display panel (PNL), a polarizing plate is attached and an alignment film for setting a pre-tilt angle of the liquid crystal is formed.

The display panel drive circuit 10 writes the data input from the timing controller 12 to the pixels of the display panel. The display panel drive circuit 10 includes a source drive IC (SIC) for outputting a data voltage and a gate drive IC (GIC) for outputting a gate pulse.

The source drive IC (SIC) and the gate drive IC (GIC) may be mounted together on a flexible circuit board such as a chip on film (COF) as shown in FIG. The input terminal of the COF is connected to a PCB (Printed Circuit Board), and the output terminal of the COF is connected to the TFT array substrate of the display panel (PNL). In COF, between the wirings (FIG. 6, dotted line) connected to the source drive IC (SIC) and the wirings (FIG. 6, solid line) connected to the gate drive IC (GIC) . The source drive IC (SIC) and the gate drive IC (GIC) may be separately arranged on the upper and lower bezels of the display panel (PNL) as shown in FIG. The source drive IC (SIC) and the gate drive IC (GIC) can be directly bonded on the substrate of the display panel (PNL) by a COG (chip on glass) process. In this case, the source drive IC SIC can be bonded to the substrate in the lower bezel on the lower outside of the pixel array region PIXR as shown in Fig. The gate drive IC (GIC) may be bonded to the substrate within the upper bezel region disposed on the upper side of the pixel array region PIXR.

The source driver IC SIC latches the digital video data of the input image under the control of the timing controller 12 and converts it into data of a parallel data system. The source driver IC SIC generates a data voltage by converting the digital video data into an analog gamma compensation voltage using a digital-to-analog converter (ADC) under the control of the timing controller 12, And supplies them to the vertical data lines VD. The gate driver IC (GIC) sequentially supplies gate pulses (or scan pulses) synchronized with the data voltage from the first vertical gate line to the nth vertical gate line under the control of the timing controller 12. [

The source drive IC (SIC) and the gate drive IC (GIC) are disposed above or below the display panel (PNL). Therefore, the gate drive IC (GIC) does not need to be joined or embedded in the left and right bezel regions of the display panel PNL and the gate link line (GIC) connecting the horizontal gate lines HG and the gate drive IC . Therefore, since the junction region and the gate link region of the gate drive IC (GIC) are removed from the right side bezel BZ and the right side bezel BZ of the display panel PNL of the present invention, the width thereof is reduced. As a result, the liquid crystal display device of the present invention can realize a narrow bezel.

The timing controller 12 transmits the digital video data of the input image received from the host system 14 to the source drive ICs SIC. The timing controller 12 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE and a main clock CLK from the host system 14. These timing signals are synchronized with the digital video data of the input image. The timing controller 12 generates a timing control signal for controlling the operation timing of the source drive ICs SIC using the timing signals Vsync, Hsync, DE, and CLK and a timing control signal for controlling the operation timings of the gate drive ICs (GIC) Lt; RTI ID = 0.0 > timing control < / RTI >

The host system 14 may be implemented in any one of a television system, a set top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, have. The host system 14 converts the digital video data RGB of the input image into a format suitable for the display panel PNL. The host system 14 transmits timing signals (Vsync, Hsync, DE, MCLK) to the timing controller 12 together with the digital video data of the input video.

The pixel array may be formed with a pixel structure capable of TRD driving as shown in FIG. And can be implemented in various structures.

8 is an equivalent circuit diagram showing a pixel structure according to an embodiment of the present invention. 9 is a waveform diagram showing a driving signal of the pixel shown in FIG. 10 is a diagram illustrating an example of displaying characters on pixels having the structure of FIG.

8 and 9, the liquid crystal display of the present invention includes one data line Di and a pair of gate lines GPn and GPn + 1 for driving three color subpixels. The pair of gate lines GPn and GPn + 1 includes a pair of vertical gate lines VGj and VGj + 1 and a pair of horizontal gate lines VGj and VGj + 1 connected to the vertical gate lines VGj and VGj + (HGj, Hj + 1). Gate pulses as shown in FIG. 9 are supplied to the horizontal gate lines HGj and Hj + 1. The gate pulse swings between the gate high voltage and the gate low voltage.

The n-th (n is a positive integer) pixel is formed in the n-th horizontal line and the data voltages of the first to third colors are supplied from the i-th (i is a positive integer) data line Di in the n-th horizontal period . The (n + 1) th pixel is formed in the (n + 1) th horizontal line and the data voltages of the first to third colors are supplied from the i th data line Di in the (n + 1) th horizontal period.

Each of the n-th and (n + l) -th pixels is divided into sub-pixels of the first to third colors sharing the i-th data line. 8, the first color is red (R), the second color is green (G), and the third color is blue (B). However, the present invention is not limited thereto. One vertical gate line VGj among the pair of vertical gate lines VGj and VGj + 1 is vertically formed along the boundary between the subpixel of the first color and the second subpixel, and another vertical gate line VGj + 1) is formed vertically along the boundary between the subpixel of the second color and the third subpixel. The vertical data line Di is formed vertically along the boundary between the subpixel of the third color and the subpixel of the first color.

In the n-th pixel, the sub-pixel of the first color includes the first TFT (T1) and the first pixel electrode. The sub-pixel of the second color includes the second TFT (T2) and the second pixel electrode. The subpixel of the third color includes the third and fourth TFTs T3 and T4 and the third pixel electrode.

The first TFT T1 includes a drain electrode connected to the vertical data line Di, a source electrode connected to the first pixel electrode, and a gate electrode connected to the jth horizontal gate line HGj. The second TFT T2 includes a drain electrode connected to the vertical data line Di, a source electrode connected to the second pixel electrode, and a gate electrode connected to the (j + 1) th horizontal gate line HGj + 1. The third TFT T3 includes a drain electrode connected to the vertical data line Di, a source electrode connected to the drain electrode of the fourth TFT T4, and a gate electrode connected to the (j + 1) th horizontal gate line HGj + 1 do. The fourth TFT T4 includes a drain electrode connected to the source electrode of the third TFT T3, a source electrode connected to the third pixel electrode, and a gate electrode connected to the jth horizontal gate line HGj.

The first TFT T1 supplies a data voltage on the i-th data line Di to the first pixel electrode in response to a gate pulse from the j-th (j is a positive integer) horizontal gate line HGj. The second TFT T2 supplies the data voltage on the i-th data line Di to the first pixel electrode in response to the gate pulse from the (j + 1) -th horizontal gate line HGj. The third and fourth TFTs T3 and T4 are turned on when gate pulses are simultaneously supplied to the jth and (j + 1) th horizontal gate lines HGj and HGj + 1, And supplies the data voltage to the third pixel electrode.

In the (n + 1) th pixel, the subpixel of the first color includes the fifth TFT (T5) and the fourth pixel electrode. The subpixel of the second color includes a sixth TFT (T6) and a fifth pixel electrode. The subpixel of the third color includes seventh and eighth TFTs T7 and T8 and a sixth pixel electrode.

The fifth TFT T5 includes a drain electrode connected to the vertical data line Di, a source electrode connected to the fourth pixel electrode, and a gate electrode connected to the (j + 2) th horizontal gate line HGj + 2. The sixth TFT T6 includes a drain electrode connected to the vertical data line Di, a source electrode connected to the fifth pixel electrode, and a gate electrode connected to the (j + 3) th horizontal gate line HGj + 3. The seventh TFT T7 includes a drain electrode connected to the vertical data line Di, a source electrode connected to the drain electrode of the eighth TFT T8, and a gate electrode connected to the (j + 3) th horizontal gate line HGj + 3 do. The eighth TFT T8 includes a drain electrode connected to the source electrode of the seventh TFT T7, a source electrode connected to the sixth pixel electrode, and a gate electrode connected to the (j + 2) th horizontal gate line HGj + 2.

The fifth TFT T5 supplies the data voltage on the i-th data line Di to the fourth pixel electrode in response to the gate pulse from the (j + 2) -th horizontal gate line HGj + 2. The sixth TFT T6 supplies the data voltage on the ith data line Di to the fifth pixel electrode in response to the gate pulse from the (j + 3) th horizontal gate line HGj + 3. The seventh and eighth TFTs T7 and T8 are turned on when gate pulses are simultaneously supplied to the (j + 2) th and (j + 3) th horizontal gate lines HGj + 2 and HGj + 3, And supplies the data voltage on the data line Di to the sixth pixel electrode.

One horizontal period is divided into a first 1/3 horizontal period, a second 1/3 horizontal period, and a third 1/3 horizontal period. The j-th horizontal gate line HGj is supplied with the first gate pulse P1 in the first 1/3 horizontal period and then the second gate pulse P2 in the third 1/3 horizontal period. The (j + 1) th horizontal gate line HGj + 1 is supplied with the first 1/3 horizontal period and the second 1/3 horizontal period third gate pulse P3. The pulse width of the third gate pulse P3 is twice as large as that of each of the first and second gate pulses.

The third and fourth TFTs T3 and T4 are turned on simultaneously in response to the first and third gate pulses P1 and P3 in the first 1/3 horizontal period of the nth horizontal period, And supplies the data voltage of the third color to the third pixel electrode. Then, the second TFT (T2) is turned on in response to the third gate pulse (P3) during the second 1/3 horizontal period of the n-th horizontal period to supply the data voltage of the second color to the second pixel electrode . Then, the first TFT (T1) supplies the data voltage of the third color to the first pixel electrode in response to the first gate pulse (P1) in the first 1/3 horizontal period of the n-th horizontal period, And supplies the data voltage of the first color to the first pixel electrode in response to the second gate pulse P2 in the 1/3 horizontal period.

The seventh and eighth TFTs T7 and T8 are simultaneously turned on in response to the first and third gate pulses P1 and P3 in the first 1/3 horizontal period of the (n + 1) And supplies the data voltage of the color to the sixth pixel electrode. Then, the sixth TFT T6 is turned on in response to the third gate pulse P3 during the second 1/3 horizontal period of the (n + 1) -th horizontal period to apply the data voltage of the second color to the fifth pixel electrode Supply. Then, the fifth TFT T5 supplies the data voltage of the third color to the fourth pixel electrode in response to the first gate pulse P1 in the first 1/3 horizontal period of the (n + 1) -th horizontal period, And is turned on in response to the second gate pulse P2 in the third 1/3 horizontal period to supply the data voltage of the first color to the fourth pixel electrode.

In the pixel structure shown in Fig. 8, the vertical direction (x axis) length of the subpixel is longer than the horizontal direction (x axis) length. Thus, the subpixel has a long structure in the horizontal direction. Due to the sub-pixel structure long in the horizontal direction (x-axis), when text is displayed on a pixel array having the pixel structure as shown in Fig. 8, character readability is remarkably improved as shown in Fig. 10A shows a pixel structure having a long vertical direction, and FIG. 10B shows an example in which "A" is displayed as a clear type in a pixel array made up of pixels as shown in FIG.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

PNL: display panel 10: display panel drive circuit
12: timing controller 14: host system
T1 to T8: TFT

Claims

Pixels that share one data line and charge a data voltage in response to gate pulses from a pair of gate lines,
Wherein the pair of gate lines includes a pair of vertical gate lines and a pair of horizontal gate lines connected to the vertical gate lines,
Wherein the pair of horizontal gate lines receives gate pulses from the pair of vertical gate lines and turns on the TFTs of the first to third sub-pixels.

The method according to claim 1,
The pair of vertical gate lines includes first and second vertical gate lines,
Wherein the pair of horizontal gate lines includes a first horizontal gate line connected to the first vertical gate line and a second horizontal gate line connected to the second vertical gate line.

3. The method of claim 2,
A first gate electrode and a second gate electrode, the first gate electrode and the second gate electrode being connected to the first gate electrode and the second gate electrode, A first TFT for supplying a second data voltage from the vertical data line to the first pixel electrode in response to a pulse;
A first TFT for supplying a second data voltage from the vertical data line to a second pixel electrode in response to a second gate pulse input in the first period and the second period through the second horizontal gate line;
A third TFT that is turned on in response to the first gate pulse input in the first period through the first horizontal gate line; And
And a fourth TFT that is turned on in response to a third gate pulse input in the first period and the second period through the second horizontal gate line,
And the third and fourth TFTs are turned on when the first and third gate pulses are generated at the same time to supply the third data voltage from the vertical data line to the third pixel electrode. .

The method of claim 3,
Wherein the first TFT includes a drain electrode connected to the vertical data line, a source electrode connected to the first pixel electrode, and a gate electrode connected to the first horizontal gate line,
The second TFT includes a drain electrode connected to the vertical data line, a source electrode connected to the second pixel electrode, and a gate electrode connected to the second horizontal gate line,
The third TFT includes a drain electrode connected to the vertical data line, a source electrode connected to a drain electrode of the fourth TFT, and a gate electrode connected to the second horizontal gate line,
Wherein the fourth TFT includes a drain electrode connected to a source electrode of the third TFT, a source electrode connected to the third pixel electrode, and a gate electrode connected to the first horizontal gate line.