KR20120119411A - Liquid crystal display - Google Patents

Abstract

PURPOSE: A liquid crystal display device is provided to reduce the number of source drive ICs necessary for operating a data line of a liquid crystal display panel, thereby enabling a user to easily read characters. CONSTITUTION: A liquid crystal display panel(100) includes data lines of a column direction, gate lines of a line direction, and pixels. The pixels are formed by the data lines and the gate lines in a matrix shape. A data operating circuit(102) supplies a data voltage to the data lines. The data voltage is for reading data in the pixels. A gate operating circuit(103) successively supplies gate pulses to the gate lines. [Reference numerals] (AA) Data line; (BB) Gate line

Description

Liquid Crystal Display {LIQUID CRYSTAL DISPLAY}

The present invention relates to a liquid crystal display device.

A liquid crystal display device of an active matrix driving type displays a moving picture by using a thin film transistor (hereinafter referred to as "TFT") as a switching element. This liquid crystal display device can be downsized as compared with a cathode ray tube (CRT), and is applied to a display device in a portable information device, an office machine, a computer, etc., and is also applied to a television, thereby quickly replacing a cathode ray tube.

Due to the development of the driving method and manufacturing process of the liquid crystal display, the manufacturing cost and the image quality are greatly improved. Recently, compared to a liquid crystal display device in which a general pixel arrangement is applied, a triple rate driving (TRD) in which the number of source drive integrated circuits (TRD) is reduced to 1/3 by applying the pixel arrangement of the liquid crystal display device to the pixel arrangement as shown in FIG. 1. Technology has been proposed.

Referring to FIG. 1, one pixel of a TRD LCD includes a red subpixel R, a green subpixel G, and a blue subpixel B arranged side by side in a column direction (y-axis direction). . The red subpixels R of the pixels are arranged side by side along the line direction (x-axis direction) in the 3N (N is a positive integer) + first line (LINE # 1, LINE # 4). The green subpixels G of the pixels are arranged side by side along the line direction in the 3N + 2th lines LINE # 2 and LINE # 5. The blue subpixels B of the pixels are arranged side by side along the line direction in the 3N + 3th lines LINE # 3 and LINE # 6.

In the conventional TRD liquid crystal display as shown in FIG. 1, the line direction length of the subpixel is longer than the column direction length. Thus, the subpixel has a long structure in the line direction. Due to the long sub-pixel structure in the line direction, displaying small text on an existing TRD liquid crystal display has a problem in that character readability of the text is lowered.

FIG. 2 shows an experimental result of displaying "A" and "Sub-pixel" by applying a clear type to an existing TRD liquid crystal display. Clear type is Microsoft's Windows font rendering technology. As can be seen in FIG. 2, due to the structure of the subpixels long in the line direction, the conventional TRD LCD has a poor readability in the clear type and is clearer than the liquid crystal display having a general pixel structure having subpixels long in the column direction. Type readability is less than 30%

The present invention provides a liquid crystal display device which can reduce the number of source drive ICs required to drive a data line of a liquid crystal display panel, improve character readability, and realize a uniform display quality over the entire screen.

According to an aspect of the present invention, a liquid crystal display includes a liquid crystal including data lines in a column direction, gate lines in a line direction, and a plurality of pixels arranged in a matrix defined by the data lines and the gate lines. Display panel; A data driving circuit for supplying data voltages to the data lines for writing data to the pixels; And a gate driving circuit sequentially supplying gate pulses to the gate lines. The first pixel on the odd-numbered line of the liquid crystal display panel and the second pixel on the even-numbered line share the first data line and the second data line. Each of the first and second pixels includes a subpixel of a first color into which data of a first color is written, a subpixel of a second color into which data of a second color is written, and a data of a third color into which the first and second pixels are written. It contains three subpixels. After data is written in the subpixels of the first pixel in the order of the data of the first color, the data of the second color, and the data of the third color, the subpixels of the third pixel Data is written in order of data, data of a first color, and data of a second color. The column length of each of the subpixels is longer than the line length of each of the subpixels.

According to another aspect of the present invention, a liquid crystal display includes a liquid crystal including data lines in a column direction, gate lines in a line direction, and a plurality of pixels arranged in a matrix defined by the data lines and the gate lines. Display panel; A data driving circuit for supplying data voltages to the data lines for writing data to the pixels; And a gate driving circuit sequentially supplying gate pulses to the gate lines. The first pixel on the odd-numbered line of the liquid crystal display panel and the second pixel on the even-numbered line share the first data line and the second data line. Each of the first and second pixels includes a subpixel of a first color into which data of a first color is written, a subpixel of a second color into which data of a second color is written, and a data of a third color into which the first and second pixels are written. It contains three subpixels. After data is written in the subpixels of the first pixel in the order of the data of the first color, the data of the second color, and the data of the third color, the subpixels of the third pixel Data is written in order of data, data of the second color, and data of the first color. The column length of each of the subpixels is longer than the line length of each of the subpixels.

According to the present invention, three primary color subpixels are connected to one data line, and three primary color data voltages are time-divisionally supplied to the subpixels, and the column length of each of the subpixels is smaller than the line length. Accordingly, the present invention can reduce the number of source drive ICs required for driving the data line of the liquid crystal display panel, the power consumption and heat generation amount of the source drive IC, and can also improve character readability.

Furthermore, in the present invention, subpixels of one pixel are disposed between the first and second data lines whose polarities are inverted in a column inversion manner, and the subpixels are alternately connected to the other data lines. As a result, the present invention can further reduce the power consumption and heat generation amount of the source drive IC and make the charge amount between the subpixels uniform to realize a uniform display quality over the entire screen.

1 is a view illustrating a part of a pixel array of a conventional TRD liquid crystal display.
FIG. 2 is a diagram illustrating an experiment result in which characters are displayed in a clear type in pixels of FIG. 1.
3 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.
4 is an equivalent circuit diagram showing a part of a pixel array according to the first embodiment of the present invention.
FIG. 5 is a diagram showing an experiment result in which characters are displayed in a clear type on a liquid crystal display having the pixel array shown in FIG. 4.
6 is an equivalent circuit diagram illustrating an example in which the pixel array shown in FIG. 4 is driven with a horizontal 3 dot and a vertical 1 dot inversion.
FIG. 7 is a waveform diagram illustrating a data voltage and a gate pulse for implementing the dot inversion shown in FIG. 6.
FIG. 8 is a diagram illustrating a luminance difference between vertical lines in dot inversion as shown in FIGS. 6 and 7.
9 is an equivalent circuit diagram showing a portion of a pixel array according to a second embodiment of the present invention.
FIG. 10 is a waveform diagram illustrating data voltages and gate pulses for driving the pixel array shown in FIG. 9 to horizontal 1 dot and vertical 1 dot inversion.
11 is an equivalent circuit diagram showing a part of a pixel array according to a third embodiment of the present invention.
FIG. 12 is a waveform diagram illustrating data voltages and gate pulses for driving the pixel array shown in FIG. 11 to horizontal 1 dot and vertical 1 dot inversion.
13 is an equivalent circuit diagram showing a portion of a pixel array according to a fourth embodiment of the present invention.
FIG. 14 is a waveform diagram illustrating data voltages and gate pulses for driving the pixel array shown in FIG. 13 to horizontal 1 dot and vertical 1 dot inversion.
15 is an equivalent circuit diagram showing a part of a pixel array according to the fifth embodiment of the present invention.
FIG. 16 is a waveform diagram illustrating data voltages and gate pulses for driving the pixel array shown in FIG. 15 to horizontal 1 dot and vertical 1 dot inversion.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, when it is determined that a detailed description of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

Referring to FIG. 3, the liquid crystal display according to the exemplary embodiment of the present invention includes a liquid crystal display panel 100, a timing controller 101, a data driving circuit 102, a gate driving circuit 103, and the like.

In the liquid crystal display panel 100, a liquid crystal layer is formed between two glass substrates. The liquid crystal display panel 100 includes pixel arrays arranged in a matrix by a cross structure of the data lines 105 and the gate lines 106.

The TFT array substrate of the liquid crystal display panel 100 includes data lines 105, gate lines 106 crossing the data lines 105, and intersections of the data lines 105 and the gate lines 106. TFTs formed therein, the pixel electrode 1 of the liquid crystal cell Clc connected to the TFT, the storage capacitor Cst connected to the pixel electrode 1, and the like are formed. The data lines 105 are formed along the column direction (y-axis direction), and the gate lines 106 are formed along the line direction (x-axis direction) orthogonal to the column direction. Black matrices, color filters, and the like are formed on the color filter array substrate of the liquid crystal display panel 100.

The liquid crystal cells Clc charge the video data voltage supplied through the TFT and are driven by an electric field between the pixel electrodes 1 and the common electrode 2. The common voltage Vcom is supplied to the common electrode 2. The common electrode 2 may be formed on a TFT array substrate and / or a color filter array substrate. A polarizing plate is attached to each of the TFT array substrate and the color filter array substrate of the liquid crystal display panel 100. On each of the TFT array substrate and the color filter array substrate, the alignment layer for setting the pre-tilt angle of the liquid crystal molecules is formed on the surface in contact with the liquid crystal layer.

The liquid crystal display panel 100 is implemented in a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, or a horizontal electric field driving such as IPS (In Plane Switching) mode and FFS (Fringe Field Switching) mode. It can be implemented in a manner. The liquid crystal display of the present invention may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display. In the transmissive liquid crystal display device and the transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The timing controller 101 arranges the digital video data RGB of the input image input from the host system 104 in a pixel array arrangement of the liquid crystal display panel 100 (FIGS. 4, 9, 11, 13, and 15). The data is rearranged to be supplied to the data driving circuit 102. The timing controller 101 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal Data Enable (DE), and a dot clock CLK from the host system 104. Timing control signals for controlling the operation timing of the driving circuit 102 and the gate driving circuit 103 are generated. The timing control signals include a gate timing control signal for controlling the operation time of the gate driving circuit 103 and a data timing control signal for controlling the operation timing of the data driving circuit 102 and the polarity of the data voltage.

The gate timing control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), and the like. The gate start pulse GSP controls the operation start timing of the gate driving circuit 103. The gate shift clock GSC is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output timing of the gate driving circuit 103.

The data timing control signal includes a source start pulse SSP, a source sampling clock SSC, a polarity control signal POL, a source output enable signal SOE, and the like. The source start pulse SSP controls the data sampling start timing of the data driving circuit 102. The source sampling clock SSC is a clock signal that controls the sampling timing of the digital video data in the data driving circuit 102. The source output enable signal SOE controls the output timing and charge sharing timing of the data driving circuit 102. The polarity control signal POL indicates the polarity inversion timing of the data voltage output from the data driving circuit 102.

The data driver circuit 102 includes a plurality of source drive ICs. The data driving circuit 102 latches the digital video data RGB input from the timing controller 101 in response to the data timing control signal. The data driving circuit 102 converts the digital video data RGB into an analog positive / negative gamma compensation voltage in response to the polarity control signal POL to generate a positive / negative data voltage. The positive / negative data voltage output from the data driving circuit 102 is supplied to the data lines 105. The source drive ICs of the data driving circuit 102 may be connected to the data lines 105 of the liquid crystal display panel 100 by a chip on glass (COG) process or a tape automated bonding (TAB) process.

The gate driving circuit 103 sequentially supplies gate pulses synchronized with the data voltage to the gate lines 106 in response to the gate timing control signals. The gate driving circuit 103 may be formed directly on the TFT array substrate of the liquid crystal display panel 100 by using a gate in panel (GIP) method or may be connected to the gate lines 106 of the liquid crystal display panel 100 by a TAB method. have.

4 is an equivalent circuit diagram showing a part of a pixel array according to the first embodiment of the present invention. In FIG. 4, D1 to D3 are data lines, and G1 to G9 are gate lines.

Referring to FIG. 4, one pixel includes a red subpixel R, a green subpixel G, and a blue subpixel B arranged side by side in a line direction (x-axis direction). The red subpixels R of the pixels are arranged side by side along the column direction (y-axis direction) in 3N (N is a positive integer of 0 or more) + first column. The green subpixels G of the pixels are arranged side by side along the column direction in the 3N + 2th column. The blue subpixels B of the pixels are arranged side by side along the column direction in the 3N + 3 th column.

In the pixel array of FIG. 4, subpixels RGB of one pixel share the same data line and continuously charge the data voltage supplied in a time division manner through the data line. As a result, the liquid crystal display of the present invention can reduce the number of data lines 105 and source drive ICs to one third as compared to a general liquid crystal display in which each of the subpixels is connected to the data line.

The pixel array structure of FIG. 4 will be described in detail with reference to a connection relationship between the subpixels of the first pixel PIX1 and the data line that time-divided charge the data voltages from the first data line D1 as an example.

The pixel electrode and the TFT of the red subpixel R are defined as the first pixel electrode P1 and the first TFT T1, respectively. The pixel electrode and the TFT of the green subpixel G are defined as the second pixel electrode P2 and the second TFT T2, respectively, and the pixel electrode and the TFT of the blue subpixel B are respectively the third pixel electrode ( It is defined as P3) and the third TFT (T3). In order to time-division drive the subpixels of the first pixel, gate pulses are sequentially applied to the first to third gate lines G1 to G3.

The first TFT T1 supplies the red data voltage from the first data line D1 to the first pixel electrode P1 in response to the first gate pulse from the first gate line G1. The gate electrode of the first TFT T1 is connected to the first gate line G1, and the drain electrode is connected to the first data line D1. The source electrode of the first TFT T1 is connected to the first pixel electrode P1. The second TFT T2 supplies the green data voltage from the first data line D1 to the second pixel electrode P2 in response to the second gate pulse from the second gate line G2. The gate electrode of the second TFT T2 is connected to the second gate line G2 and the drain electrode is connected to the first data line D1. The source electrode of the second TFT T2 is connected to the second pixel electrode P2. The third TFT T3 supplies the blue data voltage from the first data line D1 to the third pixel electrode P3 in response to the third gate pulse from the third gate line G3. The gate electrode of the third TFT T3 is connected to the third gate line G3 and the drain electrode is connected to the first data line D1. The source electrode of the third TFT T3 is connected to the third pixel electrode P3.

In FIG. 4, the first gate line G1 is disposed above the pixels, and the second and third gate lines G2 and G3 are disposed below the pixels, but are not limited thereto. For example, the first gate line G1 may be formed under the pixels along with the second and third gate lines G2 and G3.

In the pixel array of FIG. 4, the column direction length of the subpixel is longer than the line direction length. Thus, the subpixel has a long structure in the column direction. Due to the long subpixel structure in the line direction, when small text is displayed in the pixel array of FIG. 4, character readability of the text is significantly higher than that of FIG. 1.

The liquid crystal display device is driven by N (N is a natural number) dot inversion method in which deterioration and afterimage of a liquid crystal are reduced and flicker is hardly observed in a display image. Here, the dot is used in the same meaning as the sub pixel. 6 to 8 illustrate examples of dot inversion driving of the pixel array illustrated in FIG. 4.

6 is an equivalent circuit diagram illustrating an example in which horizontal 3 dot inversion is applied to a liquid crystal display of the present invention. FIG. 7 is a waveform diagram illustrating a data voltage and a gate pulse for implementing the dot inversion shown in FIG. 6.

6 and 7, the polarity control signal POL is inverted in one horizontal period 1H period. One horizontal period 1H means one line scanning time in which data is written in pixels of one display line in the liquid crystal display panel 100. The polarity control signal POL is inverted in phase every frame to invert the polarity of the data voltage charged in the pixel every frame period. The source drive ICs invert the polarity of the data voltages supplied to the data lines D1 to D3 in response to the polarity control signal POL. Each of the data voltages is supplied to the data lines for approximately one third horizontal period.

The gate driving circuit 103 sequentially supplies gate pulses having a pulse width of approximately one horizontal period to the gate lines G1 to G9 to compensate for a relatively insufficient pixel charging time. The n (n is a natural number) gate pulse overlaps the n−1 th gate pulse by approximately 2/3 pulse width and overlaps the n + 1 th gate pulse by about 2/3 pulse width.

After precharging two data voltages, the pixels charge the data voltage to be displayed and hold it for one frame period. For example, in FIG. 6, the blue subpixel B of the first pixel PIX1 is to be displayed after precharging the red and green data voltages R + and G + generated as the positive data voltages. The blue data voltage B + is charged and maintained for approximately one frame period.

In FIG. 6, polarities of data voltages simultaneously supplied to the odd data lines D1 and D3 and the even data line D2 are different from each other. Polarities of the data voltages simultaneously supplied to the odd data lines D1 and D3 and the even data line D2 are inverted every one horizontal period. Accordingly, the data voltages charged in the subpixels of the first pixel are positive data voltages, and the data voltages charged in the subpixels of a second pixel neighboring the first pixel in the same display line are negative data voltages. As a result, the pixel array of FIG. 6 operates with horizontal 3 dots and vertical 1 dot inversion.

The current of the source drive IC is large when transitioned from the positive data voltage to the negative data voltage and vice versa when transitioned from the negative data voltage to the positive data voltage. The power consumption of the source drive IC increases as the number of transitions between voltages having different polarities increases. As shown in FIG. 7, when three data voltages are continuously generated with the same polarity data voltage, power consumption may be lowered to about 1/3 or less as compared to the conventional liquid crystal display.

In the dot inversion as shown in FIGS. 6 and 7, the luminance difference between the vertical lines may be seen. In FIG. 7, since the data voltage charged in the red subpixel R changes from the positive (or negative) voltage to the negative (or positive) voltage, the rising edge is long, whereas the green and blue subpixel (G) is long. , The rising edge is short because the data voltage charged in B) changes from the positive (or negative) voltage to the negative (or positive) voltage. Therefore, the data voltage charge amount of the red subpixel R may be smaller than that of the green and blue subpixels G and B.

In the dot inversion as shown in FIGS. 6 and 7, due to the difference in the amount of data voltage charge between the subpixels, the luminance of the red subpixel R is darker than that of the green and blue subpixels G and B as shown in FIG. 8. Or lighten. In the normally white mode, in which the transmittance of the liquid crystal cell is lower as the data voltage is larger, the luminance of the red subpixel R may appear brighter than that of the green and blue subpixels G and B. FIG. In the normally black mode, in which the transmittance of the liquid crystal cell increases as the data voltage increases, the luminance of the red subpixel R may appear darker than that of the green and blue subpixels G and B. FIG. Therefore, when the liquid crystal display is driven with the dot inversion as shown in FIGS. 6 and 7, streaks in the column direction (y-axis) may be seen in the display image.

The following embodiments may improve display quality by implementing a 1 dot inversion in which the polarity is inverted in units of 1 dot and improving the amount of charge variation between subpixels. In addition, the following embodiments can further reduce the power consumption and the amount of heat generated by the data driving circuit 102 by maintaining the polarity of the data voltage output from the data driving circuit 102 for one frame period.

9 is an equivalent circuit diagram showing a portion of a pixel array according to a second embodiment of the present invention.

Referring to FIG. 9, one pixel includes a red subpixel R, a green subpixel G, and a blue subpixel B arranged side by side in a line direction (x-axis direction). The red subpixels R of the pixels are arranged side by side along the column direction (y-axis direction) in the 3N + 1th column. The green subpixels G of the pixels are arranged side by side along the column direction in the 3N + 2th column. The blue subpixels B of the pixels are arranged side by side along the column direction in the 3N + 3 th column.

In the liquid crystal display device to which the pixel array of FIG. 9 is applied, the number of data lines 105 and the source drive ICs may be reduced to one third as compared to a general liquid crystal display device in which each subpixel is connected to a data line.

In the embodiment of FIG. 9, data supplied to the first pixel PIX1 disposed on the odd-numbered line LINE # 1 and the second pixel PIX2 disposed on the even-numbered line LINE # 2 is converted into a first color. Non-uniform charging of the first and second pixels PIX1 and PIX2 by supplying data, data of a second color, data of a third color, data of a third color, data of a first color, and data of a second color. Improve the problem The first and second pixels PIX1 and PIX2 share a left data line and a right data line. To this end, the first and second pixels PIX1 and PIX2 are connected to the same left data line and the right data line. Each of the first and second pixels PIX1 and PIX2 includes a subpixel of a first color into which data of a first color is written, a subpixel of a second color into which data of a second color is written, and data of a third color. Includes a subpixel of a third color to be written. After data is written in the subpixels of the first pixel in the order of the data of the first color, the data of the second color, and the data of the third color, the data of the third color and the first color of the subpixels of the second pixel. Data is written in the order of the data, and the data of the second color. In FIG. 9, the first color is illustrated in red, the second color is blue, and the third color is green, but is not limited thereto. The color may be changed.

In order to drive the pixel array of FIG. 9, the liquid crystal display panel 100 includes a dummy data line D0 formed at the left end of the pixel array and a dummy data line formed at the right end of the pixel array. The dummy data line D0 formed at the left end of the pixel array is connected to the TFT T92 of the green subpixel G included in the left end pixel of the odd-numbered line LINE # 1, and the even-numbered line LINE #. It is connected to the TFT T94 of the red subpixel R included in the left end pixel of 2). The dummy data line formed at the right end of the pixel array is connected to the TFTs of the red and blue subpixels R and B included in the right end pixel of the odd-numbered line LINE # 1, and the even-numbered line LINE # 2. It is connected to the TFT of the green subpixel G included in the right end pixel of. In Fig. 9, although the dummy data line formed at the right end of the pixel array is omitted, the connection relationship of the dummy data line is substantially the same as that of the third data line D3.

The dummy data line formed at the left end of the pixel array and the dummy data line formed at the right end of the pixel array may be connected to each other and commonly connected to one of the output terminals of the data driving circuit 102. In this case, the data driving circuit 102 may simultaneously supply red, green, and blue data voltages to the left and right dummy data lines of the pixel array through one output terminal.

The pixel of FIG. 9 illustrates a connection relationship between the subpixels of the first and second pixels PIX1 and PIX2 that time-division-charge and charge data voltages from the dummy data line D0 and the first data line D1. The array structure will be described in detail as follows. The first pixel PIX1 is disposed on the odd-numbered line LINE # 1 in the pixel array. The odd-numbered line LINE # 1 includes pixels having the same structure as the first pixel PIX1. The second pixel PIX2 is disposed on the even-numbered line LINE # 2 in the pixel array. The even-numbered line LINE # 2 includes pixels having the same structure as the second pixel PIX2.

The pixel electrode and the TFT of the red subpixel R in the first pixel PIX1 are defined as the first pixel electrode P91 and the first TFT T91, respectively. In the first pixel PIX1, the pixel electrode and the TFT of the green subpixel G are defined as the second pixel electrode P92 and the second TFT T92, and the pixel electrode and the TFT of the blue subpixel B are defined. The third pixel electrode P93 and the third TFT T93 are respectively defined.

In order to time-divisionally drive the subpixels of the first pixel PIX1, the gate driving circuit 103 sequentially transmits gate pulses synchronized with the data voltage to the first to third gate lines G1 to G3 as shown in FIG. 10. Is authorized. The data driving circuit 102 supplies the data voltages maintaining the same polarity to the data lines D0 to D3 for one frame period. The gate pulse is synchronized with the data voltage supplied to the data lines.

In the first pixel PIX1, the first TFT T91 receives the red data voltage from the first data line D1 in response to the first gate pulse from the first gate line G1. Supplies). The gate electrode of the first TFT T91 is connected to the first gate line G1, and the drain electrode is connected to the first data line D1. The source electrode of the first TFT T91 is connected to the first pixel electrode P91. The second TFT T92 supplies the green data voltage from the dummy data line D0 to the second pixel electrode P92 in response to the third gate pulse from the third gate line G3. The gate electrode of the second TFT T92 is connected to the third gate line G3, and the drain electrode is connected to the dummy data line D0. The source electrode of the second TFT T92 is connected to the second pixel electrode P92. The third TFT T93 supplies the blue data voltage from the first data line D1 to the third pixel electrode P93 in response to the second gate pulse from the second gate line G2. The gate electrode of the third TFT T93 is connected to the second gate line G2 and the drain electrode is connected to the first data line D1. The source electrode of the third TFT T93 is connected to the third pixel electrode P93.

In the odd-numbered line LINE # 1, the green subpixels G of each of the pixels are connected to the left data line as in the first pixel PIX1, and the red and blue subpixels R and B are formed in the first line LINE # 1. Like the one pixel PIX1, it is connected to the right data line. In the odd-numbered line LINE # 1, blue data is written to the blue subpixels B by the second gate pulse after red data is written to the red subpixels R by the first gate pulse. Green data is then written to the green subpixels G by the third gate pulse.

In the second pixel PIX2, the pixel electrode and the TFT of the red subpixel R are defined as the fourth pixel electrode P94 and the fourth TFT T94, respectively. In the second pixel PIX2, the pixel electrode and the TFT of the green subpixel G are defined as the fifth pixel electrode P95 and the fifth TFT T95, respectively, and the pixel electrode and the TFT of the blue subpixel B are defined. The sixth pixel electrode P96 and the sixth TFT T96 are respectively defined.

In order to time-divisionally drive the subpixels of the second pixel PIX2, the gate driving circuit 103 sequentially transmits the gate pulses synchronized with the data voltages to the fourth to sixth gate lines G4 to G6 as shown in FIG. 10. Is authorized. The data driving circuit 102 supplies the data voltages maintaining the same polarity to the data lines D0 to D3 for one frame period.

In the second pixel PIX2, the fourth TFT T94 receives the red data voltage from the dummy data line D0 in response to the fifth gate pulse from the fifth gate line G5. To feed. The gate electrode of the fourth TFT T94 is connected to the fifth gate line G5 and the drain electrode is connected to the dummy data line D0. The source electrode of the fourth TFT T94 is connected to the fourth pixel electrode P94. The fifth TFT T95 supplies the green data voltage from the first data line D1 to the fifth pixel electrode P95 in response to the fourth gate pulse from the fourth gate line G4. The gate electrode of the fifth TFT T95 is connected to the fourth gate line G4 and the drain electrode is connected to the first data line D1. The source electrode of the fifth TFT T95 is connected to the fifth pixel electrode P95. The sixth TFT T96 supplies the blue data voltage from the dummy data line D0 to the sixth pixel electrode P96 in response to the sixth gate pulse from the sixth gate line G6. The gate electrode of the sixth TFT T96 is connected to the sixth gate line G6, and the drain electrode is connected to the dummy data line D0. The source electrode of the sixth TFT T96 is connected to the sixth pixel electrode P96.

In the even-numbered line LINE # 2, the red subpixels R of each of the pixels are connected to the left data line like the second pixel PIX2, and the green and blue subpixels G and B are connected to the zeroth line LINE # 2. Similar to the two pixels PIX2, they are connected to the right data line. In the even-numbered line LINE # 2, after the green data is written to the green subpixels G by the fourth gate pulse, the red data is written to the red subpixels R by the fifth gate pulse. Blue data is then written to the blue subpixels B by the sixth gate pulse.

In the pixel array of FIG. 9, the column direction length of the subpixel is longer than the line direction length. Thus, the subpixel has a long structure in the column direction. Due to the long sub-pixel structure in the line direction, displaying small text in the pixel array as shown in FIG. 9 improves the character readability of the text as shown in FIG.

FIG. 10 is a waveform diagram illustrating data voltages and gate pulses for driving the pixel array shown in FIG. 9 to horizontal 1 dot and vertical 1 dot inversion.

9 and 10, the polarity control signal POL maintains the same logic levels H and L for one frame period and the logic levels H and L are inverted in one frame period. For example, the polarity control signal POL maintains the high logic level H during the odd-numbered frame period and the polarity control signal POL maintains the low logic level L during the even-numbered frame period. One frame period means a time to be maintained after data is written to all pixels of the liquid crystal display panel 100 before the next data is input. The source drive ICs maintain the polarity of the data voltage supplied to the data lines D0 to D3 in response to the polarity control signal POL for one frame period and invert the polarity of the new data voltage in the next frame period. Each of the data voltages is supplied to the data lines for approximately one third horizontal period. The source drive ICs maintain the polarity of the data voltages supplied to the data lines D0 to D3 for one frame period, but invert the polarities of the data voltages in the column inversion form to neighbor the data lines D0 to D3. The data voltages of opposite polarities are supplied to D3). For example, the source drive ICs supply a negative data voltage to the odd data lines D0 and D2 and a positive data voltage to even-numbered data lines D1 and D3 during the odd frame period. .

The current of the source drive IC becomes large when transitioned from the positive data voltage to the negative data voltage and when transitioned from the negative data voltage to the positive data voltage. The power consumption of the source drive IC increases as the number of transitions between voltages having different polarities increases. 9 and 10, the source drive IC outputs data voltages whose polarities are not inverted during one frame period. Therefore, in the embodiment of Figs. 9 and 10, the power consumption and heat generation amount of the source drive IC can be significantly improved.

The gate driving circuit 103 sequentially supplies gate pulses having a pulse width of approximately one horizontal period to the gate lines G1 to G6 to compensate for a relatively insufficient pixel charging time. The n th gate pulse overlaps the rear portion of the n−1 th gate pulse by approximately 2/3 pulse width and overlaps the front portion of the n + 1 th gate pulse by approximately 2/3 pulse width.

After precharging two data voltages, the pixels charge the data voltage to be displayed and hold it for one frame period.

Although the data voltages of the same polarity are supplied to the data lines, the subpixels of the pixel array operate in horizontal 1 dot and vertical 1 dot inversion by the arrangement of the pixel array as shown in FIG. 9. Assume that the positive data voltage is supplied to the first data line D1 and the negative data voltage is supplied to the second data line D2 as shown in FIG. 10. In this case, in the pixel of the odd-numbered line LINE # 1 formed between the first and second data lines D1 and D2, the negative polarity from the second data line D2 to the red subpixel R After the red data voltage is charged, the blue subpixel B is charged with the negative blue data voltage from the second data line D2. Subsequently, the green subpixel G is charged with the positive green data voltage from the first data line D1.

In the pixel of the even-numbered line LINE # 2 formed between the first and second data lines D1 and D2, the negative green data voltage from the second data line D2 is applied to the green subpixel G. After charging, the red subpixel R is charged with the positive red data voltage from the first data line D1. Subsequently, the blue subpixel B is charged with the positive blue data voltage from the first data line D1. Each of the subpixels precharges a data voltage of a different color before charging and maintaining the data voltage of a color to be displayed.

11 is an equivalent circuit diagram showing a part of a pixel array according to a third embodiment of the present invention.

Referring to FIG. 11, one pixel includes a red subpixel R, a green subpixel G, and a blue subpixel B arranged side by side in a line direction (x-axis direction). The red subpixels R of the pixels are arranged side by side along the column direction (y-axis direction) in the 3N + 1th column. The green subpixels G of the pixels are arranged side by side along the column direction in the 3N + 2th column. The blue subpixels B of the pixels are arranged side by side along the column direction in the 3N + 3 th column.

In the liquid crystal display device to which the pixel array of FIG. 11 is applied, the number of data lines 105 and the source drive ICs may be reduced to one third as compared to a general liquid crystal display device in which each subpixel is connected to a data line.

11 shows data supplied to a first pixel PIX1 disposed on an odd-numbered line LINE # 1 and a second pixel PIX2 disposed on an even-numbered line LINE # 2 of a first color. Non-uniform charging of the first and second pixels PIX1 and PIX2 by supplying data, data of a second color, data of a third color, data of a third color, data of a first color, and data of a second color. Improve the problem The first and second pixels PIX1 and PIX2 share a left data line and a right data line. To this end, the first and second pixels PIX1 and PIX2 are connected to the same left data line and the right data line. Each of the first and second pixels PIX1 and PIX2 includes a subpixel of a first color into which data of a first color is written, a subpixel of a second color into which data of a second color is written, and data of a third color. Includes a subpixel of a third color to be written. After data is written in the subpixels of the first pixel in the order of the data of the first color, the data of the second color, and the data of the third color, the data of the third color and the first color of the subpixels of the second pixel. Data is written in the order of the data, and the data of the second color. In FIG. 11, the first color is illustrated as blue, the second color as red, and the third color as green, but is not limited thereto, and the color may be changed.

In order to drive the pixel array of FIG. 11, the liquid crystal display panel 100 includes a dummy data line D0 formed at the left end of the pixel array and a dummy data line formed at the right end of the pixel array. The dummy data line D0 formed at the left end of the pixel array includes the TFT T111 of the red subpixel R and the TFT of the blue subpixel B included in the left end pixel of the odd-numbered line LINE # 1. And the TFT T115 of the green subpixel G included in the left end pixel of the even-numbered line LINE # 2. The dummy data line formed at the right end of the pixel array is connected to the TFT of the green subpixel G included in the right end pixel of the odd-numbered line LINE # 1, and the right end pixel of the even-numbered line LINE # 2. Connected to the TFT of the red subpixel R and the TFT of the blue subpixel B. In Fig. 11, although the dummy data line formed at the right end of the pixel array is omitted, the connection relationship of the dummy data line is substantially the same as that of the third data line D3.

The dummy data line formed at the left end of the pixel array and the dummy data line formed at the right end of the pixel array may be connected to each other and commonly connected to one of the output terminals of the data driving circuit 102. In this case, the data driving circuit 102 may simultaneously supply red, green, and blue data voltages to the left and right dummy data lines of the pixel array through one output terminal.

The pixel of FIG. 11 is an example of a connection relationship between the subpixels of the first and second pixels PIX1 and PIX2 that time-division charge the data voltages from the dummy data line D0 and the first data line D1. The array structure will be described in detail as follows. The first pixel PIX1 is disposed on the odd-numbered line LINE # 1 in the pixel array. The odd-numbered line LINE # 1 includes pixels having the same structure as the first pixel PIX1. The second pixel PIX2 is disposed on the even-numbered line LINE # 2 in the pixel array. The even-numbered line LINE # 2 includes pixels having the same structure as the second pixel PIX2.

The pixel electrode and the TFT of the red subpixel R in the first pixel PIX1 are defined as the first pixel electrode P111 and the first TFT T111, respectively. In the first pixel PIX1, the pixel electrode and the TFT of the green subpixel G are defined as the second pixel electrode P112 and the second TFT T112, respectively, and the pixel electrode and the TFT of the blue subpixel B are defined. The third pixel electrode P113 and the third TFT T113 are respectively defined.

In order to time-divisionally drive the subpixels of the first pixel PIX1, the gate driving circuit 103 sequentially transmits gate pulses synchronized with the data voltage to the first to third gate lines G1 to G3 as shown in FIG. 12. Is authorized. The data driving circuit 102 supplies the data voltages maintaining the same polarity to the data lines D0 to D3 for one frame period.

In the first pixel PIX1, the first TFT T111 receives the red data voltage from the dummy data line D0 in response to the second gate pulse from the second gate line G2. To feed. The gate electrode of the first TFT T111 is connected to the second gate line G2, and the drain electrode is connected to the dummy data line D0. The source electrode of the first TFT T111 is connected to the first pixel electrode P111. The second TFT T112 supplies the green data voltage from the first data line D1 to the second pixel electrode P112 in response to the third gate pulse from the third gate line G3. The gate electrode of the second TFT T112 is connected to the third gate line G3 and the drain electrode is connected to the first data line D1. The source electrode of the second TFT T112 is connected to the second pixel electrode P112. The third TFT T113 supplies the blue data voltage from the dummy data line D0 to the third pixel electrode P113 in response to the first gate pulse from the first gate line G1. The gate electrode of the third TFT T113 is connected to the first gate line G1, and the drain electrode is connected to the dummy data line D0. The source electrode of the third TFT T113 is connected to the third pixel electrode P113.

In the odd-numbered line LINE # 1, the red and blue subpixels R and B of each of the pixels are connected to the left data line like the first pixel PIX1, and the green subpixels G are formed in the first line LINE # 1. Like the one pixel PIX1, it is connected to the right data line. In the odd-numbered line LINE # 1, after the blue data is written to the blue subpixels B by the first gate pulse, the red data is written to the red subpixels R by the second gate pulse. Green data is then written to the green subpixels G by the third gate pulse.

In the second pixel PIX2, the pixel electrode and the TFT of the red subpixel R are defined as the fourth pixel electrode P114 and the fourth TFT T114, respectively. In the second pixel PIX2, the pixel electrode and the TFT of the green subpixel G are defined as the fifth pixel electrode P115 and the fifth TFT T115, respectively, and the pixel electrode and the TFT of the blue subpixel B are defined. The sixth pixel electrode P116 and the sixth TFT T116 are respectively defined.

In order to time-divisionally drive the subpixels of the second pixel PIX2, the gate driving circuit 103 sequentially transmits the gate pulses synchronized with the data voltages to the fourth to sixth gate lines G4 to G6 as shown in FIG. 10. Is authorized. The data driving circuit 102 supplies a data voltage synchronized with the gate pulses maintaining the same polarity to the data lines D0 to D3 for one frame period.

In the second pixel PIX2, the fourth TFT T114 receives the red data voltage from the first data line D1 in response to the sixth gate pulse from the sixth gate line G6. Supplies). The gate electrode of the fourth TFT T114 is connected to the sixth gate line G6 and the drain electrode is connected to the first data line D1. The source electrode of the fourth TFT T114 is connected to the fourth pixel electrode P114. The fifth TFT T115 supplies the green data voltage from the dummy data line D0 to the fifth pixel electrode P115 in response to the fourth gate pulse from the fourth gate line G4. The gate electrode of the fifth TFT T115 is connected to the fourth gate line G4, and the drain electrode is connected to the dummy data line D0. The source electrode of the fifth TFT T115 is connected to the fifth pixel electrode P115. The sixth TFT T116 supplies the blue data voltage from the first data line D1 to the sixth pixel electrode P116 in response to the fifth gate pulse from the fifth gate line G5. The gate electrode of the sixth TFT T116 is connected to the fifth gate line G5, and the drain electrode is connected to the first data line D1. The source electrode of the sixth TFT T116 is connected to the sixth pixel electrode P116.

In the even-numbered line LINE # 2, the green subpixels G of each of the pixels are connected to the left data line similarly to the second pixel PIX2, and the red and blue subpixels R and B are connected to the zeroth line LINE # 2. Similar to the two pixels PIX2, they are connected to the right data line. In the even-numbered line LINE # 2, after the green data is written to the green subpixels G by the fourth gate pulse, the blue data is written to the blue subpixels B by the fifth gate pulse. Red data is then written to the red subpixels R by the sixth gate pulse.

In the pixel array of FIG. 11, the column direction length of the subpixel is longer than the line direction length. Thus, the subpixel has a long structure in the column direction. Due to the long sub-pixel structure in the line direction, displaying small text in the pixel array as shown in FIG. 11 improves the character readability of the text as shown in FIG.

FIG. 12 is a waveform diagram illustrating data voltages and gate pulses for driving the pixel array shown in FIG. 11 to horizontal 1 dot and vertical 1 dot inversion.

11 and 12, the polarity control signal POL maintains the same logic levels H and L for one frame period, and the logic levels H and L are inverted in one frame period. For example, the polarity control signal POL maintains the high logic level H during the odd-numbered frame period and the polarity control signal POL maintains the low logic level L during the even-numbered frame period. The source drive ICs maintain the polarity of the data voltage supplied to the data lines D0 to D3 in response to the polarity control signal POL for one frame period and invert the polarity of the new data voltage in the next frame period. Each of the data voltages is supplied to the data lines for approximately one third horizontal period. The source drive ICs maintain the polarity of the data voltages supplied to the data lines D0 to D3 for one frame period, but invert the polarities of the data voltages in the column inversion form to neighbor the data lines D0 to D3. The data voltages of opposite polarities are supplied to D3). For example, the source drive ICs supply a negative data voltage to the odd data lines D0 and D2 and a positive data voltage to even-numbered data lines D1 and D3 during the odd frame period. .

The current of the source drive IC becomes large when transitioned from the positive data voltage to the negative data voltage and when transitioned from the negative data voltage to the positive data voltage. The power consumption of the source drive IC increases as the number of transitions between voltages having different polarities increases. 11 and 12, the source drive IC outputs data voltages whose polarities are not inverted during one frame period. Thus, in the embodiment of Figs. 11 and 12, the power consumption and heat generation of the source drive IC can be significantly improved.

The gate driving circuit 103 sequentially supplies gate pulses having a pulse width of approximately one horizontal period to the gate lines G1 to G6 to compensate for a relatively insufficient pixel charging time. The n th gate pulse overlaps the rear portion of the n−1 th gate pulse by approximately 2/3 pulse width and overlaps the front portion of the n + 1 th gate pulse by approximately 2/3 pulse width. Each of the pixels charges the data voltage to be displayed after precharging two data voltages and maintains the data voltage for one frame period.

Although data voltages of the same polarity are supplied to the data lines, the subpixels of the pixel array operate in horizontal 1 dot and vertical 1 dot inversions by the arrangement of the pixel array as shown in FIG. 11. As shown in FIG. 12, it is assumed that a positive data voltage is supplied to the first data line D1 and a negative data voltage is supplied to the second data line D2. In this case, in the pixel of the odd-numbered line LINE # 1 formed between the first and second data lines D1 and D2, the positive polarity from the first data line D1 to the blue subpixel B is. After the blue data voltage is charged, the red subpixel R is charged with the positive red data voltage from the first data line D1. Subsequently, the green subpixel G is charged with the negative green data voltage from the second data line D2.

In the pixel of the even-numbered line LINE # 2 formed between the first and second data lines D1 and D2, the green subpixel G has a positive green data voltage from the first data line D1. After charging, the blue subpixel B is charged with the negative blue data voltage from the second data line D2. Subsequently, the red subpixel R is charged with the negative red data voltage from the second data line D2. Each of the subpixels precharges a data voltage of a different color before charging and maintaining the data voltage of a color to be displayed.

13 is an equivalent circuit diagram showing a portion of a pixel array according to a fourth embodiment of the present invention.

Referring to FIG. 13, one pixel includes a red subpixel R, a green subpixel G, and a blue subpixel B arranged side by side in a line direction (x-axis direction). The red subpixels R of the pixels are arranged side by side along the column direction (y-axis direction) in the 3N + 1th column. The green subpixels G of the pixels are arranged side by side along the column direction in the 3N + 2th column. The blue subpixels B of the pixels are arranged side by side along the column direction in the 3N + 3 th column.

In the liquid crystal display device to which the pixel array of FIG. 13 is applied, the number of data lines 105 and the source drive ICs may be reduced to one third as compared to a general liquid crystal display device in which each subpixel is connected to a data line.

In the embodiment of FIG. 13, the data supplied to the first pixel PIX1 disposed on the odd-numbered line LINE # 1 and the second pixel PIX2 disposed on the even-numbered line LINE # 2 is obtained by using the first color. Non-uniform charging of the first and second pixels PIX1 and PIX2 by supplying data, data of a second color, data of a third color, data of a third color, data of a second color, and data of a first color. Improve the problem The first and second pixels PIX1 and PIX2 share a left data line and a right data line. To this end, the first and second pixels PIX1 and PIX2 are connected to the same left data line and the right data line. Each of the first and second pixels PIX1 and PIX2 includes a subpixel of a first color into which data of a first color is written, a subpixel of a second color into which data of a second color is written, and data of a third color. Includes a subpixel of a third color to be written. After data is written in the subpixels of the first pixel in the order of the data of the first color, the data of the second color, and the data of the third color, the data of the third color and the second color of the subpixels of the second pixel. Data is written in the order of the data, and the data of the first color. In FIG. 13, the first color is red, the second color is green, and the third color is illustrated as blue, but the present invention is not limited thereto, and the color may be changed.

In order to drive the pixel array of FIG. 13, the liquid crystal display panel 100 includes a dummy data line D0 formed at the left end of the pixel array and a dummy data line formed at the right end of the pixel array. The dummy data line D0 formed at the left end of the pixel array includes the TFT T131 of the red subpixel R and the TFT of the blue subpixel B included in the left end pixel of the odd-numbered line LINE # 1. It is connected to T133, and is connected to the TFT T135 of the green subpixel G included in the left end pixel of the even-numbered line LINE # 2. The dummy data line formed at the right end of the pixel array is connected to the TFT of the green subpixel G included in the right end pixel of the odd-numbered line LINE # 1, and the right end pixel of the even-numbered line LINE # 2. Connected to the TFT of the red subpixel R and the TFT of the blue subpixel B. In Fig. 13, the dummy data line formed at the right end of the pixel array is omitted, but the connection relationship of the dummy data line is substantially the same as that of the third data line D3.

The dummy data line formed at the left end of the pixel array and the dummy data line formed at the right end of the pixel array may be connected to each other and commonly connected to one of the output terminals of the data driving circuit 102. In this case, the data driving circuit 102 may simultaneously supply red, green, and blue data voltages to the left and right dummy data lines of the pixel array through one output terminal.

For example, the pixel of FIG. 13 is connected to the data lines and the subpixels of the first and second pixels PIX1 and PIX2 that time-division charge the data voltages from the dummy data line D0 and the first data line D1. The array structure will be described in detail as follows. The first pixel PIX1 is disposed on the odd-numbered line LINE # 1 in the pixel array. The odd-numbered line LINE # 1 includes pixels having the same structure as the first pixel PIX1. The second pixel PIX2 is disposed on the even-numbered line LINE # 2 in the pixel array. The even-numbered line LINE # 2 includes pixels having the same structure as the second pixel PIX2.

The pixel electrode and the TFT of the red subpixel R in the first pixel PIX1 are defined as the first pixel electrode P131 and the first TFT T131, respectively. In the first pixel PIX1, the pixel electrode and the TFT of the green subpixel G are defined as the second pixel electrode P132 and the second TFT T132, and the pixel electrode and the TFT of the blue subpixel B are defined. The third pixel electrode P133 and the third TFT T133 are respectively defined.

In order to time-divisionally drive the subpixels of the first pixel PIX1, the gate driving circuit 103 sequentially transmits gate pulses synchronized with the data voltage to the first to third gate lines G1 to G3 as shown in FIG. 14. Is authorized. The data driving circuit 102 supplies the data voltages maintaining the same polarity to the data lines D0 to D3 for one frame period.

In the first pixel PIX1, the first TFT T131 receives the red data voltage from the dummy data line D0 in response to the first gate pulse from the first gate line G1. To feed. The gate electrode of the first TFT T131 is connected to the first gate line G1, and the drain electrode is connected to the dummy data line D0. The source electrode of the first TFT T131 is connected to the first pixel electrode P131. The second TFT T132 supplies the green data voltage from the first data line D1 to the second pixel electrode P132 in response to the second gate pulse from the second gate line G2. The gate electrode of the second TFT T132 is connected to the second gate line G2, and the drain electrode is connected to the first data line D1. The source electrode of the second TFT T132 is connected to the second pixel electrode P132. The third TFT T133 supplies the blue data voltage from the dummy data line D0 to the third pixel electrode P133 in response to the third gate pulse from the third gate line G3. The gate electrode of the third TFT T133 is connected to the third gate line G3, and the drain electrode is connected to the dummy data line D0. The source electrode of the third TFT T133 is connected to the third pixel electrode P133.

In the odd-numbered line LINE # 1, the red and blue subpixels R and B of each of the pixels are connected to the left data line like the first pixel PIX1, and the green subpixels G are formed in the first line LINE # 1. Like the one pixel PIX1, it is connected to the right data line. In the odd-numbered line LINE # 1, after the red data is written to the red subpixels G by the first gate pulse, the green data is written to the green subpixels G by the second gate pulse. Blue data is then written to the blue subpixels B by the third gate pulse.

In the second pixel PIX2, the pixel electrode and the TFT of the red subpixel R are defined as the fourth pixel electrode P134 and the fourth TFT T134, respectively. In the second pixel PIX2, the pixel electrode and the TFT of the green subpixel G are defined as the fifth pixel electrode P135 and the fifth TFT T135, respectively, and the pixel electrode and the TFT of the blue subpixel B are defined. The sixth pixel electrode P136 and the sixth TFT T136 are respectively defined.

In order to time-divisionally drive the subpixels of the second pixel PIX2, the gate driving circuit 103 sequentially transmits gate pulses synchronized with the data voltages to the fourth to sixth gate lines G4 to G6 as shown in FIG. 14. Is authorized. The data driving circuit 102 supplies a data voltage synchronized with the gate pulses maintaining the same polarity to the data lines D0 to D3 for one frame period.

In the second pixel PIX2, the fourth TFT T134 receives the red data voltage from the first data line D1 in response to the sixth gate pulse from the sixth gate line G6. Supplies). The gate electrode of the fourth TFT T134 is connected to the sixth gate line G6, and the drain electrode is connected to the first data line D1. The source electrode of the fourth TFT T134 is connected to the fourth pixel electrode P134. The fifth TFT T135 supplies the green data voltage from the dummy data line D0 to the fifth pixel electrode P135 in response to the fifth gate pulse from the fifth gate line G5. The gate electrode of the fifth TFT T135 is connected to the fifth gate line G5 and the drain electrode is connected to the dummy data line D0. The source electrode of the fifth TFT T135 is connected to the fifth pixel electrode P135. The sixth TFT T136 supplies the blue data voltage from the first data line D1 to the sixth pixel electrode P136 in response to the fourth gate pulse from the fourth gate line G4. The gate electrode of the sixth TFT T136 is connected to the fourth gate line G4, and the drain electrode is connected to the first data line D1. The source electrode of the sixth TFT T136 is connected to the sixth pixel electrode P136.

In the even-numbered line LINE # 2, the green subpixels G of each of the pixels are connected to the left data line similarly to the second pixel PIX2, and the red and blue subpixels R and B are connected to the zeroth line LINE # 2. Similar to the two pixels PIX2, they are connected to the right data line. In the even-numbered line LINE # 2, after the blue data is written to the blue subpixels B by the fourth gate pulse, the green data is written to the green subpixels G by the fifth gate pulse. Red data is then written to the red subpixels R by the sixth gate pulse.

In the pixel array of FIG. 13, the column direction length of the subpixel is longer than the line direction length. Thus, the subpixel has a long structure in the column direction. Due to the long sub-pixel structure in the line direction, displaying small text in the pixel array as shown in FIG. 13 improves the character readability of the text as shown in FIG.

FIG. 14 is a waveform diagram illustrating data voltages and gate pulses for driving the pixel array shown in FIG. 13 to horizontal 1 dot and vertical 1 dot inversion.

13 and 14, the polarity control signal POL maintains the same logic levels H and L for one frame period, and the logic levels H and L are inverted in one frame period. For example, the polarity control signal POL maintains the high logic level H during the odd-numbered frame period and the polarity control signal POL maintains the low logic level L during the even-numbered frame period. The source drive ICs maintain the polarity of the data voltage supplied to the data lines D0 to D3 in response to the polarity control signal POL for one frame period and invert the polarity of the new data voltage in the next frame period. Each of the data voltages is supplied to the data lines for approximately one third horizontal period. The source drive ICs maintain the polarity of the data voltages supplied to the data lines D0 to D3 for one frame period, but invert the polarities of the data voltages in the column inversion form to neighbor the data lines D0 to D3. The data voltages of opposite polarities are supplied to D3). For example, the source drive ICs supply a negative data voltage to the odd data lines D0 and D2 and a positive data voltage to even-numbered data lines D1 and D3 during the odd frame period. .

The current of the source drive IC becomes large when transitioned from the positive data voltage to the negative data voltage and when transitioned from the negative data voltage to the positive data voltage. The power consumption of the source drive IC increases as the number of transitions between voltages having different polarities increases. 13 and 14, the source drive IC outputs data voltages whose polarities are not inverted during one frame period. Thus, in the embodiment of Figs. 13 and 14, the power consumption and heat generation amount of the source drive IC can be significantly improved.

The gate driving circuit 103 sequentially supplies gate pulses having a pulse width of approximately one horizontal period to the gate lines G1 to G6 to compensate for a relatively insufficient pixel charging time. The n th gate pulse overlaps the rear portion of the n−1 th gate pulse by approximately 2/3 pulse width and overlaps the front portion of the n + 1 th gate pulse by approximately 2/3 pulse width. Each of the pixels charges the data voltage to be displayed after precharging two data voltages and maintains the data voltage for one frame period.

Although the data voltages of the same polarity are supplied to the data lines, the subpixels of the pixel array operate in horizontal 1 dot and vertical 1 dot inversion by the arrangement of the pixel array as shown in FIG. 13. Assume that the positive data voltage is supplied to the first data line D1 and the negative data voltage is supplied to the second data line D2 as shown in FIG. 14. In this case, in the pixel of the odd-numbered line LINE # 1 formed between the first and second data lines D1 and D2, the positive polarity from the first data line D1 to the red subpixel R is shown. After the red data voltage is charged, the negative green data voltage from the second data line D2 is charged in the green subpixel G. Subsequently, the blue subpixel B is charged with the positive blue data voltage from the first data line D1.

In the pixel of the even-numbered line LINE # 2 formed between the first and second data lines D1 and D2, the blue subpixel B has a negative blue data voltage from the second data line D2. After charging, the green subpixel G is charged with the positive green data voltage from the first data line D1. Subsequently, the red subpixel R is charged with the negative red data voltage from the second data line D2.

15 is an equivalent circuit diagram showing a part of a pixel array according to the fifth embodiment of the present invention.

Referring to FIG. 15, one pixel includes a red subpixel R, a green subpixel G, and a blue subpixel B arranged side by side in a line direction (x-axis direction). The red subpixels R of the pixels are arranged side by side along the column direction (y-axis direction) in the 3N + 1th column. The green subpixels G of the pixels are arranged side by side along the column direction in the 3N + 2th column. The blue subpixels B of the pixels are arranged side by side along the column direction in the 3N + 3 th column.

In the liquid crystal display device to which the pixel array of FIG. 15 is applied, the number of data lines 105 and the source drive ICs may be reduced to one third as compared to a general liquid crystal display device in which each subpixel is connected to a data line.

In the embodiment of FIG. 15, the data supplied to the first pixel PIX1 disposed on the odd-numbered line LINE # 1 and the second pixel PIX2 disposed on the even-numbered line LINE # 2 is obtained by using the first color PIX1. Non-uniform charging of the first and second pixels PIX1 and PIX2 by supplying data, data of a second color, data of a third color, data of a third color, data of a second color, and data of a first color. Improve the problem The first and second pixels PIX1 and PIX2 share a left data line and a right data line. To this end, the first and second pixels PIX1 and PIX2 are connected to the same left data line and the right data line. Each of the first and second pixels PIX1 and PIX2 includes a subpixel of a first color into which data of a first color is written, a subpixel of a second color into which data of a second color is written, and data of a third color. Includes a subpixel of a third color to be written. After data is written in the subpixels of the first pixel in the order of the data of the first color, the data of the second color, and the data of the third color, the data of the third color and the second color of the subpixels of the second pixel. Data is written in the order of the data, and the data of the first color. In FIG. 15, the first color is illustrated in blue, the second color is green, and the third color is red, but the color is not limited thereto.

In order to drive the pixel array of FIG. 15, the liquid crystal display panel 100 includes a dummy data line D0 formed at the left end of the pixel array and a dummy data line formed at the right end of the pixel array. The dummy data line D0 formed at the left end of the pixel array is connected to the TFT T152 of the green subpixel G included in the left end pixel of the odd-numbered line LINE # 1 and the even-numbered line LINE #. It is connected to the TFT T154 of the red subpixel R and the TFT T156 of the blue subpixel B included in the left end pixel of 2). The dummy data line formed at the right end of the pixel array is connected to the TFT of the red subpixel R and the TFT of the blue subpixel B included in the right end pixel of the odd-numbered line LINE # 1, and the even-numbered line It is connected to the TFT of the green subpixel G included in the right end pixel of LINE # 2. In Fig. 15, the dummy data line formed at the right end of the pixel array is omitted, but the connection relationship of the dummy data line is substantially the same as that of the third data line D3.

The dummy data line formed at the left end of the pixel array and the dummy data line formed at the right end of the pixel array may be connected to each other and commonly connected to one of the output terminals of the data driving circuit 102. In this case, the data driving circuit 102 may simultaneously supply red, green, and blue data voltages to the left and right dummy data lines of the pixel array through one output terminal.

The pixel of FIG. 15 illustrates a connection relationship between the subpixels of the first and second pixels PIX1 and PIX2 that time-division-charge and charge the data voltages from the dummy data line D0 and the first data line D1. The array structure will be described in detail as follows. The first pixel PIX1 is disposed on the odd-numbered line LINE # 1 in the pixel array. The odd-numbered line LINE # 1 includes pixels having the same structure as the first pixel PIX1. The second pixel PIX2 is disposed on the even-numbered line LINE # 2 in the pixel array. The even-numbered line LINE # 2 includes pixels having the same structure as the second pixel PIX2.

The pixel electrode and the TFT of the red subpixel R in the first pixel PIX1 are defined as the first pixel electrode P151 and the first TFT T151, respectively. In the first pixel PIX1, the pixel electrode and the TFT of the green subpixel G are defined as the second pixel electrode P152 and the second TFT T152, respectively, and the pixel electrode and the TFT of the blue subpixel B are defined. The third pixel electrode P153 and the third TFT T153 are respectively defined.

In order to time-divisionally drive the subpixels of the first pixel PIX1, the gate driving circuit 103 sequentially transmits gate pulses synchronized with the data voltage to the first to third gate lines G1 to G3 as shown in FIG. 16. Is authorized. The data driving circuit 102 supplies the data voltages maintaining the same polarity to the data lines D0 to D3 for one frame period.

In the first pixel PIX1, the first TFT T151 receives the red data voltage from the first data line D1 in response to the third gate pulse from the third gate line G3. Supplies). The gate electrode of the first TFT T151 is connected to the third gate line G3, and the drain electrode is connected to the first data line D1. The source electrode of the first TFT T151 is connected to the first pixel electrode P151. The second TFT T152 supplies the green data voltage from the dummy data line D0 to the second pixel electrode P152 in response to the second gate pulse from the second gate line G2. The gate electrode of the second TFT T152 is connected to the second gate line G2, and the drain electrode is connected to the dummy data line D0. The source electrode of the second TFT T152 is connected to the second pixel electrode P152. The third TFT T153 supplies the blue data voltage from the first data line D1 to the third pixel electrode P153 in response to the first gate pulse from the first gate line G1. The gate electrode of the third TFT T153 is connected to the first gate line G1 and the drain electrode is connected to the first data line D1. The source electrode of the third TFT T153 is connected to the third pixel electrode P153.

In the odd-numbered line LINE # 1, the green subpixels G of each of the pixels are connected to the left data line as in the first pixel PIX1, and the red and blue subpixels R and B are formed in the first line LINE # 1. Like the one pixel PIX1, it is connected to the right data line. In the odd-numbered line LINE # 1, green data is written to the green subpixels G by the second gate pulse after blue data is written to the blue subpixels B by the first gate pulse. Subsequently, red data is written to the red subpixels R by the third gate pulse.

In the second pixel PIX2, the pixel electrode and the TFT of the red subpixel R are defined as the fourth pixel electrode P154 and the fourth TFT T154, respectively. In the second pixel PIX2, the pixel electrode and the TFT of the green subpixel G are defined as the fifth pixel electrode P155 and the fifth TFT T155, respectively, and the pixel electrode and the TFT of the blue subpixel B are defined. The sixth pixel electrode P156 and the sixth TFT T156 are respectively defined.

In order to time-divisionally drive the subpixels of the second pixel PIX2, the gate driving circuit 103 sequentially transmits gate pulses synchronized with the data voltage to the fourth to sixth gate lines G4 to G6 as shown in FIG. 16. Is authorized. The data driving circuit 102 supplies a data voltage synchronized with the gate pulses maintaining the same polarity to the data lines D0 to D3 for one frame period.

In the second pixel PIX2, the fourth TFT T154 receives the red data voltage from the dummy data line D0 in response to the fourth gate pulse from the fourth gate line G4. To feed. The gate electrode of the fourth TFT T154 is connected to the fourth gate line G4, and the drain electrode is connected to the dummy data line D0. The source electrode of the fourth TFT T154 is connected to the fourth pixel electrode P154. The fifth TFT T155 supplies the green data voltage from the first data line D1 to the fifth pixel electrode P155 in response to the fifth gate pulse from the fifth gate line G5. The gate electrode of the fifth TFT T155 is connected to the fifth gate line G5, and the drain electrode is connected to the first data line D1. The source electrode of the fifth TFT T155 is connected to the fifth pixel electrode P155. The sixth TFT T156 supplies the blue data voltage from the dummy data line D0 to the sixth pixel electrode P156 in response to the sixth gate pulse from the sixth gate line G6. The gate electrode of the sixth TFT T156 is connected to the sixth gate line G6, and the drain electrode is connected to the dummy data line D0. The source electrode of the sixth TFT T156 is connected to the sixth pixel electrode P156.

In the even-numbered line LINE # 2, the red and blue subpixels R and B of each of the pixels are connected to the left data line as in the second pixel PIX2, and the green subpixels G are formed in the zeroth line LINE # 2. Similar to the two pixels PIX2, they are connected to the right data line. In the even-numbered line LINE # 2, after the red data is written to the red subpixels R by the fourth gate pulse, the green data is written to the green subpixels G by the fifth gate pulse. Blue data is then written to the blue subpixels B by the sixth gate pulse.

In the pixel array of FIG. 15, the column direction length of the subpixel is longer than the line direction length. Thus, the subpixel has a long structure in the column direction. Due to the long sub-pixel structure in the line direction, displaying small text in the pixel array as shown in FIG. 15 improves the character readability of the text as shown in FIG.

FIG. 16 is a waveform diagram illustrating data voltages and gate pulses for driving the pixel array shown in FIG. 15 to horizontal 1 dot and vertical 1 dot inversion.

15 and 16, the polarity control signal POL maintains the same logic levels H and L for one frame period, and the logic levels H and L are inverted in one frame period. For example, the polarity control signal POL maintains the high logic level H during the odd-numbered frame period and the polarity control signal POL maintains the low logic level L during the even-numbered frame period. The source drive ICs maintain the polarity of the data voltage supplied to the data lines D0 to D3 in response to the polarity control signal POL for one frame period and invert the polarity of the new data voltage in the next frame period. Each of the data voltages is supplied to the data lines for approximately one third horizontal period. The source drive ICs maintain the polarity of the data voltages supplied to the data lines D0 to D3 for one frame period, but invert the polarities of the data voltages in the column inversion form to neighbor the data lines D0 to D3. The data voltages of opposite polarities are supplied to D3). For example, the source drive ICs supply a negative data voltage to the odd data lines D0 and D2 and a positive data voltage to even-numbered data lines D1 and D3 during the odd frame period. .

The current of the source drive IC becomes large when transitioned from the positive data voltage to the negative data voltage and when transitioned from the negative data voltage to the positive data voltage. The power consumption of the source drive IC increases as the number of transitions between voltages having different polarities increases. 15 and 16, the source drive IC outputs data voltages whose polarities are not inverted during one frame period. Thus, in the embodiment of Figs. 15 and 16, the power consumption and heat generation amount of the source drive IC can be significantly improved.

The gate driving circuit 103 sequentially supplies gate pulses having a pulse width of approximately one horizontal period to the gate lines G1 to G6 to compensate for a relatively insufficient pixel charging time. The n th gate pulse overlaps the rear portion of the n−1 th gate pulse by approximately 2/3 pulse width and overlaps the front portion of the n + 1 th gate pulse by approximately 2/3 pulse width. Each of the pixels charges the data voltage to be displayed after precharging two data voltages and maintains the data voltage for one frame period.

Although the data voltages of the same polarity are supplied to the data lines, the subpixels of the pixel array operate in horizontal 1 dot and vertical 1 dot inversion by the arrangement of the pixel array as shown in FIG. 15. Assume that the positive data voltage is supplied to the first data line D1 and the negative data voltage is supplied to the second data line D2 as shown in FIG. 16. In this case, in the pixel of the odd-numbered line LINE # 1 formed between the first and second data lines D1 and D2, the negative polarity from the second data line D2 to the blue subpixel B is used. After the blue data voltage is charged, the positive green data voltage from the first data line D1 is charged in the green subpixel G. Subsequently, the negative blue data voltage from the second data line D2 is charged to the red subpixel R.

In the pixel of the even-numbered line LINE # 2 formed between the first and second data lines D1 and D2, the red subpixel R has a positive red data voltage from the first data line D1. After charging, the green subpixel G is charged with the negative green data voltage from the second data line D2. Subsequently, the blue subpixel B is charged with the positive blue data voltage from the first data line D1.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100: liquid crystal display panel 101: timing controller
102: Data driving circuit 103: Gate driving circuit

Claims (10)

A liquid crystal display panel including data lines in a column direction, gate lines in a line direction, and a plurality of pixels arranged in a matrix defined by the data lines and the gate lines;
A data driving circuit for supplying data voltages to the data lines for writing data to the pixels; And
A gate driving circuit which sequentially supplies gate pulses to the gate lines;
The first pixel on the odd-numbered line of the liquid crystal display panel and the second pixel on the even-numbered line share the first data line and the second data line.
Each of the first and second pixels includes a subpixel of a first color into which data of a first color is written, a subpixel of a second color into which data of a second color is written, and a data of a third color into which the first and second pixels are written. Contains 3 subpixels,
After data is written in the subpixels of the first pixel in the order of the data of the first color, the data of the second color, and the data of the third color, the subpixels of the third pixel Data is written in the order of data, data of a first color, and data of a second color,
And a column direction length of each of the subpixels is longer than a line direction length of each of the subpixels.
The method of claim 1,
A data voltage maintaining a first polarity is supplied to the first data line for one frame period,
And a data voltage maintaining a second polarity for the one frame period to the second data line.
The method of claim 2,
The first pixel,
A first TFT supplying a data voltage of the first color from the second data line to a first pixel electrode in response to a first gate pulse from a first gate line;
A second TFT supplying a data voltage of the third color from the first data line to a second pixel electrode in response to a third gate pulse from a third gate line; And
A third TFT supplying a data voltage of the second color from the second data line to a third pixel electrode in response to a second gate pulse from a second gate line,
The second pixel,
A fourth TFT supplying a data voltage of the first color from the first data line to a fourth pixel electrode in response to a fifth gate pulse from a fifth gate line;
A fifth TFT supplying a data voltage of the third color from the second data line to a fifth pixel electrode in response to a fourth gate pulse from a fourth gate line; And
A sixth TFT supplying a data voltage of the second color from the first data line to a sixth pixel electrode in response to a sixth gate pulse from a sixth gate line,
The gate pulses are generated in the order of the first gate pulse, the second gate pulse, the third gate pulse, the fourth gate pulse, the fifth gate pulse, and the sixth gate pulse. Display.
The method of claim 2,
The first pixel,
A first TFT supplying a data voltage of the second color from the first data line to a first pixel electrode in response to a second gate pulse from a second gate line;
A second TFT supplying a data voltage of the third color from the second data line to a second pixel electrode in response to a third gate pulse from a third gate line; And
A third TFT supplying a data voltage of the first color from the first data line to a third pixel electrode in response to a first gate pulse from a first gate line,
The second pixel,
A fourth TFT supplying a data voltage of the second color from the second data line to a fourth pixel electrode in response to a sixth gate pulse from a sixth gate line;
A fifth TFT supplying a data voltage of the third color from the first data line to a fifth pixel electrode in response to a fourth gate pulse from a fourth gate line; And
A sixth TFT supplying a data voltage of the first color from the second data line to a sixth pixel electrode in response to a fifth gate pulse from a fifth gate line,
The gate pulses are generated in the order of the first gate pulse, the second gate pulse, the third gate pulse, the fourth gate pulse, the fifth gate pulse, and the sixth gate pulse. Display.
The method of claim 1,
Wherein the polarities of the pixels are inverted by one horizontal and one vertical dot inversion.
A liquid crystal display panel including data lines in a column direction, gate lines in a line direction, and a plurality of pixels arranged in a matrix defined by the data lines and the gate lines;
A data driving circuit for supplying data voltages to the data lines for writing data to the pixels; And
A gate driving circuit which sequentially supplies gate pulses to the gate lines;
The first pixel on the odd-numbered line of the liquid crystal display panel and the second pixel on the even-numbered line share the first data line and the second data line.
Each of the first and second pixels includes a subpixel of a first color into which data of a first color is written, a subpixel of a second color into which data of a second color is written, and a data of a third color into which the first and second pixels are written. Contains 3 subpixels,
After data is written in the subpixels of the first pixel in the order of the data of the first color, the data of the second color, and the data of the third color, the subpixels of the third pixel Data is written in order of data, data of a second color, and data of a first color.
And a column direction length of each of the subpixels is longer than a line direction length of each of the subpixels.
The method according to claim 6,
A data voltage maintaining a first polarity is supplied to the first data line for one frame period,
And a data voltage maintaining a second polarity for the one frame period to the second data line.
The method of claim 7, wherein
The first pixel,
A first TFT supplying a data voltage of the first color from the first data line to a first pixel electrode in response to a first gate pulse from a first gate line;
A second TFT supplying a data voltage of the second color from the second data line to a second pixel electrode in response to a second gate pulse from a second gate line; And
A third TFT supplying a data voltage of the third color from the first data line to a third pixel electrode in response to a third gate pulse from a third gate line,
The second pixel,
A fourth TFT supplying a data voltage of the first color from the second data line to a fourth pixel electrode in response to a sixth gate pulse from a sixth gate line;
A fifth TFT supplying a data voltage of the second color from the first data line to a fifth pixel electrode in response to a fifth gate pulse from a fifth gate line; And
A sixth TFT supplying a data voltage of the third color from the second data line to a sixth pixel electrode in response to a fourth gate pulse from a fourth gate line,
The gate pulses are generated in the order of the first gate pulse, the second gate pulse, the third gate pulse, the fourth gate pulse, the fifth gate pulse, and the sixth gate pulse. Display.
The method of claim 7, wherein
The first pixel,
A first TFT supplying a data voltage of the third color from the second data line to a first pixel electrode in response to a third gate pulse from a third gate line;
A second TFT supplying a data voltage of the second color from the first data line to a second pixel electrode in response to a second gate pulse from a second gate line; And
A third TFT supplying a data voltage of the first color from the second data line to a third pixel electrode in response to a first gate pulse from a first gate line,
The second pixel,
A fourth TFT supplying a data voltage of the third color from the first data line to a fourth pixel electrode in response to a fourth gate pulse from a fourth gate line;
A fifth TFT supplying a data voltage of the second color from the second data line to a fifth pixel electrode in response to a fifth gate pulse from a fifth gate line; And
A sixth TFT supplying a data voltage of the first color from the first data line to a sixth pixel electrode in response to a sixth gate pulse from a sixth gate line,
The gate pulses are generated in the order of the first gate pulse, the second gate pulse, the third gate pulse, the fourth gate pulse, the fifth gate pulse, and the sixth gate pulse. Display.
The method according to claim 6,
Wherein the polarities of the pixels are inverted by one horizontal and one vertical dot inversion.

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