KR20060067291A - Display device - Google Patents

Abstract

The present invention relates to a display device, and more particularly to a liquid crystal display device. The display device may include a plurality of gate lines transferring a pre-charge gate on voltage having a first duration and a normal gate on voltage having a second duration, a plurality of data lines transferring a data voltage, the gate lines, and the data. A plurality of pixels including a switching element connected to a line and operated by the precharge gate on voltage and the normal gate on voltage, and a plurality of pixel electrodes to receive the data voltage by an operation of the switching element, wherein each gate A gate driver connected to a line to sequentially apply the pre-charge gate on voltage and the normal gate on voltage, and a data driver to apply the data voltage to the data line. In this case, the gate driver outputs the pre-charge gate on voltage before outputting the normal gate on voltage. The first duration is different from the second duration. As a result, due to the difference between the pre-charged pixel voltage and the data voltage applied for the main charging, the main charging is normally performed to reduce the overcharging than the target voltage, thereby improving the image quality of the display device.

LCD, LCD, Impulsive, Charging Time, Blank

Description

Display device {DISPLAY DEVICE}

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a waveform diagram of a vertical synchronization signal and a horizontal synchronization signal when an image signal is applied according to an embodiment of the present invention.

4A is a waveform diagram illustrating a voltage change of a pixel that is precharged and charged by a corresponding data voltage when a precharge gate on voltage is shorter than a duration of a normal gate on voltage according to an exemplary embodiment of the present invention.

4B is a waveform diagram illustrating a voltage change of a pixel that is precharged and charged by the data voltage when the duration of the precharge gate on voltage and the normal gate on voltage are the same.

The present invention relates to a display device.

A typical liquid crystal display (LCD) includes two display panels provided with pixel electrodes and common electrodes, and a liquid crystal layer having dielectric anisotropy interposed therebetween. The pixel electrodes are arranged in a matrix and connected to switching elements such as thin film transistors (TFTs) to receive data voltages one by one in sequence. The common electrode is formed over the entire surface of the display panel and receives a common voltage. The pixel electrode, the common electrode, and the liquid crystal layer therebetween form a liquid crystal capacitor, and the liquid crystal capacitor becomes a basic unit that forms a pixel together with a switching element connected thereto.

In such a liquid crystal display, an electric field is generated in the liquid crystal layer by applying a data voltage and a common voltage to the pixel electrode and the common electrode, respectively, and the intensity of the electric field is adjusted to adjust the transmittance of light passing through the liquid crystal layer to obtain a desired image. . In this case, in order to prevent deterioration or flicker caused by an electric field applied to the liquid crystal layer for a long time, the polarity of the data voltage with respect to the common voltage is inverted for each frame, for each row, or for each pixel.

However, when the polarity of the data voltage is inverted as described above, the response speed of the liquid crystal molecules is slow, so that it takes a long time for the liquid crystal capacitor to charge to the target voltage, so that the screen is not clear and blurring occurs. In order to solve this problem, an impulsive driving method for inserting a black screen for a short time has been developed.

Such an impulsive driving method turns off the backlight lamp at a predetermined cycle to make the entire screen black (impulsive emission type) and applies a black data voltage to the pixel at a constant cycle in addition to the normal data voltage that is substantially involved in the display (cyclic resetting type). There is).

However, these methods still do not compensate for the late response speed of the liquid crystal, but also the response speed of the backlight lamp is slow, there is a problem that the image quality is deteriorated due to the afterimage of the screen or flicker occurs. In particular, in the case of applying the black data voltage, the application time of the normal data voltage is shortened, so that the liquid crystal capacitor does not reach the target voltage.

To compensate for this problem, a pre-charging voltage is applied for a predetermined time before the normal data voltage is applied to the liquid crystal capacitor to orient the liquid crystal molecules to some extent in advance. This makes the difference between the current voltage and the target voltage of the liquid crystal capacitor relatively small, so that the target voltage can be reached within a short time.

However, when the difference between the precharged voltage by the precharge voltage and the voltage applied to the precharged pixel is small, the precharged voltage on the pixel is so large that normal charging operation is not performed and an overcharge phenomenon occurs and the image is displayed. There is a poor image quality with shadows such as shadows.

The technical problem to be solved by the present invention is to solve this problem, and to improve the image quality of the display device generated by the pre-charge.

According to an aspect of the present invention, a display device includes a plurality of gate lines and a data voltage transferring a first gate on voltage having a first duration and a second gate on voltage having a second duration. A plurality of data lines transferring the data lines, the switching elements connected to the gate lines and the data lines to be operated by the first gate on voltage and the second gate on voltage, and the data voltage to be applied by the operation of the switching elements. A plurality of pixels including a plurality of receiving pixel electrodes, a gate driver connected to each gate line to sequentially apply the first gate on voltage and the second gate on voltage, and applying the data voltage to the data line A data driver, wherein the gate driver is configured to output the first gate on voltage before outputting the second gate on voltage; Outputting a turn-on voltage, the first duration is different from the second duration.

Preferably, the first duration is shorter than the second duration.

The second duration is preferably 1H.

The display device may further include a signal controller configured to control the gate driver and the data driver, wherein the signal controller starts vertical synchronization to instruct output of the first gate on voltage and the second gate on voltage. It is preferable to supply a signal to the gate driver.

The vertical synchronization start signal may include a first pulse indicating start of output of the first gate on voltage and a second pulse indicating start of output of the second gate on voltage.

In this case, the interval between the first pulse of the vertical synchronization start signal and the second pulse of the vertical synchronization start signal may be 2H.

In addition, the signal controller may apply a plurality of output enable signals that limit the duration of the gate-on voltage to the gate driver.

In this case, the output enable signal may have a first waveform defining the first duration and a second waveform defining the second duration, respectively.

The output enable signal includes a first output enable signal and a (3N-1) th gate defining a duration of the first gate-on voltage and the second gate-on voltage applied to a (3N-2) th gate line. A second output enable signal defining a duration of the first gate on voltage and the second gate on voltage applied to a line, and the first gate on voltage and the second applied to a (3N) th gate line And a third output enable signal that defines the duration of the gate-on voltage, where N = 0, 1, 2,...

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A liquid crystal display according to an exemplary embodiment of the display device according to the present invention will now be described in detail with reference to the accompanying drawings.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver 500 connected thereto. The gray voltage generator 800 connected to the signal generator 500 and a signal controller 600 for controlling the gray voltage generator 800 are included.

The liquid crystal panel assembly 300 includes a plurality of display signal lines G ₁ -G _n , D ₁ -D _m and a plurality of pixels connected to the plurality of display signal lines G ₁ -G _n , D ₁ -D _m in an equivalent circuit, and arranged in a substantially matrix form. In terms of structure, the lower panel 100, the upper panel 200, and the liquid crystal layer 3 therebetween are included.

The display signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n for transmitting a gate signal (also called a scan signal) and a data line D ₁ -for transmitting a data signal. D _m ). The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction, and they are also substantially parallel to each other.

Each pixel includes a switching element Q connected to a display signal line G ₁ -G _n , D ₁ -D _m , and a liquid crystal capacitor C _LC and a storage capacitor C _ST connected thereto. ). The holding capacitor C _ST can be omitted as necessary.

The switching element Q, such as a thin film transistor, is provided in the lower panel 100, and the control terminal and the input terminal are three-terminal elements, respectively, with gate lines G ₁ -G _n and data lines D ₁ -D _m . The output terminal is connected to a liquid crystal capacitor (C _LC ) and a holding capacitor (C _ST ).

The liquid crystal capacitor C _LC has two terminals, the pixel electrode 190 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 190 and 270. It functions as a dielectric. The pixel electrode 190 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives the common voltage Vcom. Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, at least one of the two electrodes 190 and 270 may be linear or rod-shaped.

The storage capacitor C _ST , which serves as an auxiliary part of the liquid crystal capacitor C _LC , is formed by overlapping a separate signal line (not shown) and the pixel electrode 190 provided on the lower panel 100 with an insulator interposed therebetween. A predetermined voltage such as the common voltage Vcom is applied to this separate signal line. However, the storage capacitor C _ST may be formed such that the pixel electrode 190 overlaps the front end gate line directly above the insulator.

On the other hand, to implement color display, each pixel uniquely displays one of the three primary colors (spatial division) or each pixel alternately displays the three primary colors over time (time division) so that the desired color can be selected by the spatial and temporal sum of these three primary colors. To be recognized. 2 shows that each pixel includes a red, green, or blue color filter 230 in a region corresponding to the pixel electrode 190 as an example of spatial division. Unlike FIG. 2, the color filter 230 may be formed above or below the pixel electrode 190 of the lower panel 100.

A polarizer (not shown) for polarizing light is attached to an outer surface of at least one of the two display panels 100 and 200 of the liquid crystal panel assembly 300.

The gray voltage generator 800 generates two sets of gray voltages related to the transmittance of the pixel. One of the two sets has a positive value for the common voltage Vcom and the other set has a negative value.

The gate driver 400 is connected to the gate lines G ₁ -G _n of the liquid crystal panel assembly 300 to gate signals formed of a combination of a gate on voltage Von and a gate off voltage Voff from the outside. It is applied to (G ₁ -G _n ) and may be composed of a plurality of integrated circuits.

The data driver 500 is connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300, selects a gray voltage from the gray voltage generator 800, and applies the gray voltage to the pixel as a data signal. It may be made of.

The plurality of gate driving integrated circuits or data driving integrated circuits may be mounted in a tape carrier package (TCP) (not shown) in the form of a chip to attach the TCP to the liquid crystal panel assembly 300, and may be advantageous without using TCP. These integrated circuit chips may be directly attached onto a substrate (chip on glass, COG mounting method), and a circuit performing the same functions as those integrated circuit chips may be formed directly on the liquid crystal panel assembly 300 together with the thin film transistors of the pixel. It may be.

The signal controller 600 controls operations of the gate driver 400 and the data driver 500.

The display operation of such a liquid crystal display device will now be described in detail.

The signal controller 600 is configured to control the input image signals R, G, and B and their display from an external graphic controller (not shown), for example, a vertical synchronization signal Vsync and a horizontal synchronization signal ( Hsync), main clock (MCLK), data enable signal (DE) is provided. The signal controller 600 properly processes the image signals R, G, and B according to operating conditions of the liquid crystal panel assembly 300 based on the input image signals R, G, and B and the input control signal to control the gate control signals. After generating the CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are transmitted to the data driver 500. Export to

The gate control signal CONT1 includes a vertical synchronization start signal STV indicating the start of output of the gate-on voltage Von, a gate clock signal CPV for controlling the output timing of the gate-on voltage Von, and a gate-on voltage ( And a plurality of output enable signals OE1-OE3 that define the duration of Von).

The data control signal CONT2 is a horizontal synchronous start signal STH indicating the start of transmission of the image data DAT, a load signal LOAD for applying a corresponding data voltage to the data lines D ₁ -D _m , and a common voltage. An inversion signal RVS and a data clock signal HCLK for inverting the polarity of the data voltage with respect to Vcom (hereinafter, referred to as the polarity of the data voltage by reducing the polarity of the data voltage with respect to the common voltage).

The data driver 500 sequentially receives and shifts image data of one row of pixels according to the data control signal CONT2 from the signal controller 600, and displays each image of the gray voltages from the gray voltage generator 800. The image data DAT is converted into a corresponding data voltage by selecting a gray voltage corresponding to the data DAT, and then applied to the data lines D ₁ -D _m .

The gate driver 400 applies the gate-on voltage Von to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n . The switching element Q connected to is turned on, and accordingly, a data voltage applied to the data lines D ₁ -D _m is applied to the corresponding pixel through the turned-on switching element Q.

The difference between the voltage applied to the pixel electrode 190 (hereinafter referred to as the pixel electrode voltage) and the common voltage V _com is shown as the charging voltage of the liquid crystal capacitor C _LC , that is, the pixel voltage. The arrangement of the liquid crystal molecules varies according to the magnitude of the pixel voltage, thereby changing the polarization of light passing through the liquid crystal layer 3. The change in polarization is represented by a change in transmittance of light by a polarizer (not shown) attached to the display panels 100 and 200.

After one horizontal period (or 1H) (one period of the horizontal sync signal H _sync ) passes, the data driver 500 and the gate driver 400 repeat the same operation for the pixels in the next row. In this manner, the gate-on voltages Von are sequentially applied to all the gate lines G ₁ -G _n during one frame to apply data voltages to all the pixels. At the end of one frame, the next frame starts and the state of the inversion signal RVS applied to the data driver 500 is controlled so that the polarity of the data voltage applied to each pixel is opposite to that of the previous frame ("frame inversion). "). In this case, the polarities of the data voltages flowing through one data line may be changed (row inversion and point inversion) or the polarities of the data voltages applied to one pixel row may be different according to the characteristics of the inversion signal RVS within one frame. (Invert columns, invert points).

Next, a driving method of the liquid crystal display according to the exemplary embodiment of the present invention will be described in detail with reference to FIG. 3.

3 is a waveform diagram of various signals used in a liquid crystal display according to an exemplary embodiment of the present invention, and includes a data voltage Vd, a vertical synchronization start signal STV, a gate clock signal CPV, and an output enable signal. (OE1-OE3) and gate signals g ₁ , g ₂ , .., g _n-1 , g _n are shown.

As described above, the signal controller 600 provides the vertical synchronization start signal STV, the output enable signals OE1-OE3 and the gate clock signal CPV to the gate driver 400 to perform scanning. The inversion scheme of the data voltage Vd is, for example, one dot inversion or line inversion.

In FIG. 3, the gate on voltage Von includes one precharge gate on voltage Von1 and one normal gate on voltage Von2, and the pulse width of the precharge gate on voltage Von1 is normal gate on. It is smaller than the pulse width of the voltage Von2.

The pre-charge gate-on voltage Von1 has its pulse width determined according to the voltage charged to the corresponding pixel through the switching element Q turned on by the voltage Von1. As described above, the normal gate-on voltage Von2 is determined. Is not greater than the pulse width.

When the precharge gate on voltage Von1 and the normal gate on voltage Von2 are output, the polarities of the data voltages applied to the pixel electrode 190 should be the same. Therefore, the interval between the pre-charge gate on voltage Von1 and the normal gate on voltage Von2 is equal to an even number of horizontal periods or gate lines.

The vertical synchronization start signal STV is a pulse for a precharge gate on voltage P1 for outputting a precharge gate on voltage Von1 and a pulse for a normal gate on voltage P2 for outputting a normal gate on voltage Von2. ). The generation interval of the precharge gate on voltage pulse P1 and the normal gate on voltage pulse P2 is equal to the output interval of the precharge gate on voltage Von1 and the normal gate on voltage Von2.

The magnitude of the pulse P1 for the pre-charge gate on voltage and the magnitude of the pulse P2 for the normal gate on voltage are the same, but may not be the same.

The three output enable signals OE1-OE3 are provided to the gate driver 400 by the signal controller 600 and transferred through the corresponding gate lines G ₁ -G _n to gate-on voltages Von1 and Von2. It serves to limit the duration of the pulse, i.e. the pulse width. In the present invention, the first output enable signal OE1 is the gate-on voltage Von1, which is applied to the (3N-2) th gate line G ₁ , G ₄ , G ₇ , G ₁₀ , G ₁₃ ,... And the second output enable signal OE2 is applied to the (3N-1) th gate line G ₂ , G ₅ , G ₈ , G ₁₁ , G ₁₄ , ... and a gate-on limiting the duration of the voltage (Von1, Von2), the third output enable signal (OE3) is (3N) th gate lines _{(G 3, G 6, G} 9, G 12, G 15, ... Limit the duration of the gate-on voltages Von1, Von2 that are applied (where N = 1, 2, 3, ...).

Each output enable signal OE1-OE3 has two waveforms, a precharge waveform I and a normal charge waveform II, and the waveform changes at an appropriate time under the control of the signal controller 600.

In FIG. 3, when the output enable signals OE1 to OE3 have a high value, the output of the gate on voltage Von is suppressed, and the gate off voltage Voff is output. When the output enable signals OE1 to OE3 have a high value, the gate on voltage Von is output. . The ratio between the high section and the low section of the output enable signals OE1-OE3 can be adjusted as needed in consideration of the ratio between the time for precharging and the time for normal charging. It may be.

The operation of precharging will then be described in more detail.

First, the signal controller 600 generates the precharge gate-on voltage pulse P1 in the vertical synchronization start signal STV applied to the gate driver 400, and then, after a predetermined time elapses, the signal controller 600 generates the pulse clock signal CPV. Generate a pulse.

When a pulse is transmitted to the gate clock signal CPV transmitted from the signal controller 600, the gate driver 400 sequentially outputs the pre-charge gate-on voltage Von1 from the first gate line G ₁ . In this case, as illustrated in FIGS. 3D to 3F, the first to third output enable signals OE1 to OE3 are applied to the gate driver 400. In this case, the waveform of the output enable signals OE1-OE3 applied to the gate driver 400 by the signal controller 600 is a precharge waveform I, and the precharge waveform I corresponds to the 1H interval. Generated on Output Enable Signals OE2 and OE3

By this output enable signal OE1-OE3, as previously described, the dictionary is applied to the (3N-2) th gate line G ₁ , G ₄ , G ₇ , G ₁₀ , G _13, ... The charge gate-on voltage Von1 has its pulse width determined by the first output enable signal OE1, and the (3N-1) th gate lines G ₂ , G ₅ , G ₈ , G ₁₁ , G ₁₄ , pre-charge the gate-on voltage (Von1) is applied to) is up two is determined that the pulse width by a second output enable signal (OE2), (3N) th gate lines _{(G 3, G 6, G} 9, The precharge gate-on voltage Von1 applied to G ₁₂ , G ₁₅ ,... Is pulse width determined by a third output enable signal OE3.

As such, when the pre-charge gate-on voltage Von1 having the pulse width determined by the waveform of the output enable signals OE1-OE3 is sequentially output from the first gate line G ₁ , the first gate line ( The pixel electrode 190 sequentially connected to the gate line from G ₁ ) is sequentially charged with the data voltage Vd transmitted through the data lines D ₁ -D _m , and is precharged in the pixel.

After the pre-charge gate-on voltage Von1 is output to the second gate line G ₂ and before the pre-charge gate-on voltage Von1 is output to the third gate line G ₃ , the signal controller 600 may include a gate. After generating a pulse P2 for the normal gate-on voltage to the vertical synchronization start signal STV applied to the driver 400, a predetermined time elapses, and generates a pulse to the gate clock signal CPV. At this time, as shown in (d) to (f) of FIG. 3, the waveform of the first output enable signal OE1 is changed to the normal charging waveform II, and the second and third output enable signals ( The waveforms of OE2 and OE3 also have the normal charging waveform II at intervals of 1H.

The gate driver 400 receiving the vertical synchronizing signal STV and the gate clock signal CPV sequentially starts from the gate line G ₁ connected to its first output terminal according to the output enable signals OE1-OE3. The gate-on voltage Von2 having a predetermined pulse width, for example, a duration of 1H, is output.

In this case, as described above, since the first output enable signal OE1 has the normal charging waveform II, while the third output enable signal OE3 has the precharging waveform I, The gate-on voltage Von output through the first gate line G ₁ is the normal gate-on voltage Von2 and the gate-on voltage Von output through the third gate line G ₃ is the precharge gate on. Voltage Von1. In addition, the first and third output enable signals OE1 and OE3 allow the normal gate-on voltage Von2 to have a duration of 1H, while the pre-charge gate-on voltage Von1 has a duration shorter than 1H. .

As such, the interval between the pre-charge gate on voltage pulse P1 and the normal gate on voltage pulse P2 is two horizontal periods, so that the gate on voltages Von1 and Von2 are connected to a pair of next nearest gate lines. This is applied at the same time. That is, the gate-on voltages Von1 and Von2 are in the order of the first gate line G ₁ , the third gate line G ₃ , the second gate line G ₂ , and the fourth gate line G ₄ . Is approved. At this time, the pixels connected to the front gate line of each pair of gate lines perform main charging to charge their data voltages, and the pixels connected to the rear gate lines of the pixels in rows other than their own data voltages. There is a precharge to charge the data voltage. As already explained, the pre-charge time is longer than the present charge time by the output enable signals OE1-OE3.

Pixels connected in sequence from the third gate line G ₃ are precharged with the data voltage Vd applied for main charging before 2H or before two gate lines, but the first gate line G ₁ and the second The gate line G ₂ is precharged with a data voltage Vd corresponding to arbitrary image data DAT transmitted to the data driver 500 through the signal controller 600. The arbitrary image data DAT may be image data having a predetermined gray scale value such as black image data, white image data, or an intermediate gray scale value, and these gate lines G ₁ and G _{2 as necessary} . The image data DAT pre-charged may be changed.

Through this operation, the pre-charge gate-on voltage Von1 and the normal gate-on voltage Von2 are sequentially applied from the first gate line G ₁ to the last gate line G _n , thereby performing precharge and main charge in this order. .

As described above, the voltage change charged in the pixel when the precharge and the main charge are performed will be described with reference to FIGS. 4A and 4B.

4A illustrates a voltage change of a pixel that is precharged and charged by a corresponding data voltage when the precharge gate on voltage Von1 is shorter than the duration of the normal gate on voltage Von2 according to an embodiment of the present invention. 4B is a waveform diagram illustrating a voltage change of a pixel that is precharged and charged by a corresponding data voltage when the durations of the precharge gate-on voltage Von1 and the normal gate-on voltage Von2 are the same. to be.

As shown in FIG. 4A, since the precharge time determined by the precharge gate-on voltage Von1 is shorter than the present charge time, the pixel voltage Vpixel gradually decreases due to the data voltage Vd applied during the precharge period. After increasing, it can be seen that the battery is normally charged to the target voltage by the data voltage Vd applied during the charging period.

In contrast, as shown in FIG. 4B, when the precharge gate on voltage Von1 and the normal gate on voltage Von2 have the same pulse width, the precharge time and the main charge time are the same, and during the precharge period. It can be seen that the pixel voltage Vpixel is charged to the target voltage by the applied data voltage Vd and eventually overcharges beyond the target voltage during the main charging.

Since the pre-charging is performed for a time shorter than the main charging time according to the present invention, the main charging is normally performed due to the difference between the pre-charged pixel voltage and the data voltage applied for the main charging. As a result, the phenomenon of overcharging than the target voltage is reduced, and the image quality of the display device is improved.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (9)

A plurality of gate lines transferring a first gate on voltage having a first duration and a second gate on voltage having a second duration, A plurality of data lines for transferring data voltages, A switching element connected to the gate line and the data line and operated by the first gate on voltage and the second gate on voltage, and a plurality of pixel electrodes to receive the data voltage by an operation of the switching element. A plurality of pixels, A gate driver connected to each of the gate lines to sequentially apply the first gate on voltage and the second gate on voltage, and A data driver for applying the data voltage to the data line Including, The gate driver outputs the first gate on voltage before outputting the second gate on voltage, The first duration is different from the second duration Display device. In claim 1, And the first duration is shorter than the second duration. In claim 2, And the second duration is 1H. In claim 1, A signal controller for controlling the gate driver and the data driver More, And the signal controller supplies a vertical synchronization start signal to the gate driver to indicate the start of output of the first gate on voltage and the second gate on voltage. In claim 4, The vertical synchronization start signal may include a first pulse indicating start of output of the first gate on voltage and a second pulse indicating start of output of the second gate on voltage. In claim 5, And the interval between the first pulse of the vertical synchronization start signal and the second pulse of the vertical synchronization start signal is 2H. In claim 4, The signal controller applies a plurality of output enable signals for limiting the duration of the gate-on voltage to the gate driver. In claim 7, And each of the output enable signals has a first waveform defining the first duration and a second waveform defining the second duration. In claim 8, The output enable signal,  A first output enable signal defining a duration of the first gate on voltage and the second gate on voltage applied to a (3N-2) th gate line, A second output enable signal defining a duration of the first gate on voltage and the second gate on voltage applied to a (3N-1) th gate line, and  And a third output enable signal defining a duration of the first gate on voltage and the second gate on voltage applied to a (3N) th gate line. Where N = 1, 2, 3, ...

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