KR20080017990A - Liquid crystal display and driving method thereof - Google Patents

Abstract

A liquid crystal display device and a driving method thereof are provided to improve image quality of the LCD device by enhancing a charging ratio of a data voltage by performing preliminary and main charging processes. An LCD(Liquid Crystal Display) panel(300) includes RGB pixels, gate lines, and data lines. The gate lines are connected to the pixels in a first direction, while the data lines are connected to the pixel in a second direction. A timing controller(600) includes a vertical synchronization start signal generator and a vertical synchronization start signal regulator. The vertical synchronization start signal generator supplies a first vertical synchronization start signal. The vertical synchronization start signal regulator receives the first vertical synchronization start signal and first and second gate clock signals and adjusts the first vertical synchronization start signal, so that rising edges of the first and second gate clock signals are overlapped with an activation period of the first vertical synchronization start signal, at a start timing of an N-th horizontal period. Gate drivers(400L,400R) receive a second vertical synchronization start signal and the first and second clock signals and sequentially outputs gate signals having first and second gate-on voltages. The first gate-on voltage is used to perform a preliminary charging process during the N-th horizontal period. The second gate-on voltage is used to perform a main charging process during an N+1-th horizontal period.

Description

Liquid crystal display and driving method thereof

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is a diagram illustrating pixels arranged in a matrix form according to an embodiment of the present invention.

3 is an internal block diagram of a timing controller according to an embodiment of the present invention.

4 is a diagram illustrating a gate driver according to an exemplary embodiment of the present invention.

5 is a waveform diagram illustrating a signal of a liquid crystal display according to an exemplary embodiment of the present invention over time.

6 is a diagram illustrating pixels arranged in a matrix form according to another exemplary embodiment of the present invention.

7 is a waveform diagram illustrating a signal of a liquid crystal display according to another exemplary embodiment of the present invention over time.

(Explanation of symbols for the main parts of the drawing)

300: liquid crystal panel 400L, 400R: gate driver

500: data driver 600: timing controller

610: vertical synchronization start signal providing unit 620: vertical synchronization start signal adjusting unit

700: voltage generator 800: gray voltage generator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a driving method thereof, and more particularly, to a liquid crystal display device and a driving method thereof capable of improving the charging rate of a data voltage.

In general, a liquid crystal display (Liquid Crystal Display) is a flat panel display device that displays an image using a liquid crystal (Liquid Crystal), is thinner and lighter than other display devices, has the advantage of low power consumption and low driving voltage There is this.

In the liquid crystal display (LCD), a liquid crystal layer is interposed between a color filter display panel on which a reference electrode and a color filter are formed, and a thin film transistor substrate on which a switching element and a pixel electrode are formed. By applying different potentials to the pixel electrode and the reference electrode, an electric field is formed to change the arrangement of the liquid crystal molecules, and thereby, the image is represented by adjusting the light transmittance.

In the liquid crystal display, a timing control unit that receives color signals or color data from a color signal source (for example, a computer or a TV) outputs a gate signal to a gate driver at a predetermined timing when supplying image data to each pixel electrode. The image data is output to the data driver. The gate driver sequentially turns on a switching element connected to the gate line by applying a gate-on voltage corresponding to a high period of the gate signal to the gate line, and at the same time, the data driving unit turns a color on the pixel row where the turned-on switching element is located. The data voltage corresponding to the data is supplied to the corresponding data line. The data voltage supplied to the data line is applied to the corresponding pixel through the turned-on switching element. In this way, image data is applied to all the pixel rows by applying the gate-on voltage to all the gate lines in turn for one frame.

Recently, in order to reduce the number of data drivers, R, G, and B pixels are arranged in the vertical direction. When the R, G, and B pixels are arranged in the vertical direction, the number of data lines is reduced by 1/3 while the gate lines are increased by three times, thereby reducing the charging time of each gate line by 1/3. In order to solve this problem, gate driving circuits are disposed on both sides of the liquid crystal panel to lower the gate driving frequency, and the data driver precharges the next pixel with the data voltage of the current pixel when charging the data voltage to the current pixel. Was used.

In this method, the delay of the gate signal applied to the gate line increases from the beginning to the end of the gate line, causing the signal to be distorted. As a result, a gate line where a signal distortion occurs and a gate line that does not occur appear to generate a horizontal line. do. In addition, the charging time of the gate line is reduced to one third, which causes severe charging failure in the monochrome surface.

An object of the present invention is to provide a liquid crystal display device capable of improving the charging rate of a data voltage.

An object of the present invention is to provide a method of driving a liquid crystal display device capable of improving the charging rate of a data voltage.

The technical problems of the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

A liquid crystal display according to an exemplary embodiment of the present invention for achieving the technical problem is a liquid crystal panel in which R, G, and B pixels are arranged in a matrix form, and pixels having the same color in a first direction of the matrix are provided. And a plurality of R, G, and B pixels repeatedly arranged in a second direction, a gate line connected to pixels in the first direction, and a data line connected to pixels in the second direction. And a vertical synchronization start signal providing unit for providing a first vertical synchronization start signal, and a switching device in a first direction connected to the gate line by receiving the first vertical synchronization start signal and the first and second gate clock signals. At the start of the N (where N is a natural number) horizontal period, the rising edges of the first and second gate clock signals overlap with the activation period of the first vertical synchronization start signal. A timing controller including a vertical synchronization start signal adjusting unit configured to adjust the first vertical synchronization start signal and output the second vertical synchronization start signal, and receive the second vertical synchronization start signal and the first and second gate clock signals, Sequentially outputting a gate signal having a first gate on voltage preliminarily charged for the predetermined horizontal period in the N horizontal period and a second gate on voltage for main charging for a predetermined horizontal period in the N + 1 horizontal period It includes a gate driver.

According to an aspect of the present invention, there is provided a method of driving a liquid crystal display, the method comprising: providing a first vertical synchronization start signal, the first vertical synchronization start signal, and first and second gate clocks; A rising edge of the first and second gate clock signals at a start point of N (where N is a natural number) horizontal period indicating a time at which the switching element in the first direction connected to the gate line is turned on upon receiving a signal; Adjusting and providing the first vertical synchronization start signal as a second vertical synchronization start signal such that an activation period of the first vertical synchronization start signal overlaps, the second vertical synchronization start signal and the first and second gate clocks; A first gate-on voltage which is precharged for a predetermined horizontal period in the N horizontal period, and a main charge for a predetermined horizontal period in the N + 1 horizontal period Providing a gate signal having a second gate-on voltage, and applying the gate signal to the second gate-on voltage after a predetermined time after the first gate-on voltage is applied to the gate line. And applying a data voltage to a corresponding pixel.

Specific details of other embodiments are included in the detailed description and the drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be embodied in various different forms, and the present embodiments are merely common knowledge in the technical field to which the present disclosure is completed and to which the present invention pertains. It is provided to fully inform the person having the scope of the invention, the invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, with reference to the accompanying drawings will be described embodiments of the present invention;

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, in the liquid crystal display according to the exemplary embodiment, a gray scale connected to the liquid crystal panel 300 and the gate drivers 400L and 400R, the data driver 500, and the data driver 500 connected thereto. The voltage generator 800 includes a timing controller 600 and a voltage generator 700 for controlling the voltage generator 800.

The liquid crystal panel 300 is connected to a plurality of display signal lines G1-Gn and D1 -Dm as an equivalent circuit, and includes a plurality of unit pixels Px arranged in a matrix form.

Here, the display signal lines G1-Gn and D1-Dm include a plurality of gate lines G1-Gn transferring gate signals and data lines D1-Dm transferring data signals. The gate lines G1-Gn extend in the row direction and are substantially parallel to each other, and the data lines D1-Dm extend in the column direction and are substantially parallel to each other.

Although not shown, each unit pixel Px includes a switching element connected to the display signal lines G1-Gn and D1-Dm, a liquid crystal capacitor, and a storage capacitor connected thereto. The holding capacitor can be omitted as needed.

The switching element is provided in the first display panel (not shown), and the control terminal and the input terminal thereof are connected to the gate lines G1-Gn and the data lines D1-Dm, respectively, and the output terminal is It is connected to the liquid crystal capacitor and the holding capacitor.

The liquid crystal capacitor uses the pixel electrode of the first display panel and the common electrode of the second display panel (not shown) as two terminals, and the liquid crystal layer between the two electrodes functions as a dielectric. The pixel electrode is connected to the switching element, and the common electrode is formed on the front surface of the second display panel and receives the common voltage Vcom. In addition, a common electrode may be provided in the first display panel, and both electrodes may be made in a linear or bar shape.

The storage capacitor is formed by overlapping a separate signal line (not shown) and a pixel electrode included in the first display panel, and a predetermined voltage such as a common voltage Vcom is applied to the separate signal line (independent wiring method). However, the sustain capacitor may be formed such that the pixel electrode overlaps the front end gate line directly above the insulator (shear gate method).

On the other hand, in order to implement color display, each unit pixel should be able to display color, which is possible by providing a red, green, or blue color filter in a region corresponding to the pixel electrode. In addition, although the color filter is formed in a corresponding region of the second display panel, the color filter may be formed above or below the pixel electrode of the first display panel.

A polarizer (not shown) for polarizing light is attached to an outer surface of at least one of the first display panel and the second display panel of the liquid crystal panel 300.

The gray voltage generator 800 may generate two sets of gray voltages related to transmittance of a unit pixel. That is, one of the two sets is the positive voltage, and the other is the negative voltage. The positive voltage and the negative voltage mean voltages whose polarities of the data voltages are opposite to the common voltage Vcom, and are alternately provided to the liquid crystal panel during inversion driving.

The gate drivers 400L and 400R are disposed on the left and right sides of the liquid crystal panel 300 and are connected to the respective gate lines G1 -Gn, and a combination of the gate on voltage Von and the gate off voltage Voff is provided. The first and second gate clock signals CPV1 and CPV2 may be applied to the gate lines G1 to Gn.

The data driver 500 is connected to the data lines D1-Dm of the liquid crystal panel 300, generates a plurality of gray voltages based on voltages provided from the gray voltage generator 800, and generates the generated gray voltages. It is selected and applied to a unit pixel as a data signal, and is usually composed of a plurality of integrated circuits.

The timing controller 600 generates control signals for controlling operations of the gate drivers 400L and 400R and the data driver 500, and transmits corresponding control signals to the gate drivers 400L and 400R and the data driver 500. To provide. In addition, the timing controller 600 adjusts the first vertical synchronization start signal STV1 generated therein to output the second vertical synchronization start signal STV2 to improve the charging rate of the data voltage in the pixel. The adjusting unit 620 is included. Detailed description thereof will be described with reference to FIG. 2.

The voltage generator 700 generates a plurality of driving voltages. For example, the first and second gate clock signals CPV1 and CPV2 and the common voltage Vcom formed by a combination of the gate on voltage Von and the gate off voltage Voff are generated. Here, the first and second gate clock signals CPV1 and CPV2 are gate-on voltages Von at high levels to drive the switching elements, and gate-off voltages Voff at low levels. do.

Hereinafter, the display operation of the liquid crystal display will be described in more detail.

The timing controller 600 controls an RGB image signal R, G, and B and an input control signal, for example, a vertical sync signal Vsync and a horizontal sync signal, from an external graphic controller (not shown). Hsync), main clock MCLK, and data enable signal DE are provided. The timing controller 600 generates a gate control signal CONT1, a data control signal CONT2, and the like based on the input control signal and appropriately adjusts the image signals R, G, and B according to the operating conditions of the liquid crystal panel 300. After processing, the gate control signal CONT1 is provided to the gate drivers 400L and 400R, and the data control signal CONT2 and the processed image signals R ', G', and B 'are provided to the data driver 500. do.

The gate control signal CONT1 may include the vertical synchronization start signal STV2 indicating the start of the output of the gate-on voltage Von, the output enable signal OE defining the width of the gate-on voltage Von, and the like. Include.

The data control signal CONT2 is a data load for applying a corresponding data voltage to the horizontal synchronization start signal STH indicating the start of input of the image data R ', G', and B 'and the data lines D1-Dm. Signal (TP), inverted signal (RVS) and data clock to invert the polarity of the data voltage relative to the common voltage (Vcom) (hereinafter referred to as 'polarity of the data voltage by reducing the polarity of the data voltage for the common voltage') Signal HCLK and the like.

The data driver 500 sequentially receives the image data R ′, G ′, and B ′ corresponding to one row of unit pixels according to the data control signal CONT2 from the timing controller 600. By selecting the gray scale voltages corresponding to the image data R ', G', and B ', the image data R', G ', and B' are converted into the corresponding data voltages.

The gate drivers 400L and 400R apply the gate-on voltage Von to the gate lines G1-Gn according to the gate control signal CONT1 to turn on the switching elements connected to the gate lines G1-Gn.

While the gate-on voltage Von is applied to one gate line G1-Gn, and a row of switching elements connected thereto is turned on (this period is referred to as '1H' or '1 horizontal period'). ], The data driver 500 supplies each data voltage to the corresponding data lines D1-Dm. The data voltage supplied to the data lines D1-Dm is applied to the corresponding unit pixel through the turned-on switching element.

The liquid crystal molecules change their arrangement according to the electric field generated by the pixel electrode and the common electrode, and thus the polarization of light passing through the liquid crystal layer changes. This change in polarization is represented by a change in transmittance of light by a polarizer (not shown) attached to the first display panel and the second display panel.

In this manner, the gate-on voltages Von are sequentially applied to all the gate lines G1 -Gn during one frame to apply data voltages to all the unit pixels. When one frame ends, the next frame starts and the state of the inversion signal RVS applied to the data driver 500 is controlled so that the polarity of the data voltage applied to each unit pixel is opposite to that of the previous frame ('frame' reversal'). In this case, the polarity of the data voltage flowing through one data line may be changed ('line inversion') or the polarity of the data voltage applied to one pixel row may be different according to the characteristics of the inversion signal RVS within one frame ( 'Dot reversal').

2 is a diagram illustrating pixels arranged in a matrix form according to an embodiment of the present invention.

Referring to FIG. 2, the pixels 310 of the liquid crystal panel 300 according to the exemplary embodiment of the present invention are arranged in a matrix form, and R pixels having the same color are arranged in the first direction of the matrix. R, G, and B pixels are repeatedly arranged in two directions. In this case, the gate lines G1 to G9 are connected to the pixels in the first direction, and the data lines D1 to D7 are connected to the pixels in the second direction. In this case, the first direction and the second direction represent a row direction and a column direction, respectively.

3 is an internal block diagram of a timing controller according to an embodiment of the present invention.

Referring to FIG. 3, the timing controller 600 includes a vertical synchronization start signal providing unit 610 and a vertical synchronization start signal adjusting unit 620.

The vertical synchronization start signal providing unit 610 generates a vertical synchronization start signal STV1 based on an input control signal provided from an external graphic controller. The vertical synchronization start signal STV1 is a gate control signal and indicates the start of output of the gate-on voltage Von section.

The vertical synchronization start signal controller 620 receives the first vertical synchronization start signal STV1 and the first and second gate clock signals CPV1 and CPV2 so that the switching element of the first direction connected to the gate line is turned on. Activation of the rising edges of the first and second gate clock signals CPV1 and CPV2 and the first vertical synchronization start signal STV1 at the start of the N (where N is a natural number) horizontal period representing time. The first vertical synchronization start signal STV1 is adjusted so as to overlap the sections and output as the second vertical synchronization start signal CPV2. Here, the first direction represents the row direction.

4 is a diagram illustrating a gate driver according to an exemplary embodiment of the present invention. Here, the gate driver 400L will be described for convenience of description.

Referring to FIG. 4, the gate driver 400L according to an exemplary embodiment of the present invention may include the second vertical synchronization start signal STV2, the first and second gate clock signals CPV1 required for gate control from the timing controller 600. CPV2, a data load signal TP and an output enable signal OE are provided.

Then, the gate driver 400L may be configured to precharge the first gate-on voltage Von1 for a predetermined horizontal period from the N horizontal period to the N + 1 horizontal level according to the second vertical synchronization start signal STV2. In the cycle, the gate signals Gate1, Gate2, Gate3, ... that have the second gate-on voltage Von2 that is main-charged for a predetermined horizontal period are sequentially output. In this case, the first gate-on voltage Von1 preliminarily charges the pixel with the same color data voltage, and the second gate-on voltage Von2 has the same color data as the pixel row having the same color. The voltage is charged to the pixel.

5 is a waveform diagram illustrating a signal of a liquid crystal display according to an exemplary embodiment of the present invention over time.

As shown in FIG. 5, the gate driver 400L generates gate signals Gate1, Gate2, Gate3,... According to the second vertical synchronization start signal STV2 provided from the timing controller.

The gate signals Gate1, Gate2, Gate3, ... generated by the gate driver 400L are applied to the gate line, and turn on the switching element connected to the gate lines G1-Gn. Accordingly, the pixels connected to the gate line receive the corresponding data voltages R_Dummy, G_Dummy, B_Dummy, R1, G1, B1 ... in order from the data driver in accordance with the data load signal TP provided from the timing controller 600. Will charge.

Here, the timing at which the gate driver 400L applies the first gate on voltage Von1 and the market time at which the second gate on voltage Von2 is applied differ by 2/3 horizontal periods. Therefore, as shown in FIG. 2, when the target data voltage R1 is mainly charged to the R pixel connected to the gate line G4 during the 1/3 horizontal period A, which is its charging time, the gate line G1 is charged. The data voltage R_Dummy is precharged in the same R pixel connected during the third horizontal period B, which is its charging time. Similarly, when the target data voltage G1 is charged to the G pixel connected to the gate line G5 during its charging time, the data voltage G_Dummy is applied to the same G pixel connected to the gate line G2 during its charging time. This is precharged. That is, pixel rows having the same color are charged with pixel data voltages of the same color.

6 is a diagram illustrating pixels arranged in a matrix form according to another exemplary embodiment of the present invention.

Referring to FIG. 6, the pixels 310 of the liquid crystal panel 300 according to the exemplary embodiment of the present invention are arranged in a matrix form, and R pixels having the same color are arranged in the first direction of the matrix. R, G, and B pixels are repeatedly arranged in two directions. In this case, the gate lines G1 to G9 are connected to the pixels in the first direction, and the data lines D1 to D7 are disposed on both sides of the R, G, and B pixels arranged in the second direction. And the second data line D2 are disposed. One of the pixels neighboring in the second direction is connected to the first data line D1 and the other is connected to the second data line D2. In this case, the first direction and the second direction represent a row direction and a column direction, respectively.

As shown in FIG. 4, the gate driver 400L according to another exemplary embodiment of the present invention includes the second vertical synchronization start signal STV2, the first and second gate clock signals CPV1 required for gate control from the timing controller 600. CPV2, a data load signal TP and an output enable signal OE are provided.

Then, the gate driver 400L and the first gate-on voltage Von1 precharged for a predetermined horizontal period from the N horizontal period according to the second vertical synchronization start signal STV2 and 2N + 1 horizontal In the cycle, the gate signals Gate1, Gate2, Gate3, ... that have the second gate-on voltage Von2 that is main-charged for a predetermined horizontal period are sequentially output. In this case, the first gate-on voltage Von1 preliminarily charges the pixel with the same color data voltage, and the second gate-on voltage Von2 has the same color data as the pixel row having the same color. The voltage is charged to the pixel.

7 is a waveform diagram illustrating a signal of a liquid crystal display according to another exemplary embodiment of the present invention over time.

As illustrated in FIG. 7, the gate driver 400L generates gate signals Gate1, Gate2, Gate3,... According to the second vertical synchronization start signal STV2 provided from the timing controller 600.

The gate signals Gate1, Gate2, Gate3, ... generated by the gate driver 400L are applied to the gate line, and turn on the switching element connected to the gate lines G1-Gn. Accordingly, the pixels connected to the gate line receive the corresponding data voltages R_Dummy1, G_Dummy1, B_Dummy1, R_Dummy2, G_Dummy2, B_Dummy2, R1, G1, B1 ... in accordance with the data load signal TP provided from the timing controller 600. In turn, it is charged from the data driver.

Here, the timing at which the gate driver 400L applies the first gate on voltage Von1 and the market price at which the second gate on voltage Von2 is applied differ by 5/3 horizontal periods. Therefore, as shown in FIG. 6, when the target data voltage R1 is charged in the R pixel connected to the gate line G7 during the 1/3 horizontal period A, which is its charging time, the gate line G1 is charged. The data voltage R_Dummy1 is precharged in the same R pixel connected during the third horizontal period B, which is its charging time. Similarly, when the target data voltage G1 is charged to the G pixel connected to the gate line G8 during its charging time, the data voltage G_Dummy1 is applied to the same G pixel connected to the gate line G2 during its charging time. This is precharged.

According to the present invention, the charge rate of the data voltage charged in the pixel may be improved by preliminary charging and main charging of the pixel rows having the same color with the pixel data voltage having the same color.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, the embodiments described above are to be understood in all respects as illustrative and not restrictive.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the liquid crystal display according to the present invention and the driving method thereof according to the present invention as described above are provided with a vertical synchronization start signal control unit and have the same color row. The precharge and the main charge may be performed using the pixel data voltage of the same color to improve the charging rate of the data voltage charged in the pixel. For this reason, the image quality of a liquid crystal display device can be improved.

Claims (18)

A liquid crystal panel in which R, G, and B pixels are arranged in a matrix, in which pixels having the same color are arranged in a first direction of the matrix, and the R, G, and B pixels are repeatedly arranged in a second direction. A liquid crystal panel having a gate line connected to pixels in the first direction and a data line connected to pixels in the second direction; A vertical synchronization start signal providing unit for providing a first vertical synchronization start signal, and a switching element in a first direction connected to the gate line by receiving the first vertical synchronization start signal and the first and second gate clock signals, and being turned on At the start of a horizontal period of N (where N is a natural number), the first vertical sync such that the rising edges of the first and second gate clock signals overlap with the activation period of the first vertical sync start signal. A timing controller including a vertical synchronization start signal adjusting unit configured to adjust a start signal and output the second vertical synchronization start signal as a second vertical synchronization start signal; And A first gate-on voltage supplied with the second vertical synchronization start signal and first and second gate clock signals to precharge a predetermined horizontal period in the N horizontal period, and a predetermined horizontal period in the N + 1 horizontal period And a gate driver for sequentially outputting a gate signal having a second gate-on voltage for main charging. The method of claim 1, The gate driver is disposed on both sides of the liquid crystal panel. The method of claim 1, The first and second gate-on voltages are configured to charge a pixel with a data voltage having the same color. The method of claim 1, The second gate on voltage is applied after the first gate on voltage is applied and 2/3 horizontal period passes. The method of claim 1, The first and second gate on voltages are each one-third horizontal period. The method of claim 1, First and second data lines are disposed on both sides of the R, G, and B pixels arranged in the second direction, one of the pixels neighboring in the second direction is connected to the first data line, and the other is the second data line. Liquid crystal display connected with line. The method of claim 6, The gate driver, A first gate-on voltage supplied with the second vertical synchronization start signal and first and second gate clock signals to precharge a predetermined horizontal period in the N horizontal period, and a predetermined horizontal period in a 2N + 1 horizontal period A liquid crystal display for sequentially outputting a gate signal having a second gate-on voltage for main charging. The method of claim 7, wherein The first and second gate-on voltages are configured to charge a pixel with a data voltage corresponding to the same color. The method of claim 7, wherein The second gate on voltage is applied after the first gate on voltage is applied and 5/3 horizontal period passes. The method of claim 7, wherein The first and second gate on voltages are each one-third horizontal period. Providing a first vertical synchronization start signal; Start of the N (where N is a natural number) horizontal period indicating the time when the first vertical synchronization start signal and the first and second gate clock signals are turned on in a first direction switching element connected to the gate line. At this point, adjusting the first vertical synchronization start signal to provide a second vertical synchronization start signal such that the rising edges of the first and second gate clock signals overlap with the activation period of the first vertical synchronization start signal. ; A first gate-on voltage supplied with the second vertical synchronization start signal and the first and second gate clock signals and precharged for a predetermined horizontal period in the N horizontal period, and a predetermined horizontal in the N + 1 horizontal period; Providing a gate signal having a second gate on voltage for main charge during the period; Applying the gate signal to the gate line such that the second gate on voltage is applied after a predetermined time after the first gate on voltage is applied to the gate line; And A method of driving a liquid crystal display device comprising applying a data voltage to a corresponding pixel. The method of claim 11, And a data voltage corresponding to the same color as the first and second gate-on voltages in the pixel. The method of claim 11, And the predetermined time is 2/3 horizontal periods. The method of claim 11, And the first and second gate-on voltages are 1/3 horizontal periods, respectively. The method of claim 11, Providing the gate signal, Providing a gate signal having a first gate-on voltage preliminarily charged for a predetermined horizontal period in the N horizontal period and a second gate-on voltage for main charging for a predetermined horizontal period in a 2N + 1 horizontal period; The driving method of the liquid crystal display device. The method of claim 15, And a data voltage corresponding to the same color as the first and second gate-on voltages in the pixel. The method of claim 15, And the predetermined time is 5/3 horizontal period. The method of claim 15, And the first and second gate-on voltages are 1/3 horizontal periods, respectively.

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