KR101294848B1 - Liquid crystal display - Google Patents

Abstract

The present invention relates to a liquid crystal display device, comprising: a first gate integrated circuit configured to output scan signals to gate lines formed in a first area of the liquid crystal panel in response to a first gate enable signal input through a first signal line ; A second gate integrated circuit configured to output a scan signal to gate lines formed in a second region of the liquid crystal panel in response to a second gate enable signal input through a second signal line longer than the first signal line; And a timing controller generating the first and second gate enable signals to control the gate integrated circuits. The pulse width of the second gate enable signal is smaller than the pulse width of the first gate enable signal.

Liquid Crystal Display, Gate Enable Signal, Horizontal Line, Luminance

Description

[0001] Liquid crystal display [0002]

1 is a configuration diagram of a liquid crystal display according to the prior art.

2A and 2B are waveform diagrams illustrating a process of generating a scan signal in the gate driver of FIG. 1.

3 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

4A and 4B are waveform diagrams illustrating a process of compensating a charging time by controlling a pulse width of a gate enable signal.

5 is a configuration diagram of a liquid crystal display according to another exemplary embodiment of the present invention.

6 is a flowchart illustrating a method of driving a liquid crystal display according to an exemplary embodiment of the present invention.

DESCRIPTION OF THE REFERENCE NUMERALS (S)

100: liquid crystal panel 200: drive circuit portion

210: gate driver GIC_1, GIC_2, GIC_3: gate integrated circuit

220: data driver SIC_1, SIC_2, SIC_3: data integrated circuit

230: printed circuit board 231: timing controller

232: gamma voltage generator 233: power supply unit

The present invention relates to a liquid crystal display device.

The liquid crystal display device forms a liquid crystal layer having anisotropic dielectric constant between upper and lower substrates, which are transparent insulating substrates, and then adjusts the intensity of an electric field formed in the liquid crystal layer to change the molecular arrangement of the liquid crystal material, thereby The display device expresses a desired image by adjusting the amount of light transmitted through the upper substrate. As a liquid crystal display device, a thin film transistor liquid crystal display (TFT LCD) using a thin film transistor (TFT) as a switching element is mainly used.

1 is a configuration diagram of a liquid crystal display according to the prior art.

Referring to FIG. 1, a conventional liquid crystal display device includes a liquid crystal panel 10 for displaying an image, a gate driver 21, a data driver 22, and a gate driver 21 for driving the liquid crystal panel 10. And a timing controller 24 for controlling the driving timing of the data driver 22.

In the liquid crystal panel 10, a plurality of pixels in which regions are divided by a horizontal gate line GL and a vertical data line DL that cross each other is arranged in a matrix form, and the gate line GL and the data line are arranged in a matrix form. A thin film transistor TFT having a gate electrode, an active layer, a source electrode, and a drain electrode is disposed at an intersection portion of the DL.

Each pixel is formed with a liquid crystal material equivalent to the liquid crystal cell Clc and a storage capacitor Cst for maintaining a constant voltage charged in the liquid crystal cell Clc.

The liquid crystal panel 10 displays an image on each pixel according to a scan signal supplied through the gate line GL and a data signal supplied through the data line DL. Here, the scan signal is a pulse in which the gate high voltage supplied for one horizontal period and the gate low voltage supplied for the remaining period are alternated.

The thin film transistor TFT provided for each pixel is turned on when the gate high voltage is supplied from the gate line GL to supply the data signal transmitted from the data line DL to the liquid crystal cell Clc. When a gate low voltage is supplied from the gate line GL, the gate signal is turned off to maintain the data signal charged in the liquid crystal cell Clc for one frame period.

The gate driver 21 sequentially supplies scan signals to the plurality of gate lines GL arranged in the horizontal direction according to the gate control signal supplied from the timing controller 24. The gate control signal input to the gate driver 21 includes a gate start pulse (GSP), a gate shift clock (GSC), a gate enable signal (GOE), and the like.

The data driver 22 converts red, green, and blue pixel data input from the timing controller 24 into a data signal in response to a data control signal supplied from the timing controller 24, and converts the pixel data into a data signal. Supply. Here, the data signal is a gamma voltage selected corresponding to the red, green, and blue pixel data (gray level) input from the outside of the gamma voltages of various levels.

The timing controller 24 is generally mounted on a printed circuit board (PCB) 23 and connected to the data driver 21, and reprocesses red, green, and blue pixel data input from the outside. Supply to the data driver 22. A gate control signal for controlling the driving timing of the gate driver 21 and a data control signal for controlling the driving timing of the data driver 22 are generated using the synchronization signals such as vertical and horizontal synchronization signals and a clock. .

The gate driver 21 and the data driver 22 are formed of a plurality of integrated circuits (ICs) (GIC_1 to GIC_3 and SIC_1 to SIC_3), which are integrated on a tape carrier package (TCP). It is mounted on and connected to the liquid crystal panel 10.

FIG. 2A is a waveform diagram illustrating a process of generating a scan signal in the gate driver of FIG. 1.

The gate start pulse GSP is a signal for controlling the start and end points of the scan signals SP1, SP2, and SP3 among one vertical synchronization signal, and the gate shift clock GSC is a gate on / off gate of the thin film transistor TFT. The signal indicating time, and the gate enable signal (GOE) is a signal that controls the output of the gate integrated circuit (GIC_1, GIC_2, GIC_3).

Referring to these operations, the gate start pulse GSP is shifted by the gate shift clock GSC, and the output of the gate integrated circuits GIC_1, GIC_2, and GIC_3 is controlled by the gate enable signal GOE.

The gate integrated circuits GIC_1, GIC_2, and GIC_3 recognize the high level of the gate start pulse GSP at the rising edge or the falling edge of the gate shift clock GSC to increase the level as high as one period of the gate shift clock GSC. To generate output. In this case, when a high level is applied to the gate enable signal GOE, a plurality of scan signals SP1, SP2, and SP3 that are disabled by the pulse width of the gate enable signal GOE are each gate line GL. Are printed sequentially.

However, in the related art, as shown in FIG. 1, the gate enable signal GOE is formed from the timing controller 24 through the first gate integrated circuit GIC_1 and the first through the plurality of signal lines AL1, AL2, and AL3. The second gate integrated circuit GIC_2, the third gate integrated circuit GIC_3, and the like are sequentially transferred in order.

Accordingly, as the positions of the gate integrated circuits GIC_1, GIC_2, and GIC_3 move away from the timing controller 24 and the path through which the gate enable signal GOE is transmitted is increased, the scan output in response to the gate enable signal GOE is output. A phenomenon in which the signals SP2 and SP3 are delayed occurs.

When the scan signals SP2 and SP3, which are output waveforms of the gate integrated circuits GIC_2 and GIC_3, are delayed, the pulse widths of the scan signals SP2 and SP3 vary according to the delay degree, and the gate integrated circuits GIC_1 and GIC_2, The charging time of GIC_3) will be different.

In particular, when the signal lines AL1, AL2, and AL3 are of a line on glass (LOG) type formed on the liquid crystal panel 10, the self-resistance of the signal lines AL1, AL2, and AL3 becomes large. This deepened.

FIG. 2B illustrates a gate enable signal GOE sequentially transmitted to the first gate integrated circuit GIC_1 and the second gate integrated circuit GIC_2, and integrates the first and second gates in response to the gate enable signal GOE. More specifically, the waveforms of the scan signals SP1 and SP2 output from the circuits GIC_1 and GIC_2 are shown.

2A, when the gate enable signal GOE is sequentially transmitted to the first and second gate integrated circuits GIC_1 and GIC_2, the scan signal SP2 of the second gate integrated circuit GIC_2 is output. The time point is delayed from the time point at which the scan signal SP1 of the first gate integrated circuit GIC_1 is output.

Accordingly, the pulse widths of the scan signals SP1 and SP2 output from the first, second, and third gate integrated circuits GIC_1, GIC_2, and GIC_3 are controlled by the control of the gate enable signal GOE, thereby resulting in an area ( R1, R2, and R3) have a luminance deviation, and this luminance variation causes a horizontal line and has a problem of degrading image quality.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a liquid crystal display device in which a gate enable signal may be appropriately changed in some regions to improve luminance deviation and image quality degradation due to signal delay.

Another object of the present invention is to provide a liquid crystal display device capable of making the overall luminance uniform by controlling and optimizing a pulse width of a gate enable signal differently for each gate integrated circuit.

Technical problems to be achieved by the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned above will be clearly understood by those skilled in the art from the following description. Could be.

According to an exemplary embodiment of the present invention, a liquid crystal display includes: data lines to which data signals are supplied, gate lines to which scan signals are supplied by crossing the data lines, and pixels in which a pixel is arranged in a matrix; A first gate integrated circuit configured to output a scan signal to gate lines formed in a first region of the liquid crystal panel in response to a first gate enable signal input through a first signal line; A second gate integrated circuit configured to output a scan signal to gate lines formed in a second region of the liquid crystal panel in response to a second gate enable signal input through a second signal line longer than the first signal line; And a timing controller generating the first and second gate enable signals to control the gate integrated circuits.
The pulse width of the second gate enable signal is smaller than the pulse width of the first gate enable signal.
The scan signal output from the first gate integrated circuit is inactive by the pulse width of the first gate enable signal, and the scan signal output from the second gate integrated circuit is inactive by the pulse width of the second gate enable signal. do.

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The details of other embodiments are included in the detailed description and drawings. Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. Like reference numerals refer to like elements throughout.

Hereinafter, the liquid crystal display according to the exemplary embodiments of the present invention will be described in detail with reference to FIGS. 3 to 5.

3 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 3, the liquid crystal display according to the exemplary embodiment may be largely divided into a liquid crystal panel 100 and a driving circuit unit 200 driving the liquid crystal panel 100.

The liquid crystal panel 100 includes upper and lower substrates facing each other and a liquid crystal layer formed therebetween. Each pixel is defined by crossing the gate line GL and the data line DL on the lower substrate, and a thin film transistor TFT for driving the liquid crystal cell Clc is formed at the intersection thereof.

The thin film transistor TFT formed at the intersection of the vertical data line DL and the horizontal gate line GL receives a data signal on the data line DL in response to a scan signal applied from the gate line GL. It is supplied to the liquid crystal cell Clc. For this operation, the gate electrode of the thin film transistor TFT is connected to the gate line GL, the source electrode is connected to the data line DL, and the drain electrode is configured to be connected to the pixel electrode of the liquid crystal cell Clc. do.

A common voltage is supplied to the common electrode facing the pixel electrode, and a storage capacitor Cst is connected to each liquid crystal cell Clc of the liquid crystal panel 100 to maintain a constant voltage charged in the liquid crystal cell Clc. . The storage capacitor Cst is formed between the liquid crystal cell Clc connected to any kth gate line and the liquid crystal cell Clc connected to the kth gate line, May be formed between the storage lines.

The driving circuit 200 may include a timing controller 231, a gate driver 210, a data driver 220, a plurality of signal lines BL1, BL2, and BL3 formed in a line on glass type, a timing controller 231, and a gamma voltage. Generation unit 232, power supply unit 233, and the like.

The timing controller 231 reprocesss the input pixel data and supplies it to the data driver 220. In addition, a gate control signal for controlling the gate driver 210 and a data control signal for controlling the data driver 220 are generated by using synchronization signals such as vertical and horizontal synchronization signals and a clock to control respective driving timings. do.

The gate control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate enable signal (GOE), and the like.

The data control signal includes a source start pulse (SSP), a source shift clock (SSC), a source enable signal (SOC), a polarity control signal (POL), and the like. This includes.

The gate driver 210 includes a plurality of gate integrated circuits GIC_1, GIC_2, and GIC_3, and sequentially supplies scan signals to the gate line GL of the liquid crystal panel 100 under the control of the timing controller 231. The thin film transistor TFT formed in the pixel is switched.

That is, the gate driver 210 generates a scan signal including a gate low voltage and a gate high voltage in response to the gate control signal supplied from the timing controller 231. Then, the gate line GL is sequentially supplied to the gate line GL of each pixel along one direction (for example, from top to bottom). As the scan signal is supplied, the thin film transistor TFT connected to the gate line GL is sequentially driven.

The gate driver 210 includes a shift register for sequentially generating a scan signal and a level shifter for shifting the voltage of the scan signal to a level suitable for driving the liquid crystal cell Clc.

When the gate enable signals having the same pulse width are supplied to all the gate integrated circuits GIC_1, GIC_2, and GIC_3, the resistances of the signal lines BL1, BL2, and BL3, the transmission paths, and the gate integrated circuits GIC_1, GIC_2, and GIC_3 may be The gate enable signal is delayed according to the position, the characteristic, and the like, and the pulse width is changed. Then, the pulse width of the scan signal supplied to each gate line GL is changed by the control of the gate enable signal, so that the charging time is different for each of the regions R1, R2, and R3. It may cause a horizontal line defect.

For example, the charging time of the k-th gate line connected to the first gate integrated circuit GIC_1 and the k + 1 th connected to the second gate integrated circuit GIC_2 due to the resistance of the signal lines BL1 and BL2, and the like. Differences occur in the charging time of the gate line, and a horizontal line defect occurs due to the luminance difference between the two gate lines.

In order to solve this problem, the timing controller 231 generates a plurality of gate enable signals GOE1, GOE2, and GOE3 having different pulse widths by adjusting the pulse width of the gate enable signal, and then uses the gate integrated circuit GIC_1. Are independently supplied to the gate integrated circuits GIC_1, GIC_2, and GIC_3 via signal lines BL1, BL2, and BL3 connected to the GIC_2 and GIC_3, respectively.

In other words, the pulse widths of the gate enable signals GOE1, GOE2, and GOE3 are adjusted according to the positions of the gate integrated circuits GIC_1, GIC_2, and GIC_3, and the difference in charging time due to the resistance of the signal lines BL1, BL2, BL3, and the like. It compensates for the horizontal line defect.

The gate enable signals GOE1, GOE2, and GOE3 are not sequentially transmitted in one direction while passing through the plurality of gate integrated circuits GIC_1, GIC_2, and GIC3, and the signal lines BL1, which are connected to the output channel of the timing controller 231, are not provided. Individually directly supplied to each gate integrated circuit GIC_1, GIC_2, and GIC_3 along BL2 and BL3.

In the case of FIG. 3, gate enable signals GOE1, GOE2, and GOE3 are generated by the number of gate integrated circuits GIC_1, GIC_2, and GIC_3, and gate enable to correspond to the gate integrated circuits GIC_1, GIC_2, and GIC_3. The pulse widths of the signals GOE1, GOE2, GOE3 are determined.

The gate driver 210 generates a plurality of scan signals to correspond to the plurality of gate enable signals supplied from the timing controller 231, and supplies the plurality of scan signals to the gate lines GL of the liquid crystal panel 100.

The timing controller 231 controls the pulse widths of the gate enable signals GOE1, GOE2, and GOE3 to compensate for signal delays of the gate enable signals GOE2 and GOE3. As a result, the width of the scan signal, which is the output of the gate integrated circuits GIC_1, GIC_2, and GIC_3 and the corresponding charging time, may be the same in all the gate lines GL.

The data driver 220 includes a plurality of data integrated circuits SIC_1, SIC_2, and SIC_3. The data driver 220 transmits data signals of one line every one horizontal period in response to the data control signal, and the data lines DL of the liquid crystal panel 100. To supply. In this case, the data driver 220 receives pixel data from the timing controller 231, selects a gamma voltage corresponding thereto, and supplies the data signal to the data line DL.

The power supply unit 233 receives power from an external system (not shown) and generates various levels of driving voltages such as a gate high voltage, a gate low voltage, a common voltage, a constant voltage, and applies a voltage to each unit.

The gamma voltage generator 232 receives a voltage branched from the power supply unit 233 to generate and supply gamma voltages (reference voltages) necessary for digital / analog conversion of the data driver 220 to the data driver 220.

The timing controller 231, the power supply unit 233, the gamma voltage generator 232, and the like are mounted on or on the printed circuit board 230 connected to the data driver 220 as shown in FIG. It is mounted on a circuit board.

4A and 4B are waveform diagrams illustrating a process of compensating a charging time by controlling a pulse width of a gate enable signal.

The first to third gate enable signals GOE1, GOE2, and GOE3 illustrate three gate enable signals applied to the first to third gate integrated circuits GIC_1, GIC_2, and GIC_3.

The first gate enable signal GOE1 and the second gate enable signal GOE2 have the second gate enable signal GOE2 and the third gate enable signal GOE3 by the first period DT1 in the pulse width. Has a difference as much as the second period DT2 in the pulse width.

The charging time of each pixel is determined to correspond to the high level section or the low level section of the scan signals SP1 to SP3 output from the gate driver 210, and the high / lowness of the scan signals SP1 to SP3 for determining the charging time. The low level period is controlled by the gate enable signals GOE1 to GOE3. Therefore, if a gate enable signal having the same pulse width is applied to each of the gate integrated circuits GIC_1, GIC_2, and GIC_3, the charging time varies with the time delay of the gate enable signal, and as a result, the luminance difference varies depending on the region. Will occur.

In order to solve this problem, the pulse widths of the gate enable signals GOE1, GOE2, and GOE3 supplied to the respective gate integrated circuits GIC_1, GIC_2, and GIC_3 may cancel the signal time delay and the resulting luminance difference. It is decided to the extent that it is possible.

For example, the second signal line BL2 through which the second gate enable signal GOE2 is transmitted is longer than that of the first signal line BL1 through which the first gate enable signal GOE1 is transmitted, and thus has a higher resistance. .

In this case, when the pulse widths of the first and second gate enable signals GOE1 and GOE2 are the same, the signal delay of the second gate enable signal GOE2 becomes larger than that of the first gate enable signal GOE1. . In addition, the widths of the scan signals output from the first and second gate integrated circuits GIC_1 and GIC2 and the charging time corresponding thereto are different from each other.

Therefore, the timing controller 231 controls the pulse width of the second gate enable signal GOE2 to be smaller than the pulse width of the first gate enable signal GOE1 so that the two scan signals SP1 after the signal delay occurs. , The actual pulse width of SP2) is consequently the same to compensate for the signal delay.

Similarly, since the third signal line BL3 is longer than the second signal line BL2 and the resistance thereof is greater, the pulse width of the third gate enable signal GOE3 is the pulse width of the second gate enable signal GOE2. It is controlled to be smaller than.

As a result, the timing controller 231 gradually decreases the pulse widths of the first to third gate enable signals GOE1, GOE2, and GOE3 as shown in FIG. The pulse widths are made to be substantially equal, thereby controlling the charging times of all the gate lines GL to be equal to each other.

In FIG. 4A, the high level section OT of the scan signals SP1 to SP3 corresponds to the low level section IT1 of the gate enable signals GOE1 to GOE3, respectively, and the charging time of each gate line GL is changed. The case corresponding to the high level section OT of the scan signals SP1 to SP3 is illustrated.

When the lengths and the resistances of the signal lines BL1, BL2, and BL3 increase, the delay degrees of the scan signals SP2 and SP3 increase correspondingly.

In this case, the timing controller 231 scans by controlling the pulse widths of the gate enable signals GOE1, GOE2, and GOE3 to decrease as the length of the signal lines BL1, BL2, and BL3 increases, as shown in FIG. 4A. The delay of the signals SP2 and SP3 and the reduction of the charging time due to the signal delay can be compensated.

In this way, the timing controller 231 pulses the gate enable signals GOE1, GOE2, and GOE3 such that the charging time determined by the scan signals SP1 through SP3 is the same in all the gate integrated circuits GIC_1, GIC_2, and GIC_3. The width can be controlled.

For example, when the charging time of the gate line GL connected to the third gate integrated circuit GIC_3 is less than that of other gate lines GL, the third gate in supplied to the third gate integrated circuit GIC_3 may be The pulse width of the enable signal GOE3 is controlled to be smaller than the pulse widths of the first and second gate enable signals GOE1 and GOE2.

In addition, the timing controller 231 may control the pulse widths of the gate enable signals GOE1, GOE2, and GOE3 to vary according to positions at which the gate integrated circuits GIC_1, GIC_2, and GIC_3 are disposed.

Alternatively, the position-specific luminance corresponding to each gate integrated circuit GIC_1, GIC_2, and GIC_3 may be checked, and the pulse widths of the gate enable signals GOE1, GOE2, and GOE3 may be controlled according to the luminance deviation. In this case, as the luminance of each position is lower, it is more efficient to control the pulse width of the gate enable signals (GOE1, GOE2, GOE3) to secure the charging time.

As described above, when the gate enable signals GOE1, GOE2, and GOE3 having different pulse widths are applied according to the position-specific luminance corresponding to the gate integrated circuits GIC_1, GIC_2, and GIC_3, the signal lines BL1, BL2, and BL3. The difference in the charging time according to the resistance of the back can be compensated for and the horizontal line defect can be improved.

That is, the timing controller 231 makes the pulse widths of the gate enable signals GOE1, GOE2, and GOE3 applied to the gate integrated circuits GIC_1, GIC_2, and GIC_3 different from each other, and the second gate enable signals GOE2, In the case of GOE3), the low level sections IT2 and IT3 are further increased by the first and second sections DT1 and DT2 to further increase the charging time.

In this case, the pulse widths of the second and third gate enable signals GOE2 and GOE3 applied to the second and third gate integrated circuits GIC_2 and GIC_3 may be equal to the pulse widths of the first gate enable signal GOE1. different. However, the time delay of the second and third gate enable signals GOE2 and GOE3 occurs due to the resistances of the actual signal lines BL2 and BL3, resulting in the first to third gate integrated circuits GIC1, GIC2, and GIC3. Since the charging times are the same, the luminance difference can be compensated and the horizontal line problem can be solved.

FIG. 4B illustrates gate enable signals GOE1 and GOE2 transmitted to the first gate integrated circuit GIC_1 and the second gate integrated circuit GIC_2, respectively, and responds to the gate enable signals GOE1 and GOE2 in response to the first and second gate integrated signals GIC_1 and GIC_2. More specifically, waveforms of the scan signals SP1 and SP2 output from the second gate integrated circuits GIC_1 and GIC_2 are shown.

Since the pulse widths of the first and second gate enable signals GOE1 and GOE2 are different from each other, the second scan signal GOE2 has a longer charging time than the first scan signal GOE1 by the first period DT1. Secured.

However, in practice, signal delay occurs due to factors such as resistance of the signal lines BL1 and BL2, so that the charging time between the first and second gate integrated circuits GIC_1 and GIC_2 becomes equal, thereby compensating for the luminance difference. The horizontal line problem is solved.

5 is a configuration diagram of a liquid crystal display according to another exemplary embodiment of the present invention.

In the liquid crystal display of FIG. 5, the timing controller 231 generates fewer gate enable signals GOE1 and GOE2 than the number of gate integrated circuits GIC1, GIC2, and GIC3.

The gate enable signals GOE1 and GOE2 are directly supplied to some gate integrated circuits GIC_1 and GIC_2 along the signal lines CL1 and CL2 connected to the output channel of the timing controller 231.

The gate enable signal GOE2 transmitted to some gate integrated circuits GIC_2 is transmitted from the gate integrated circuit GIC_2 to the remaining gate integrated circuits GIC3. In this case, the gate enable signal GOE2 proceeds sequentially along the upper direction or the lower direction of the liquid crystal panel 100, and the wiring and the liquid crystal on the tape carrier substrate TCP on which the gate integrated circuits GIC_2 and GIC_3 are mounted. It is supplied along the signal lines CL2, CL3, CL4 on the panel 100.

For example, the first gate integrated circuit GIC1 and the second gate integrated circuit GIC2 receive the gate enable signals GOE1 and GOE2 directly from the timing controller 231 through the signal lines CL1 and CL2. do. The gate enable signal GOE2 transmitted to the second gate integrated circuit GIC2 is sequentially supplied to the lower ends of the third gate integrated circuit GIC3 and the like.

The pulse widths of the gate enable signals GOE1 and GOE2 can be optimized as in the case of FIG. 3.

That is, the timing controller 231 forms a plurality of gate enable signals GOE1 and GOE2, and horizontal lines such as characteristics of the gate integrated circuits GIC_1, GIC_2, and GIC_3, vertical position, charging time, delay time, and luminance for each part. The pulse widths of the gate enable signals GOE1 and GOE2 are controlled to offset the factors causing the failure.

In FIG. 5, the first gate enable signal GOE1 and the second gate enable signal GOE2 having different pulse widths pass through the first and second signal lines CL1 and CL2 to the first gate integrated circuit GIC_1. ) And a second gate enable signal GOE2 are sequentially supplied from the second gate integrated circuit GIC_2 to the gate integrated circuit GIC3 at the bottom thereof. Doing.

However, the present invention is not limited thereto, and the position or number of the gate integrated circuits GIC_1, GIC_2, and GIC_3 directly receiving the gate enable signals GOE1, GOE2, and GOE3 from the timing controller 231 may be changed. have.

For example, when the luminance of the region R3 connected to the third gate integrated circuit GIC_3 among the vertical positions R1, R2, and R3 of the liquid crystal panel 100 is significantly lower than other regions, the third gate integration may be performed. The charging time may be secured by applying a gate enable signal having a narrower pulse width than the other gate integrated circuits GIC_1 and GIC_2 to the circuit GIC_3.

Since the components of FIG. 5 are the same as the components of FIG. 3, a detailed description thereof will be omitted.

Hereinafter, a driving method of the liquid crystal display according to the exemplary embodiment of the present invention will be described in detail with reference to FIG. 6.

First, in step S100, the timing controller 231 generates a gate control signal and a data control signal for controlling the driving timing and supplies them to the gate driver 210 and the data driver 220, respectively. In this case, the gate control signal includes a plurality of gate enable signals having different pulse widths.

Here, the timing controller 231 controls the pulse width of the gate enable signal so that the charging time determined by the scan signal is equal to each other, or the luminance of each vertical position of the liquid crystal panel 100 and the vertical position of the liquid crystal panel 100. The pulse width of the gate enable signal varies according to the deviation.

Next, in step S110, after the gate driver 210 generates a plurality of scan signals having different widths in response to the plurality of gate enable signals, the gate lines of the liquid crystal panel 100 in response to the gate control signals. A plurality of scan signals are supplied to GL.

Next, in step S120, the data driver 220 supplies the data signal to the data line DL of the liquid crystal panel 100 in response to the data control signal.

Next, in operation S130, the liquid crystal panel 100 displays an image for each pixel according to a plurality of scan signals supplied to the gate lines GL and data signals supplied to the data lines DL.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, You will understand.

Therefore, it should be understood that the above-described embodiments are provided so that those skilled in the art can fully understand the scope of the present invention. Therefore, it should be understood that the embodiments are to be considered in all respects as illustrative and not restrictive, The invention is only defined by the scope of the claims.

The liquid crystal display and the driving method thereof according to the present invention configured as described above can appropriately vary the gate enable signal in a partial region to improve luminance deviation and image quality degradation due to signal delay.

In addition, the liquid crystal display and the driving method thereof according to the present invention can uniformly control the pulse width of the gate enable signal for each gate integrated circuit to optimize the overall luminance.

Claims (15)

A liquid crystal panel in which data lines to which data signals are supplied, gate lines to which scan signals are supplied while crossing the data lines, and pixels are arranged in a matrix; A first gate integrated circuit configured to output a scan signal to gate lines formed in a first region of the liquid crystal panel in response to a first gate enable signal input through a first signal line; A second gate integrated circuit configured to output a scan signal to gate lines formed in a second region of the liquid crystal panel in response to a second gate enable signal input through a second signal line longer than the first signal line; And A timing controller configured to generate the first and second gate enable signals to control the gate integrated circuits; The pulse width of the second gate enable signal is smaller than the pulse width of the first gate enable signal, The scan signal output from the first gate integrated circuit is inactive by the pulse width of the first gate enable signal, and the scan signal output from the second gate integrated circuit is inactive by the pulse width of the second gate enable signal. Liquid crystal display device characterized in that. delete The method of claim 1, And the first and second signal lines are formed on the liquid crystal panel in a line on glass type. delete delete delete delete delete delete delete delete delete delete delete delete

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