KR20060118775A - Driving apparatus of liquid crystal display - Google Patents

Abstract

A driving device of a liquid crystal display is provided to restrict flicker by decreasing the magnitude of kick-back voltage by reducing the difference between gate-on voltage and gate-off voltage in some gray scales in which the kick-back voltage is generated. A driving device of a liquid crystal display having plural pixels each including switching element(Q) includes a gate driving unit(400) applying gate voltage to the switching elements; a compensation unit(700) connected to the gate driving unit; a gate voltage generating unit(750) connected with the compensation unit and the gate driving unit; a memory(650) connected to a signal control unit(600) to store information on the kick-back voltage according to the gray scales; and the gate driving unit generating compensation control signals(CONT1,CONT2) having a predetermined duty ratio on the basis of the information output from the memory and applying the compensation control signal to the compensation unit.

Description

Driving device of liquid crystal display {DRIVING APPARATUS OF LIQUID CRYSTAL DISPLAY}

With reference to the accompanying drawings will be described in detail the embodiments of the present invention to make the present invention clear.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is an example of a circuit diagram of the compensator shown in FIG. 1.

4 is a graph measuring the amount of kickback according to gradation.

5 is a waveform diagram illustrating a change in a gate signal according to a width of a high section of a control signal.

<Description of Drawing>

3: liquid crystal layer 100: lower display panel

190: pixel electrode 200: upper display panel

230: color filter 270: common electrode

300: liquid crystal panel assembly 400: gate driver

500: data driver 600: signal controller

650: memory 700: compensation unit

750: gate voltage generator 800: gray voltage generator

R, G, B: Input image data DE: Data enable signal

MCLK: Main Clock Hsync: Horizontal Sync Signal

Vsync: Vertical Sync Signal CONT1: Gate Control Signal

CONT2: data control signal DAT: output video signal

C _LC : Liquid Crystal Capacitor C _ST : Holding Capacitor

Q: switching device

The present invention relates to a drive device for a liquid crystal display device.

A typical liquid crystal display (LCD) includes two display panels provided with pixel electrodes and a common electrode, and a liquid crystal layer having dielectric anisotropy interposed therebetween. The pixel electrodes are arranged in a matrix and connected to switching elements such as thin film transistors (TFTs) to receive data voltages one by one in sequence. The common electrode is formed over the entire surface of the display panel and receives a common voltage. The pixel electrode, the common electrode, and the liquid crystal layer therebetween form a liquid crystal capacitor, and the liquid crystal capacitor becomes a basic unit forming a pixel together with a switching element connected thereto.

In such a liquid crystal display, a voltage is applied to two electrodes to generate an electric field in the liquid crystal layer, and the intensity of the electric field is adjusted to adjust the transmittance of light passing through the liquid crystal layer to obtain a desired image. In this case, in order to prevent degradation caused by an electric field applied to the liquid crystal layer for a long time, the polarity of the data voltage with respect to the common voltage is inverted frame by frame, row by pixel, or pixel by pixel.

On the other hand, the liquid crystal display includes a gate driver for outputting a gate voltage for turning on / off the switching element and a data driver for applying a data voltage to the pixel through the turned on switching element.

At this time, the applied data voltage must be maintained even after the switching element is turned off, but the applied voltage is distorted due to the parasitic capacitance between the gate electrode and the drain electrode or the source electrode. The distorted voltage is called a kick-back voltage, and the kick-back voltage reduces the pixel voltage at the portion where the gate voltage changes. Therefore, asymmetry occurs in the positive and negative pixel voltages during the inversion driving, causing a flicker phenomenon in which the screen flickers.

Accordingly, an object of the present invention is to provide a liquid crystal display device capable of preventing flicker.

According to an exemplary embodiment of the present invention, there is provided a driving apparatus of a liquid crystal display including a plurality of pixels each including a switching element, the gate driver applying a gate voltage to the switching element, and the gate driver. A compensator connected to the gate, a gate voltage generator connected to the compensator and the gate driver, a memory connected to the signal controller and storing kickback voltage information according to the gray scale, and based on the information from the memory. And a signal control unit generating a compensation control signal having a predetermined duty ratio and applying the compensation control signal to the compensation unit.

The gate voltage generator may apply a first gate on voltage to the compensator and a gate off voltage to the gate driver.

The compensator may receive the first gate-on voltage to send a second gate-on voltage according to the compensation control signal to the gate driver.

The compensator may include a first transistor configured to receive the first gate-on voltage and transmit the first gate-on voltage to an output terminal, and a second transistor connected to the output terminal through a predetermined resistor and operating according to the compensation control signal.

The output terminal may output the second gate on voltage, and when the second transistor is turned on according to the compensation control signal, the level of the second gate on voltage may decrease.

The signal controller sends a gate control signal to the gate driver, and the gate control signal is an output that defines a gate clock signal for controlling the output timing of the second gate on voltage and a duration of the second gate on voltage. It may include an enable signal.

The compensation control signal may be the gate clock signal, the output enable signal, or a signal synchronized with the gate clock signal.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Now, a driving device of a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention is connected to a liquid crystal panel assembly 300, a gate driver 400 and a gate driver 400 connected thereto. The compensator 700 and the gate voltage generator 750 connected thereto, the data driver 500, the gray voltage generator 800 connected to the data driver 500, and the signal controller 600 controlling them, and Memory 650 is coupled.

The liquid crystal panel assembly 300 includes a plurality of display signal lines G ₁ -G _n , D ₁ -D _m and a plurality of pixels connected to the plurality of display signal lines G ₁ -G _n , D ₁ -D _m , and arranged in a substantially matrix form. .

The display signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n for transmitting a gate signal (also called a “scan signal”) and a data signal line or data for transmitting a data signal. Line D ₁ -D _m . The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel includes a switching element Q connected to a display signal line G ₁ -G _n , D ₁ -D _m , and a liquid crystal capacitor C _LC and a storage capacitor C _ST connected thereto. It includes. The holding capacitor C _ST can be omitted as necessary.

The switching element Q is provided on the lower panel 100, and the control terminal and the input terminal are connected to the gate line G ₁ -G _n and the data line D ₁ -D _m, respectively. The output terminal is connected to the liquid crystal capacitor C _LC and the storage capacitor C _ST . In addition, the switching element Q is preferably a thin film transistor, and particularly preferably comprises amorphous silicon.

The liquid crystal capacitor C _LC has two terminals, the pixel electrode 190 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 190 and 270. It functions as a dielectric. The pixel electrode 190 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives a common voltage V _com . Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, both electrodes 190 and 270 may be linear or rod-shaped.

The storage capacitor C _ST is formed by overlapping a separate signal line (not shown) and the pixel electrode 190 provided on the lower panel 100, and a predetermined voltage such as a common voltage V _com is applied to the separate signal line. Is approved. However, the storage capacitor C _ST may be formed such that the pixel electrode 190 overlaps the front end gate line directly above the insulator.

On the other hand, in order to implement color display, each pixel should be able to display color, which is provided with a color filter 230 of three primary colors, for example, red, green, or blue, in a region corresponding to the pixel electrode 190. It is possible by doing. In FIG. 2, the color filter 230 is formed on the upper panel 200. Alternatively, the color filter 230 may be formed on or under the pixel electrode 190 of the lower panel 100.

A polarizer (not shown) for polarizing light is attached to an outer surface of at least one of the two display panels 100 and 200 of the liquid crystal panel assembly 300.

The gray voltage generator 800 generates two sets of gray voltages related to the transmittance of the pixel. One of the two sets has a positive value for the common voltage (V _com ) and the other set has a negative value.

The gate voltage generator 750 generates a gate voltage including the gate on voltage V _on1 and the gate off voltage Voff, and outputs the gate on voltage V _on1 to the compensator, and the gate off voltage Voff Export to the gate driver 400.

The compensator 700 compensates for the gate-on voltage V _on1 and emits the gate-on voltage V _on2 .

The gate driver 400 is connected to the gate lines G ₁ -G _n of the liquid crystal panel assembly 300 to form a combination of the gate on voltage V _on2 and the gate off voltage V _off from the compensator 700. The formed gate signal is applied to the gate lines G ₁ -G _n . The gate driver 400 includes a plurality of stages arranged substantially in a row as a shift register.

The data driver 500 is connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300 to select the gray voltage from the gray voltage generator 800 and apply the gray voltage to the pixel as a data signal. It consists of a circuit.

The signal controller 600 controls operations of the gate driver 400 and the data driver 500.

Next, the display operation of the liquid crystal display will be described in more detail.

The signal controller 600 inputs an input control signal for controlling the image signals R, G, and B and its display from an external graphic controller (not shown), for example, a vertical sync signal V _sync and a horizontal sync signal ( H _sync ), a main clock MCLK, a data enable signal DE, and the like. The signal controller 600 generates a gate control signal CONT1 and a data control signal CONT2 based on the input control signal, and adjusts the image signals R, G, and B to match the operating conditions of the liquid crystal panel assembly 300. After appropriately processing, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are sent to the data driver 500. In addition, the signal controller 600 sends the compensation control signal CONT3 to the compensation unit 700 based on the kickback information according to the grayscale stored in the memory 650.

The gate control signal (CONT1) includes a gate-on voltage vertical synchronization start signal (STV) for instructing the start of output of the (V _on), the gate-on voltage gated clock signal that controls the output timing of the (V _on) (CPV) and the gate-on An output enable signal OE or the like that defines the duration of the voltage V _on .

The data control signal CONT2 includes a horizontal synchronization start signal STH indicating the start of input of the image data DAT, a load signal LOAD for applying a corresponding data voltage to the data lines D ₁ -D _m , and a common voltage. An inversion signal (RVS) and a data clock signal (HCLK) that invert the polarity of the data voltage with respect to (V _com ) (hereinafter referred to as "data voltage polarity" by reducing "polarity of data voltage with respect to common voltage"). It includes.

The data driver 500 sequentially receives the image data DAT corresponding to one row of pixels according to the data control signal CONT2 from the signal controller 600, and among the gray voltages from the gray voltage generator 800. By selecting the gray scale voltage corresponding to each image data DAT, the image data DAT is converted into a corresponding data voltage and applied to the data lines D ₁ -D _m .

The gate driver 400 applies the gate-on voltage V _on2 to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n. Turn on the switching element (Q) connected to. The data voltage supplied to the data lines D ₁ -D _m is applied to the corresponding pixel through the turned-on switching element Q.

The difference between the data voltage applied to the pixel and the common voltage V _com is shown as the charging voltage of the liquid crystal capacitor C _LC , that is, the pixel voltage. The liquid crystal molecules vary in arrangement depending on the magnitude of the pixel voltage. As a result, the polarization of light passing through the liquid crystal layer 3 changes. The change in polarization is represented by a change in transmittance of light by a polarizer (not shown) attached to the display panels 100 and 200.

After one horizontal period (or "1H") (one period of the horizontal sync signal H _sync , the data enable signal DE, and the gate clock CPV), the data driver 500 and the gate driver 400 are next. The same operation is repeated for the pixels in the row. In this manner, the gate-on voltages V _{on are} sequentially applied to all the gate lines G ₁ -G _n during one frame to apply data voltages to all the pixels. At the end of one frame, the next frame starts and the state of the inversion signal RVS applied to the data driver 500 is controlled so that the polarity of the data voltage applied to each pixel is opposite to that of the previous frame ("frame inversion). "). At this time, the polarity of the data voltage flowing through one data line is changed according to the characteristics of the inversion signal RVS even in one frame (eg, "row inversion", "point inversion"), or the voltage of the data voltage applied to one pixel row. The polarities can also be different (eg "heat inversion", "point inversion").

Next, a driving device of the liquid crystal display according to the exemplary embodiment of the present invention will be described in detail with reference to FIGS. 3 to 5.

FIG. 3 is an example of a circuit diagram of the compensator shown in FIG. 1, FIG. 4 is a graph showing an amount of kickback voltage according to gray levels, and FIG. 5 is a diagram showing a change in gate voltage according to a compensation control signal.

Referring to FIG. 3, the compensator 700 according to an exemplary embodiment of the present invention includes a plurality of transistors T1 and T2, resistors R1-R3, and a capacitor C. FIG.

The transistors T1 and T2 are bipolar junction transistors (BJTs). The transistor T1 is of pnp type and the transistor T2 is of npn type. Alternatively, the transistors T1 and T2 may be MOS transistors.

The first terminal of the transistor T1 receives the gate-on voltage V _on1 , the second terminal is connected to the ground voltage, and the third terminal is connected to the capacitor C and the resistor R1 once in parallel. Is connected to. The transistor T1 is always turned on because the second terminal, which is the control terminal, is connected to the ground voltage, and transmits the gate-on voltage V _on1 to the third terminal.

The first terminal of the transistor T2 is connected to the ground voltage, the second terminal is connected to the compensation control signal CONT3, and the third terminal is connected to the resistor R2. The transistor T2 is turned on or off depending on the level of the compensation control signal CONT3.

Next, the operation of the compensator 700 will be described.

Figure 4 shows the relative amount of the kickback voltage measured by each gray scale, measured the kickback voltage represented by the center point of the screen in three different samples.

Although there is a slight variation depending on the sample, it can be seen that the kickback voltage is remarkably small in a specific gradation, for example, 28 gradation, and the kickback voltage is considerably large in the vicinity of 20 and 36 to 42 gradations.

The information according to the gray scale is stored in the memory 650 in advance, and the signal controller 600 analyzes the gray scale distribution of the input image data R, G, and B, and then compensates the compensation control signal CONT3 accordingly. Export to section 700.

At this time, the compensation control signal CONT3 is a signal having a predetermined duty ratio, and the magnitude of the gate-on voltage Von is determined according to the width of the high section.

As described above, this is for adjusting the amount of kickback voltage in consideration of the amount of kickback voltage depending on the gray level. For example, the signal controller 600 may not emit the compensation control signal CONT3 when the image data R, G, and B are distributed near 28 gray levels, and may be near 20 gray levels or 36 to 42 gray levels. In the vicinity, the control signal CONT3 having the width W3 can be exported, and in the meantime, the control signal CONT3 having the width W2 can be exported.

When the control signal CONT3 having the width W1 is input, the transistor T2 is turned on to form a current path so that a current flowing to the third terminal of the transistor T1 is turned on with the resistor R2 and the transistor T2 turned on. To ground terminal. Accordingly, as shown in FIG. 5, the gate-on voltage V _on1 begins to decrease exponentially from the rising edge of the control signal CONT3, so that the gate-on voltage V _on1 becomes the voltage ( The voltage reduced by d1) is output as the gate on voltage V _on2 . In addition, when the control signal CONT3 has the width W2, the voltage reduced by the voltage d2 is output as the gate-on voltage V _on2 . Of course, when the width of the high section of the control signal CONT3 is 0, that is, when the signal controller CONT3 does not output the compensation control signal CONT3, the gate-on voltage V _on1 is _converted to the gate-on voltage V _on2. As it is.

The gate driver 400 generates a gate output Gout using the gate on voltage V _on2 and the gate off voltage Voff. At this time, for example, the gate output Gout (k) applied to the k-th gate line has a decrease d1 'slightly smaller than the decrease d1, and the (k + 1) th gate output Gout (k +1)] has a decrease d2 'slightly smaller than the decrease d2. This is because the reduction slope is the same but the gate output Gout has a width slightly smaller than 1H. In this case, as the kickback voltage is known, the kickback voltage is proportional to the difference between the gate on voltage and the gate off voltage, and thus, the kickback voltage may be reduced by the decreases d1 'and d2'.

On the other hand, in certain gray scales, for example, 16 gray scales or 32 gray _scales , the filling rate of the liquid crystal capacitor C _LC may be insufficient, so that defects such as spots may appear on the screen. In such gray scales, the compensation control signal CONT3 may not be emitted. It is preferable.

The gray scale analysis may be performed by using an adaptive color correction (ACC) or dynamic capacitance compensation (DCC) scheme, which is applied to a liquid crystal display device, and does not require an apparatus or algorithm for gray scale analysis. In this case, the reference gradation may be selected from among data forming one pixel row, and an average gray level of data constituting one pixel row may be used.

In addition, the compensation control signal CONT3 may be a gate clock signal CPV, an output enable signal OE, or a signal synchronized with the gate clock signal CPV.

As described above, in some gray levels in which the kickback voltage occurs, the flicker may be prevented by reducing the magnitude of the kickback voltage by reducing the difference between the gate on voltage Von and the gate off voltage Voff.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (8)

A driving device of a liquid crystal display device including a plurality of pixels each including a switching element, A gate driver for applying a gate voltage to the switching device; A compensator connected to the gate driver; A gate voltage generator connected to the compensator and the gate driver; A memory connected to the signal controller and storing kickback voltage information according to the gray scale; and A signal controller configured to generate a compensation control signal having a predetermined duty ratio based on the information from the memory and apply the compensation control signal to the compensation unit; Driving device for a liquid crystal display comprising a. In claim 1, And the gate voltage generator applies a first gate-on voltage to the compensator and a gate-off voltage to the gate driver. In claim 2, And the compensator is configured to receive the first gate-on voltage and send a second gate-on voltage according to the compensation control signal to the gate driver. In claim 3, The compensation unit A first transistor receiving the first gate-on voltage and transferring the first gate-on voltage to an output terminal; A second transistor connected to the output terminal through a predetermined resistor and operating according to the compensation control signal; Containing Driving device for liquid crystal display device. In claim 4, And the output terminal outputs the second gate on voltage. In claim 5, And a level of the second gate on voltage decreases when the second transistor is turned on according to the compensation control signal. In claim 6, The signal controller sends a gate control signal to the gate driver, The gate control signal includes a gate clock signal for controlling the output timing of the second gate on voltage and an output enable signal for defining a duration of the second gate on voltage. Driving device for liquid crystal display device. In claim 7, And the compensation control signal is the gate clock signal, the output enable signal, or a signal synchronized with the gate clock signal.

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