KR101012797B1 - Liquid crystal display - Google Patents

Abstract

The present invention relates to a liquid crystal display device comprising: a liquid crystal panel assembly including a plurality of pixels, a clock generator for generating a reference clock, and a swing common voltage based on the reference clock to generate the liquid crystal panel assembly It includes a common voltage generator for applying to. According to the present invention, it is possible to apply a normal pixel voltage to a pixel by generating a stable swing common voltage according to a fixed reference clock generated by the clock generator and applying the same to the pixel, thereby preventing a screen defect of the liquid crystal display device. Can be.

Liquid crystal display, reference clock, common voltage, swing, op amp, data voltage, pixel voltage

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY}

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3A is a waveform diagram showing waveforms of a data voltage and a swing common voltage in a normal case.

3B is a waveform diagram illustrating waveforms of a data voltage and a swing common voltage when the level of the swing common voltage is changed by an abnormal reset.

4A is a diagram illustrating a clock generator and a common voltage generator of a liquid crystal display according to another exemplary embodiment of the present invention.

FIG. 4B is a diagram showing the voltage waveform at one point V _comS of FIG. 4A.

4C is a diagram illustrating a swing common voltage V _{com that} is an output of the common voltage generator.

5 is a diagram illustrating a common voltage generator of a liquid crystal display according to another exemplary embodiment of the present invention.

6 is a diagram illustrating a common voltage generator of a liquid crystal display according to another exemplary embodiment of the present invention.

7 is a diagram illustrating a common voltage generator of a liquid crystal display according to another exemplary embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device generating a stable swing common voltage.

A typical liquid crystal display (LCD) includes two display panels provided with pixel electrodes and a common electrode, and a liquid crystal layer having dielectric anisotropy interposed therebetween. The pixel electrodes are arranged in a matrix and connected to switching elements such as thin film transistors (TFTs) to receive data voltages one by one in sequence. The common electrode is formed over the entire surface of the display panel and receives a common voltage. The pixel electrode, the common electrode, and the liquid crystal layer therebetween form a liquid crystal capacitor, and the liquid crystal capacitor becomes a basic unit that forms a pixel together with a switching element connected thereto.

In such a liquid crystal display, a voltage is applied to two electrodes to form an electric field in the liquid crystal layer, and the intensity of the electric field is adjusted to control the transmittance of light passing through the liquid crystal layer to obtain a desired image. At this time, in order to prevent deterioration caused by the application of an electric field in one direction to the liquid crystal layer for a long time, the polarity of the data voltage with respect to the common voltage is inverted frame by frame, row, or dot.

On the other hand, small and medium-sized liquid crystal display devices used in mobile phones and smart phones, and the like to swing the common voltage between a certain voltage level in order to reduce the power consumption, and applies a relatively low data voltage to the pixel to be opposite to the phase of the swing common voltage. In other words, if the data voltage is applied with a value of 0 to 5V, but the common voltage is swinged to -0.98V and 3.84V, the difference voltage between the common voltage and the data voltage is actually applied to the liquid crystal, so the common voltage is set to a constant voltage and the polarity of the data voltage. It has the same effect as driving by inverting.

However, when an abnormal signal is input to the liquid crystal display, the level of the swing common voltage changes. In particular, when the liquid crystal display is abnormally reset by physical shock or electromagnetic waves, the level of the swing common voltage is changed. In this case, even if the data voltage applied to the pixel is normal, the common voltage, which is the reference voltage, is shaken, so that the desired voltage is not applied to the pixel.

3A is a waveform diagram showing waveforms of a data voltage and a swing common voltage in a normal case. As shown in Figure 3A, the swing common voltage swings between -0.98V and 3.84V. 3B is a waveform diagram illustrating waveforms of a data voltage and a swing common voltage when the level of the swing common voltage is changed by an abnormal reset. As shown in FIG. 3B, the data voltage is the same as in FIG. 3A but the swing common voltage swings between -1.64V and 3.24V. As a result, a black shadow image phenomenon occurs in which a black shadow partially appears on the screen, and after-image defects may occur.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a liquid crystal display device which constantly fixes a level of a swing common voltage even when an abnormal signal is input to the liquid crystal display device.

The liquid crystal display according to an embodiment of the present invention for achieving the technical problem,

A liquid crystal panel assembly comprising a plurality of pixels,

A clock generator for generating a reference clock, and

And a common voltage generator configured to generate a swing common voltage based on the reference clock and apply the swing common voltage to the liquid crystal panel assembly.

Preferably, the period of the reference clock is the same as the period of the horizontal synchronization signal.

A signal control unit including a memory for storing the waveform of the horizontal synchronization signal;

Preferably, the clock generation section generates the reference clock in accordance with the waveform of the horizontal synchronization signal stored in the memory.

The clock generator may include an oscillator for generating the reference clock.

The clock generator may include a divider for dividing a main clock into the reference clock.

The common voltage generator includes a level stabilization circuit of the swing common voltage,

The level stabilization circuit may include a first resistor having one terminal connected to a first reference voltage, a second resistor having one terminal connected to a second reference voltage, and an inverting terminal connected to the other terminal of the first resistor. An operational amplifier having a non-inverting terminal connected to the other terminal of the second resistor and an output terminal connected to an output terminal of the common voltage generator, between the other terminal of the first resistor and the output terminal of the operational amplifier, Preferably includes a third resistor, and a fourth resistor connected between the other terminal of the second resistor and the ground.

The common voltage generator includes a first resistor having one terminal connected to the reference clock, an inverting terminal connected to the other terminal of the first resistor, a non-inverting terminal connected to the reference voltage, and the reference terminal through an output terminal. And an operational amplifier for amplifying the voltage level of the clock and outputting a signal shifted by the amplified voltage level, and a second resistor connected between the other terminal of the first resistor and the output terminal of the operational amplifier. Do.

The common voltage generator includes: a first resistor having one terminal connected to the reference clock; an inverting terminal connected to the other terminal of the first resistor; and a non-inverting terminal connected to the first reference voltage. A first operational amplifier configured to output a signal obtained by amplifying the voltage level of the reference clock, a second resistor connected between the other terminal of the first resistor and an output terminal of the first operational amplifier, and one terminal of the first operational amplifier; A third resistor connected to the output terminal of the amplifier, an inverting terminal connected to the other terminal of the third resistor, a non-inverting terminal connected to the second reference voltage, and shifting the level of the amplified signal through the output terminal A second operational amplifier, and a fourth resistor connected between the other terminal of the third resistor and the output terminal of the second operational amplifier. It is preferred.

According to another embodiment of the present invention,

A liquid crystal panel assembly comprising a plurality of pixels,

A clock generator for generating a reference clock,

A common voltage generator configured to generate a swing common voltage based on the reference clock and apply the swing common voltage to the liquid crystal panel assembly;

A data driver which applies a data voltage corresponding to image data to the pixel, and

A signal controller for transmitting the image data to the data driver

Including;

The clock generator, the common voltage generator, the data driver, and the signal controller are configured as a single chip.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.                     

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A liquid crystal display according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of a liquid crystal display device according to an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of a pixel of a liquid crystal display device according to an embodiment of the present invention.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a common voltage generation connected thereto. The unit 700 includes a gray voltage generator 800 connected to the data driver 500, and a signal controller 600 for controlling the gray voltage generator 800.

The liquid crystal panel assembly 300 includes a plurality of display signal lines G ₁ -G _n , D ₁ -D _m and a plurality of pixels connected to the plurality of display signal lines G ₁ -G _n , D ₁ -D _m , and arranged in a substantially matrix form. .

The display signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n for transmitting a gate signal (also called a “scan signal”) and a data signal line or data for transmitting a data signal. Line D ₁ -D _m . The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel includes a switching element Q connected to a display signal line G ₁ -G _n , D ₁ -D _m , and a liquid crystal capacitor C _LC and a storage capacitor C _ST connected thereto. It includes. The holding capacitor C _ST can be omitted as necessary.

The switching element Q is provided on the lower panel 100, and the control terminal and the input terminal are connected to the gate line G ₁ -G _n and the data line D ₁ -D _m, respectively. The output terminal is connected to the liquid crystal capacitor C _LC and the storage capacitor C _ST .

The liquid crystal capacitor C _LC has two terminals, the pixel electrode 190 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 190 and 270. It functions as a dielectric. The pixel electrode 190 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives a common voltage V _com . Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, both electrodes 190 and 270 may be linear or rod-shaped.

The storage capacitor C _ST is formed by overlapping a separate signal line (not shown) and the pixel electrode 190 provided on the lower panel 100, and the predetermined signal line such as a common voltage V _com is provided on the separate signal line. Is applied. However, the storage capacitor C _ST may be formed such that the pixel electrode 190 overlaps the front end gate line directly above the insulator.

Meanwhile, in order to implement color display, each pixel must display color, which is possible by providing a red, green, or blue color filter 230 in a region corresponding to the pixel electrode 190. In FIG. 2, the color filter 230 is formed in a corresponding region of the upper panel 200. Alternatively, the color filter 230 may be formed above or below the pixel electrode 190 of the lower panel 100.

A polarizer (not shown) for polarizing light is attached to an outer surface of at least one of the two display panels 100 and 200 of the liquid crystal panel assembly 300.

The gray voltage generator 800 generates two sets of gray voltages related to the transmittance of the pixel. One of the two sets has a positive value for the common voltage (V _com ) and the other set has a negative value.

The gate driver 400 is connected to the gate lines G ₁ -G _n of the liquid crystal panel assembly 300 to receive a gate signal formed by a combination of a gate on voltage V _on and a gate off voltage V _off from the outside. It is applied to the gate lines G ₁ -G _n and usually consists of a plurality of integrated circuits.

The data driver 500 is connected to the data lines D ₁ -Dm of the liquid crystal panel assembly 300 to select the gray voltage from the gray voltage generator 800 and apply the gray voltage to the pixel as a data signal. Is made of.

A plurality of gate drive integrated circuits or data drive integrated circuits may be mounted in a tape carrier package (TCP) (not shown) to attach TCP to the liquid crystal panel assembly 300, or to integrate these onto a glass substrate without using TCP. Circuits may be directly attached (chip on glass, COG mounting method), and circuits performing the same functions as those integrated circuits may be directly mounted on the liquid crystal panel assembly 300.

In particular, only the gate driver 400 is formed of amorphous silicon together to form a switching element in order to reduce the cost and reduce the cost and demand of a narrow bezel to reduce the area of the screen outer frame. May be integrated on the same substrate.

The signal controller 600 generates control signals for controlling operations of the gate driver 400 and the data driver 500, and provides the corresponding control signals to the gate driver 400 and the data driver 500.

The common voltage generator 700 generates a swing common voltage V _com having an appropriate value corresponding to the data voltage and supplies the generated common voltage V _com to the liquid crystal panel assembly 300. This will be described in detail later.

Next, the display operation of the liquid crystal display will be described in more detail.

The signal controller 600 inputs an input control signal for controlling the RGB image signals R, G, and B and their display from an external graphic controller (not shown), for example, a vertical sync signal V _sync and a horizontal sync signal. (H _sync ), a main clock (MCLK), a data enable signal (DE) is provided. The signal controller 600 properly processes the image signals R, G, and B according to the operating conditions of the liquid crystal panel assembly 300 based on the input image signals R, G, and B and the input control signal, and controls the gate control signal. After generating the CONT1 and the data control signal CONT2 and the like, the gate control signal CONT1 is sent to the gate driver 400 and the data control signal CONT2 and the processed image signals R ', G', and B 'are processed. ) Is sent to the data driver 500.

The gate control signal CONT1 includes a vertical synchronization start signal STV for indicating the start of output of the gate-on pulse (high period of the gate signal), a gate clock signal CPV for controlling the output timing of the gate-on pulse, and a gate-on pulse. And an output enable signal OE that defines the width of the signal.

The data control signal CONT2 is a load for applying a corresponding data voltage to the horizontal synchronization start signal STH indicating the start of input of the image data R ', G', and B 'and the data lines D ₁ -D _m . Signal LOAD, inverted signal RVS and data that inverts the polarity of the data voltage with respect to common voltage V _com (hereinafter referred to as " polarity of data voltage " by reducing " polarity of data voltage with respect to common voltage "). Clock signal HCLK and the like.

The data driver 500 sequentially receives image data R ′, G ′, and B ′ corresponding to one row of pixels according to the data control signal CONT2 from the signal controller 600, and generates a gray voltage generator ( The image data R ', G', B 'is converted into the corresponding data voltage by selecting the gray voltage corresponding to each of the image data R', G ', and B' among the gray voltages from the 800.

The gate driver 400 applies the gate-on voltage V _on to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n. Turn on the switching element (Q) connected to.

The gate-on voltage V _on is applied to one gate line G ₁ -G _n so that a row of switching elements Q connected thereto is turned on (this period is "1H" or "1 horizontal period). (horizontal period) "and equal to one period of the horizontal sync signal Hsync, the data enable signal DE, and the gate clock CPV], and the data driver 500 converts each data voltage to a corresponding data line D. ₁ -D _m ). The data voltage supplied to the data lines D ₁ -D _m is applied to the corresponding pixel through the turned-on switching element Q.

In this manner, the gate-on voltages V _{on are} sequentially applied to all the gate lines G ₁ -G _n during one frame to apply data voltages to all the pixels. At the end of one frame, the next frame starts and the state of the inversion signal RVS applied to the data driver 500 is controlled so that the polarity of the data voltage applied to each pixel is opposite to that of the previous frame ("frame inversion). "). In this case, the polarity of the data voltage flowing through one data line may be changed (“line inversion”) within one frame or the polarity of the data voltage applied to one pixel row may be different according to the characteristics of the inversion signal RVS ( "Dot reversal").

Next, the clock generator and the common voltage generator of the liquid crystal display according to the exemplary embodiment of the present invention will be described with reference to FIGS. 4A to 4C. This liquid crystal display generates a common voltage V _com which swings based on the reference clock from the clock generator.

4A is a diagram illustrating a clock generator 40 and a common voltage generator 700 of a liquid crystal display according to another exemplary embodiment of the present invention, and FIG. 4B is a voltage at a point V _comS of FIG. 4A. 4C is a diagram illustrating a waveform, and FIG. 4C illustrates a swing common voltage V _com which is an output of the common voltage generator 700.

As shown in FIG. 4A, the common voltage generator 700 includes four resistors R1, R2, R3, and R4, two capacitors C1 and C2, a switch S, and an amplifier AMP1.

One end of the resistor R1 is connected to the power supply voltage V _DH , the other end is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to ground. The input terminal of the amplifier AMP1 is connected between the resistor R1 and the resistor R2 connected in series, the output terminal is connected to one end of the capacitor C1, and the other end of the capacitor C1 It is connected to ground. One end of the switch S is connected to the output terminal of the amplifier AMP1 and the other end is connected to the ground, and the output terminal of the switch S is connected to the output clock of the switch S according to the reference clock from the clock generator 40. One end or the other end. One end of the resistor R3 is connected to the power supply voltage V _DH , the other end is connected to one end of the resistor R4, and the other end of the resistor R4 is connected to ground. One end of the capacitor C2 is connected to the output terminal of the switch S, the other end is connected between the resistor R3 and the resistor R4 connected in series, and this point P1 generates a common voltage. It becomes an output terminal of the part 700.

The power supply voltage V _DH is divided by the resistor R1 and the resistor R2, and the amplifier AMP1 amplifies the divided voltage to an appropriate magnitude. The switch S switches the output terminal and the output terminal of the amplifier AMP1 and ground once per clock with respect to the reference clock from the clock generator 40. Then, as shown in Fig. 4B, the output waveform V _comS of the switch S is outputted with a voltage waveform swinging at a value of 0 V and V _{com R} V.

This voltage waveform is then passed through a capacitor C2, and the voltage level is lowered by the resistors R3 and R4 and output as a swinging common voltage V _com as shown in FIG. 4C. The voltage level is lowered by a level corresponding to the kickback voltage V _kb due to the parasitic capacitance of the pixel. As a result, the swing common voltage (V _com ) swings between -0.98V and 3.84V levels.

As such, when the common voltage V _com is _swinged between predetermined voltage levels, the polarity of the data voltage does not need to be inverted for line inversion and dot inversion. That is, in general, in order to perform line inversion and dot inversion, the common voltage V _com is kept constant, and the positive and negative voltages are applied to the pixel with the data voltage as a value between -5V and 5V. However but swings between a common voltage (V _com) of -0.98V and 3.84V level in place of the common voltage (V _com) establishing a data voltage to this take a positive voltage to the pixel when the -0.98V, and a common voltage When (V _com ) is 3.84V, a data voltage is set and applied so that a negative voltage is applied to the pixel. Then, the data voltage has a value between 0V and 5V, not a value between -5V and 5V, so that line inversion and dot inversion can be sufficiently performed as above. Therefore, the level of the data voltage can be reduced by half, and as a result, when the level of the data voltage is reduced, power consumption of the liquid crystal display is reduced.

On the other hand, the clock generator 40 generates a reference clock to generate a swing common voltage (V _com ) and transfers it to the switch (S) of the common voltage generator 700. The frequency of the reference clock is set equal to the frequency of the horizontal sync signal H _sync .

The clock generator 40 may generate the reference clock in various ways. For example, the clock generator 40 may include an oscillator as the reference clock as an output clock from the oscillator. The oscillator generates a fixed clock, which may be an LC oscillator, an RC oscillator, a Wien bridge type oscillator, a crystal oscillator, or the like.

As another example, the clock generator 40 may include a divider to generate a reference clock. The divider is a device that senses a given frequency at a low frequency forming an integer ratio with it. The clock generator 40 inputs the main clock MCLK to the divider and outputs a divided reference clock to have the same frequency as that of the horizontal sync signal H _sync .

As another example, a reference clock is generated using a memory included in the signal controller 600. That is, a waveform of one cycle of the horizontal synchronization signal H _sync is stored in the memory, and the waveform is repeatedly outputted to generate a reference clock having the same frequency as the frequency of the horizontal synchronization signal H _sync .

As such, the clock generator 40 generates a fixed reference clock and outputs the fixed reference clock to the common voltage generator 700. The common voltage generator 700 also generates a fixed swing common voltage V _com according to the reference clock. Therefore, a stable data voltage is applied to the pixel.

When generating a common voltage (V _com) on the basis of the horizontal synchronizing signal (H _sync) and a data enable signal (DE) from the external apparatus, horizontal synchronizing signal (H _sync) due to disturbance such as noise or shock, or data When the enable signal DE is abnormally input, the common voltage V _com may become unstable accordingly, and an unwanted pixel voltage may be applied, thereby causing a defect on the screen of the liquid crystal display. However, according to an exemplary embodiment of the present invention, such a screen failure may be prevented by the clock generator 40 generating a fixed reference clock and thereby generating a swing common voltage V _com .

Next, the common voltage generator of the liquid crystal display according to the exemplary embodiment of the present invention will be described with reference to FIG. 5. The liquid crystal display includes an operational amplifier at an output terminal of the common voltage generator so that the common voltage V _com is stably output.

5 is a diagram illustrating a common voltage generator 700 of a liquid crystal display according to another exemplary embodiment of the present invention.

As shown in FIG. 5, the common voltage generator 700 includes six resistors R1, R2, R3, R4, R5, and R6, two capacitors C1 and C2, a switch S, and an amplifier AMP1. , And op amps. Since the two resistors R1 and R2, the two capacitors C1 and C2, the switch S, and the amplifier AMP1 have the same connection relationship as in the previous embodiment, description thereof is omitted.

One end of the resistor R3 is connected to the power supply voltage V _DH , and the other end is connected to the inverting terminal of the operational amplifier OPAMP. One end of the resistor R4 is connected to the reference voltage V _ref , and the other end is connected to the non-inverting terminal of the operational amplifier OPAMP. The resistor R5 is connected between the inverting terminal of the operational amplifier OPAMP and the output terminal, and the resistor R6 is connected between the non-inverting terminal of the operational amplifier OPAMP and ground. The output terminal of the operational amplifier OPAMP is connected to the other end of the capacitor C2 and outputs a swing common voltage V _com .

The operational amplifier OPAMP having such a structure lowers the level of the output voltage of the switch S by a level corresponding to the kickback voltage V _kb , as shown in FIG. 4C, and at the output terminal of the common voltage generator 700. It serves to fix the DC component of the voltage. Accordingly, the swing common voltage V _com is stably applied to the liquid crystal panel assembly 300 even in a disturbance caused by noise.

The clock generator 40 shown in FIG. 5 also generates a reference clock having the same frequency as the horizontal sync signal H _{sync in the} same manner as in the previous embodiment, and transmits the reference clock to the common voltage generator 700.

Next, the common voltage generator 700 of the liquid crystal display according to the exemplary embodiment of the present invention will be described with reference to FIG. 6. The common voltage generator 700 generates a swing common voltage V _com using two operational amplifiers.

6 is a diagram illustrating a common voltage generator 700 of a liquid crystal display according to another exemplary embodiment of the present invention.

As shown in FIG. 6, the common voltage generator 700 includes four resistors R1, R2, R3, and R4 and two operational amplifiers OPAMP1 and OPAMP2.

One end of the resistor R1 is connected to the clock generator 40, and the other end is connected to the inverting terminal of the operational amplifier OPAMP1. The resistor R2 is connected between the inverting terminal and the output terminal of the operational amplifier OPAMP1. The non-inverting terminal of the operational amplifier OPAMP1 is connected to the reference voltage V _ref1 , and the output terminal is connected to one end of the resistor R3. The other end of the resistor R3 is connected to the inverting terminal of the operational amplifier OPAMP2, and the resistor R4 is connected between the inverting terminal and the output terminal of the operational amplifier OPAMP2. The non-inverting terminal of the operational amplifier OPAMP2 is connected to the reference voltage V _ref2 and outputs a swing common voltage V _com through the output terminal.

The clock generator 40 shown in FIG. 6 also generates a reference clock having the same frequency as the horizontal sync signal H _{sync in the} same manner as in the previous embodiment, and transmits the reference clock to the common voltage generator 700.

The operational amplifier OPAMP1 receives the reference clock from the clock generator 40 through the resistor R1 and amplifies the reference clock to a predetermined level, and outputs the voltage waveform shown in FIG. 4B to the output terminal. The operational amplifier OPAMP2 receives the output voltage from the operational amplifier OPAMP1 through the resistor R3 and lowers the voltage level corresponding to the kickback voltage V _kb to output the swing common voltage V _com shown in FIG. 4C. .

The common voltage generator 700 of the present embodiment also maintains the output common voltage V _com through the operational amplifier in the same manner as in the previous embodiment, thereby stably applying the swing common voltage V _com to the pixel.

Next, the common voltage generator of the liquid crystal display according to the exemplary embodiment of the present invention will be described with reference to FIG. 7. The common voltage generator generates a swing common voltage V _com using one operational amplifier.

FIG. 7 is a diagram illustrating a common voltage generator 700 of a liquid crystal display according to another exemplary embodiment of the present invention.

As shown in FIG. 7, the common voltage generator 700 of the present embodiment includes two resistors R1 and R2 and an operational amplifier OPAMP.

One end of the resistor R1 is connected to the clock generator 40, and the other end is connected to the inverting terminal of the operational amplifier OPAMP. The resistor R2 is connected between the inverting terminal of the operational amplifier OPAMP and the output terminal, and the non-inverting terminal of the operational amplifier OPAMP is connected to the reference voltage V _ref . The operational amplifier OPAMP outputs a swing common voltage V _com through an output terminal.

The clock generator 40 shown in FIG. 7 also generates a reference clock having the same frequency as the horizontal sync signal H _{sync in the} same manner as in the previous embodiment, and transmits the reference clock to the common voltage generator 700.

The operational amplifier OPAMP receives the reference clock from the clock generator 40 through the resistor R1 and amplifies the reference clock to a predetermined level, and adjusts the input voltage input to the operational amplifier OPAMP to adjust the output level to the kickback voltage ( Lowering the voltage level corresponding to V _kb ) outputs the swing common voltage V _com shown in FIG. 4C.

The common voltage generator 700 of the present embodiment also maintains the output common voltage V _com through the operational amplifier in the same manner as in the previous embodiment, thereby stably applying the swing common voltage V _com to the pixel. In addition, the present embodiment has a simpler circuit structure since only one operational amplifier can be used, unlike in the previous embodiment.

Meanwhile, the clock generator 40, the common voltage generator 700, the data driver 500, and the signal controller 600 of the liquid crystal display according to the present invention may be formed of a single chip, also called a one-chip. . By integrating all the blocks for driving the liquid crystal display in one chip, the mounting area can be reduced and power consumption can be reduced. Of course, if necessary, the circuit elements used in each driving block may be placed outside a single chip. Such a single chip is particularly advantageous in small and medium sized liquid crystal displays.

In conclusion, according to the present invention, the clock generator generates a fixed reference clock, and the common voltage generator generates a stable swing common voltage accordingly as shown in FIG. 3A. When the swing common voltage is stabilized, screen failure of the liquid crystal display may be prevented.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, a normal swing voltage may be applied to the pixel by generating a stable swing common voltage according to the fixed reference clock generated by the clock generator and applying the same to the pixel. Therefore, screen failure of the liquid crystal display device can be prevented.

Claims (9)

A liquid crystal panel assembly comprising a plurality of pixels, Signal controller, A clock generator for generating a reference clock, and A common voltage generator configured to generate a swing common voltage based on the reference clock and apply the swing common voltage to the liquid crystal panel assembly Including, The period of the reference clock is the same as the period of the horizontal synchronization signal, The signal controller includes a memory for storing a waveform of the horizontal synchronizing signal, And the clock generation section generates the reference clock in accordance with the waveform of the horizontal synchronization signal stored in the memory. delete delete delete delete In claim 1, The common voltage generator includes a level stabilization circuit of the swing common voltage, The level stabilization circuit may include a first resistor having one terminal connected to a first reference voltage, a second resistor having one terminal connected to a second reference voltage, and an inverting terminal connected to the other terminal of the first resistor. An operational amplifier having a non-inverting terminal connected to the other terminal of the second resistor and an output terminal connected to an output terminal of the common voltage generator, between the other terminal of the first resistor and the output terminal of the operational amplifier, A third resistor, and a fourth resistor connected between the other terminal of the second resistor and the ground. Liquid crystal display. In claim 1, The common voltage generator includes a first resistor having one terminal connected to the reference clock, an inverting terminal connected to the other terminal of the first resistor, a non-inverting terminal connected to the reference voltage, and the reference terminal through an output terminal. A liquid crystal display including an operational amplifier for amplifying a voltage level of a clock and outputting a signal shifted by the amplified voltage level, and a second resistor connected between the other terminal of the first resistor and an output terminal of the operational amplifier Device. In claim 1, The common voltage generator includes: a first resistor having one terminal connected to the reference clock; an inverting terminal connected to the other terminal of the first resistor; and a non-inverting terminal connected to the first reference voltage. A first operational amplifier configured to output a signal obtained by amplifying the voltage level of the reference clock, a second resistor connected between the other terminal of the first resistor and an output terminal of the first operational amplifier, and one terminal of the first operational amplifier; A third resistor connected to the output terminal of the amplifier, an inverting terminal connected to the other terminal of the third resistor, a non-inverting terminal connected to the second reference voltage, and shifting the level of the amplified signal through the output terminal A second operational amplifier, and a fourth resistor connected between the other terminal of the third resistor and the output terminal of the second operational amplifier. Crystal display device. A liquid crystal panel assembly comprising a plurality of pixels, A clock generator for generating a reference clock, A common voltage generator configured to generate a swing common voltage based on the reference clock and apply the swing common voltage to the liquid crystal panel assembly; A data driver which applies a data voltage corresponding to image data to the pixel, and A signal controller for transmitting the image data to the data driver Including; The clock generator, the common voltage generator, the data driver, and the signal controller may be formed of a single chip. The period of the reference clock is the same as the period of the horizontal synchronization signal, The signal controller includes a memory for storing a waveform of the horizontal synchronizing signal, The clock generation unit generates the reference clock according to the waveform of the horizontal synchronization signal stored in the memory. Liquid crystal display.

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