KR20060018391A - Display device - Google Patents

Abstract

The present invention relates to a display device.

A plurality of pixels, a reference voltage generator for generating a plurality of reference voltages, and dividing the reference voltages to generate a plurality of gray voltages, and selecting a gray voltage corresponding to image data among the gray voltages as a data voltage, And a data controller configured to apply the data driver, a selector connected to the reference voltage generator, and a signal controller configured to generate and apply a control signal for controlling the image data.

In this way, by storing a plurality of gamma curve data in the reference voltage generation unit and selecting the same through the selection unit, it is possible to compensate when the value of the memory included in the signal controller is incorrect, while simplifying the function of the signal controller. The signal control unit can be used efficiently, thereby improving the display quality of the display device.

Display, digital, analog, reference voltage, gradation voltage, memory, gamma curve

Description

Display device {DISPLAY DEVICE}

1 is a block diagram of a display device according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a schematic diagram of a display device according to an exemplary embodiment of the present invention.

4 is a diagram illustrating an example of a circuit of the selector and the reference voltage generator shown in FIG. 3.

The present invention relates to a display device and a driving device thereof.

Recently, organic electroluminescence display (OLED), plasma display panel (PDP), liquid crystal display (LCD), instead of heavy and large cathode ray tube (CRT) Flat panel display devices such as are being actively developed.

PDP is a device for displaying characters or images using plasma generated by gas discharge, and the organic EL display device displays characters or images by using electroluminescence of specific organic materials or polymers. The liquid crystal display device applies an electric field to a liquid crystal layer interposed between two display panels, and adjusts the intensity of the electric field to adjust a transmittance of light passing through the liquid crystal layer to obtain a desired image.

Among such flat panel display devices, for example, a liquid crystal display and an organic EL display device may turn on / off a switching element of a pixel by emitting a gate signal to a pixel including a switching element, a display panel provided with a display signal line, and a gate line among the display signal lines. The gate driver to turn off, the reference voltage generator for generating a plurality of gray reference voltages, and the reference voltages from the reference voltage generator are divided to generate a plurality of gray voltages, and among the gray voltages, a gray voltage corresponding to an image signal is selected. A data driver applied to the pixel, and a signal controller generating a control signal for controlling the pixel driver.

At this time, recently, a signal controller or the like has a memory and digitally stores information on a gamma curve for generating transmittance or luminance suitable for a display device, and sends the digital information to a reference voltage generator. The voltage generator generates an analog reference voltage based on this digital information.

However, since the information stored in the memory is based on the information generated in generating the analog reference voltage, an optimized image may not be obtained when the information stored in the memory differs from the gamma curve actually displayed by the display device.

In order to improve the problem, the signal controller may be divided into several areas to input and use different data, but in this case, the cost of the signal controller increases and there is a problem in that the signal controller cannot be efficiently used.

In addition, since most of the memory included in the signal controller is read only memory (ROM), it is not easy to modify data. To solve this problem, a gamma curve may be stored in an additional memory EEPROM (electrically erasable and programmable ROM). However, even in this case, the auxiliary memory may be expensive or there may be no auxiliary memory at all.

Accordingly, the technical problem to be achieved by the present invention is to provide a display device that can solve the problems of the prior art.

According to an embodiment of the present invention, a display device includes a memory storing a plurality of pixels and a plurality of gamma data for adjusting luminance of the display device, wherein the gamma data from the memory is stored. A reference voltage generator configured to generate a plurality of reference voltages based on the divided reference voltages, and divide the reference voltages to generate a plurality of gray voltages, and select a gray voltage corresponding to image data among the gray voltages as a data voltage and apply the same to the pixel; A data driver, a selector connected to the reference voltage generator, and a signal controller configured to generate a control signal for controlling the image data and apply the control signal to the data driver.

In this case, the reference voltage generator includes a logic unit connected between the selector and the memory, first and second registers connected to the memory and sequentially receiving and storing the gamma data from the memory. First and second demultiplexers connected to a second resistor, first and second resistor strings connected to the first and second demultiplexers, respectively, and including a plurality of resistors, the first and second demultiplexers. An amplifier which is connected to an output terminal of the neutralizer and which amplifies a voltage output through the first and second switching elements, which are opened and closed according to a control signal from the second register, and the first or second switching element. It may further include.

Here, the selector may apply a signal for selecting any one of the plurality of gamma data stored in the memory through the logic unit, and the selector may further include third and fourth switching connected in series between a high voltage and a low voltage. And a contact point of the third and fourth switching elements may be connected to the logic unit, and the third and fourth switching elements may be different kinds of transistors.

Alternatively, the selector may include a resistor string connected in series between a high voltage and a low voltage, and the center of the resistor string may be connected to the logic unit.

On the other hand, the logic unit may be an AND circuit having one end connected to a high voltage and the other end connected to the selection unit, or a logic sum circuit having one end connected to a low voltage and the other end connected to the selection unit.

The gamma data is a 10-bit digital signal, the most significant bit of the 10 bits may be used to select the first and second switching elements, and the remaining 9 bits may be used to select a part of voltage divided by the resistor string. .

The data driver may include a plurality of data driver integrated circuits, and each data driver integrated circuit may be connected to the signal controller through two buses.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A display device according to an embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a block diagram of a display device according to an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of one pixel of a liquid crystal display device according to an embodiment of the present invention, and FIG. 3 is an embodiment of the present invention. A schematic diagram of a display device according to the present invention.

As shown in FIG. 1, a display device according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver 500 connected thereto. The reference voltage generator 800 connected to the signal control unit 600 for controlling them.                     

The display panel unit 300 includes a plurality of display signal lines G ₁ -G _n , D ₁ -D _m and a plurality of pixels Px connected to the plurality of display signal lines G ₁ -G _n and D ₁ -D _m in an equivalent circuit.

The display signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n for transmitting a gate signal (also called a “scan signal”) and a data signal line or data for transmitting a data signal. Line D ₁ -D _m . The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel includes a switching element Q connected to a display signal line G ₁ -G _n , D ₁ -D _m , and a pixel circuit connected thereto.

The switching element Q is a three-terminal element whose control terminal and input terminal are connected to the gate line G ₁ -G _n and the data line D ₁ -D _m, respectively, and the output terminal is connected to the pixel circuit. have. In addition, the switching element Q is preferably a thin film transistor, and particularly preferably comprises amorphous silicon.

In the case of a liquid crystal display, which is a representative example of a flat panel display, the lower panel 100, the upper panel 200, and a liquid crystal layer 3 therebetween are included as shown in FIG. 2. The display signal lines G ₁ -G _n , D ₁ -D _m and the switching elements Q are provided on the lower display panel 100. The pixel circuit of the liquid crystal display device includes a liquid crystal capacitor C _LC and a storage capacitor C _ST connected to the switching element Q. The holding capacitor C _ST can be omitted if necessary.

The liquid crystal capacitor C _LC has two terminals, the pixel electrode 190 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 190 and 270. It functions as a dielectric. The pixel electrode 190 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives a common voltage V _com . Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, both electrodes 190 and 270 may be linear or rod-shaped.

The storage capacitor C _ST is formed by overlapping a separate signal line (not shown) and the pixel electrode 190 provided on the lower panel 100, and a predetermined voltage such as a common voltage V _com is applied to the separate signal line. Is approved. However, the storage capacitor C _ST may be formed such that the pixel electrode 190 overlaps the front end gate line directly above the insulator.

On the other hand, in order to implement color display, each pixel should be able to display color, which is provided with a color filter 230 of three primary colors, for example, red, green, or blue, in a region corresponding to the pixel electrode 190. It is possible by doing. In FIG. 2, the color filter 230 is formed on the upper panel 200. Alternatively, the color filter 230 may be formed above or below the pixel electrode 190 of the lower panel 100.

Polarizers (not shown) for polarizing light are attached to outer surfaces of at least one of the two display panels 100 and 200 of the display panel unit 300 of the liquid crystal display device.                     

Referring back to FIG. 1, the reference voltage generator 800 generates one or two gray level voltages related to the luminance of the pixel. If there are two sets, one of the sets has a positive value for the common voltage (V _com ) and the other set has a negative value.

The selector 700 selects an operation of the reference voltage generator 800 to cause the reference voltage generator 800 to generate a reference voltage suitable for the luminance characteristic of the display device.

The gate driver 400 is connected to the gate lines G ₁ -G _n of the display panel 300 to gate a gate signal formed by a combination of a gate on voltage V _on and a gate off voltage V _off from the outside. Applies to lines G ₁ -G _n . The gate driver 400 includes a plurality of stages substantially arranged in a row as a shift register. As shown in FIG. 3, the gate driver 400 is mounted on both left and right sides of the display panel 300. The gate driving sections 401 and 402 are divided, and the voltage from the signal controller 600 is supplied through the level shifter 610, respectively.

The data driver 500 includes a plurality of data driver ICs 501-508 mounted on the display panel 300, and is connected to the data lines D ₁ -D _m of the display panel 300 to generate a reference voltage. The reference voltage from the unit 800 is divided into a plurality of gray voltages, and a gray voltage corresponding to an image signal among the gray voltages is selected and applied to the pixel as a data signal.

Each of the driving ICs 501-508 is connected to the reference voltage generator 800, and two buses from the reference voltage generator 800 are divided and connected to each of the driving ICs 501-508.

Each driving IC 501-508 is also connected to the signal controller 600 to receive image data and data control signals. The data control signal is, for example, a two-bit clock signal, and has a structure in which a bus from the signal controller 600 is divided and connected to each data driving IC 501-508. The image data is supplied from the signal controller 600 to the data driver ICs 501-508 through two wires that are separately provided between the data driver ICs 501-508 and the signal controller 600.

The signal controller 600 controls operations of the gate driver 400 and the data driver 500.

The display operation of such a display device will now be described in more detail.

The signal controller 600 inputs an input control signal for controlling the RGB image signals R, G, and B and their display from an external graphic controller (not shown), for example, a vertical sync signal V _sync and a horizontal sync signal. (H _sync ), a main clock (MCLK), a data enable signal (DE) is provided. The signal controller 600 generates a gate control signal CONT1 and a data control signal CONT2 based on the input control signal and the input image signals R, G, and B, and generates the image signals R, G, and B. After appropriately processing the display panel 300 according to the operating conditions, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are transferred to the data driver 500. Export.

The gate control signal (CONT1) is the gate-on start vertical sync indicating the start of output of a voltage (V _on) signal (STV), a gate-on voltage gated clock signal that controls the output timing of the (V _on) (CPV) and the gate An output enable signal OE or the like that defines the duration of the on voltage V _on .

The data control signal CONT2 is a load signal LOAD and a data clock signal for applying a corresponding data voltage to the horizontal synchronization start signal STH indicating the start of input of the image data DAT and the data lines D ₁ -D _m . (HCLK). In the case of the liquid crystal display or the like shown in FIG. 2, the polarity of the data voltage with respect to the common voltage V _com (hereinafter referred to as "polarization of the data voltage" by reducing the "polarity of the data voltage with respect to the common voltage") is inverted. The inversion signal RVS may also be included.

The data driver 500 sequentially receives the image data DAT corresponding to one row of pixels according to the data control signal CONT2 from the signal controller 600, and receives the reference voltage from the reference voltage generator 800. By dividing the voltage into a plurality of gray voltages and selecting a gray voltage corresponding to each image data DAT among the gray voltages, the image data DAT is converted into a corresponding data voltage and applied to the data lines D ₁ -D _m . do.

The gate driver 400 applies the gate-on voltage V _on to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n. Turn on the switching element (Q) connected to. The data voltage supplied to the data lines D ₁ -D _m is applied to the corresponding pixel through the turned-on switching element Q.

In the case of the liquid crystal display of FIG. 2, the difference between the data voltage applied to the pixel and the common voltage V _com is shown as the charging voltage of the liquid crystal capacitor C _LC , that is, the pixel voltage. The liquid crystal molecules vary in arrangement depending on the magnitude of the pixel voltage. As a result, the polarization of light passing through the liquid crystal layer 3 changes. The change in polarization is represented by a change in transmittance of light by a polarizer (not shown) attached to the display panels 100 and 200.

After one horizontal period (or “1H”) (one period of the horizontal sync signal H _sync , the data enable signal DE, and the gate clock CPV), the data driver 500 and the gate driver 400 are next. The same operation is repeated for the pixels in the row. In this manner, the gate-on voltages V _{on are} sequentially applied to all the gate lines G ₁ -G _n during one frame to apply data voltages to all the pixels. In the case of the liquid crystal display shown in FIG. 2, in particular, when one frame ends, the next frame starts and an inversion signal applied to the data driver 500 such that the polarity of the data voltage applied to each pixel is opposite to the polarity of the previous frame. The state of (RVS) is controlled ("frame inversion"). At this time, the polarity of the data voltage flowing through one data line is changed according to the characteristics of the inversion signal RVS even in one frame (eg, "row inversion", "point inversion"), The polarities can also be different (eg "invert columns", "invert points")

Next, a driving device of the display device according to an exemplary embodiment of the present invention will be described in more detail with reference to FIG. 4.

FIG. 4 is an example of a circuit diagram of the selector and the reference voltage generator shown in FIG. 3.                     

As shown in FIG. 4, the selector 700 includes a resistor string in which a plurality of resistors R1 and R2 are connected in series. A high voltage VDD is connected to one end of the resistor string and the other end is grounded. The center of the resistor string is connected to the logic unit 870.

The reference voltage generator 800 is connected to the logic unit 870, a memory 810 connected thereto, and a pair of gamma registers 820 and 830 and a rear gamma register 830 connected to each other by a 10-bit bus. The demultiplexers 840 and 850 and a plurality of resistor rows 841 and 851 connected to the demultiplexers 840 and 850 are included.

The logic unit 870 includes a certain logic circuit, and may be, for example, an AND circuit or an OR circuit. In the case of an AND circuit, one end of the AND circuit is connected to a high voltage and the other end is connected to the center of the resistor string so that the operation of the memory 810 may be selected according to the voltage of the other end. Alternatively, in the case of an OR circuit, one end of the OR circuit may be grounded and the other end may be connected to the center of the resistor string to select an operation of the memory 810 according to the voltage of the other end.

The memory 810 stores digital values for certain gamma curves, for example gamma 2.2 and gamma 2.6.

The gamma registers 820 and 830 are connected to the memory 810 by two buses to receive and store digital gamma curve data from the memory 810 separately for each of R, G, and B.

The demultiplexers 840 and 850 convert the analog voltages by selecting some of the voltages divided by the resistor strings 841 and 851 using the digital values stored in the gamma registers 820 and 830 as selection signals, thereby converting the two bus wirings. Outputs to the data driver 500 through. For example, as shown, one bit of data of 10 bits is used as a selection signal for opening and closing the switching elements SW1 and SW2, and the remaining 9 bits are used as selection signals of the demultiplexers 840 and 850. In the case of 9 bits, all 512 can be selected.

Both ends of each of the resistor strings 841 and 851 are connected to constant reference voltages VREF1, VREF2, VREF3 and VREF4, respectively, and the centers of the resistor strings 841 and 851 are respectively fixed to the constant center voltages VCNT1 and VCNT2. It is connected.

In this case, the demultiplexer 840 may output 8 positive reference voltages, and the demultiplexer 850 may output 8 negative reference voltages, respectively, and the output analog voltage GMA_IN may be buffered. Amplified through 860.

Meanwhile, the selector 700 substantially selects the operation of the memory 810. When the gamma 2.2 curve data and the gamma 2.6 curve data are stored, the selector 700 may select one of the two curve data. do. For example, when the logic unit 870 is an AND circuit, when the high voltage VDD is applied to the logic unit 870 by shorting the resistor R1 and opening the resistor R2, the logic unit 870 generates logic. When the value '1' is outputted, the memory 810 outputs gamma 2.2 curve data. Alternatively, when a low voltage ground voltage is applied to the logic unit 870, the logic R1 opens the resistor R1 and shorts the resistor R2. The unit 870 outputs a logic value '0', and the memory 810 outputs gamma 2.6 curve data.

The resistors R1 and R2 may be implemented as transistors, for example, the resistor R1 may be implemented as an NMOS transistor and the resistor R2 may be implemented as a PMOS transistor. Then, when the signal controller 600 emits a high signal, a high voltage is applied to the logic unit 870, and when the signal controller 600 emits a low signal, a low voltage is applied to the logic unit 870 to selectively output data as described above. have.

Alternatively, the operator may adjust the resistance value directly after the display device is manufactured. In this case, the resistors R1 and R2 are implemented as actual resistors, and the resistances of the two resistors are adjusted to adjust the voltage applied to the logic unit 870. I can regulate it. For example, a voltage closer to the high voltage VDD is applied by increasing the resistance value of the resistor R2 than the resistor R1, or a voltage closer to the low voltage by increasing the resistance value of the resistor R1 than the resistor R2. When a value is applied. Alternatively, one of the two resistors may be removed to apply a high voltage or a ground voltage to the logic unit 870.

At this time, it is preferable to select the two curve data according to the state of the display device. That is, gamma 2.2 curve data is selected when the luminance of the display device is low, and gamma 2.6 curve data is selected when the luminance is high.

In this way, when the value of the memory included in the signal controller 600 is incorrect by selecting a gamma curve by having a separate memory 810 in the reference voltage generator 800, the signal controller may be compensated. By simplifying the function of 600, the signal controller 600 can be efficiently used, thereby improving display quality of the display device.

In addition, when the data is difficult to modify because there is no auxiliary memory EEPROM, it can be easily modified by utilizing the data of the memory 810 provided in the reference voltage generator 800.

As described above, the display quality of the display device may be improved while the signal controller 600 may be efficiently used by selecting one of the gamma curves with the separate memory 810 in the reference voltage generator 800.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (10)

A display device including a plurality of pixels, A reference voltage generator including a memory configured to store a plurality of gamma data for adjusting luminance of the display device, and generating a plurality of reference voltages based on the gamma data from the memory; A data driver which divides the reference voltage to generate a plurality of gray voltages, selects a gray voltage corresponding to the image data among the gray voltages as a data voltage, and applies the same to the pixel A selection unit connected to the reference voltage generation unit, and A signal controller generating a control signal for controlling the image data and applying the control signal to the data driver Display device comprising a. In claim 1, The reference voltage generator A logic unit connected between the selection unit and the memory, First and second registers connected to the memory and sequentially receiving and storing the gamma data from the memory; First and second demultiplexers coupled to the second register, First and second resistor rows connected to the first and second demultiplexers, respectively, and including a plurality of resistors; First and second switching elements connected to output terminals of the first and second demultiplexers, respectively, and opened and closed according to a control signal from the second register; and An amplifier for amplifying the voltage output through the first switching element or the second switching element Containing more Display device. In claim 2, And the selection unit applies a signal for selecting any one of a plurality of gamma data stored in the memory through the logic unit. In claim 3, The selector includes third and fourth switching elements connected in series between a high voltage and a low voltage, Contacts of the third and fourth switching elements are connected to the logic unit. Display device. In claim 4, And the third and fourth switching elements are transistors of different types. In claim 3, The selection unit includes a resistor string connected in series between the high voltage and the low voltage, The center of the resistor string is connected to the logic section Display device. In claim 2, And the logic unit is an AND circuit whose one end is connected to a high voltage and the other end is connected to the selection unit. In claim 2, And the logic unit is a logic sum circuit having one end connected to a low voltage and the other end connected to the selector. In claim 1, The gamma data is a 10-bit digital signal, the most significant bit of the 10 bits is used to select the first and second switching elements, and the remaining 9 bits are used to select some of the voltages divided by the resistor string. Device. In claim 1, The data driver includes a plurality of data driver integrated circuits, Each data driving integrated circuit is connected to the signal controller via two buses.

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