KR100983712B1 - Unit of driving liquid crystal display - Google Patents

Abstract

The present invention relates to a driving unit of a dual mode liquid crystal display device, wherein the driving unit of the liquid crystal display device of the present invention receives external data to form a plurality of signals and outputs a driving voltage; A first time controller which receives a driving voltage from the first power supply and outputs a first output enable signal; A second time controller which receives a driving voltage from the second power supply and outputs a second output enable signal; A first synchronizing unit configured to apply a synchronizing signal to the first power supply unit by synchronizing the first and second output enable signals; And a second synchronizer for synchronizing the first and second output enable signals to apply a synchronization signal to the second power supply.

Power Supply, Time Control, Synchronous, Dual Mode, Control Board

Description

Drive unit of liquid crystal display {UNIT OF DRIVING LIQUID CRYSTAL DISPLAY}

1 is a plan view schematically showing a general dual mode liquid crystal display device.

2 is a diagram briefly showing an operation relationship between a power supply unit and a time control unit;

Figure 3 is a simplified diagram showing the internal configuration of the drive unit of the liquid crystal display device according to the present invention.

** Description of the symbols for the main parts of the drawings **

231: first control board 232: second control board

241: first power supply unit 241: second power supply unit

243. first time controller 244: second time controller

261: first synchronization unit 262: second synchronization unit

DATA10: External data SYNC_OE: Sync signal

OE11: first output enable signal OE12: second output enable signal

VCC11, VCC12: Drive voltage VGL11, VGL12: Low potential scan signal

VGH11, VGH12: High potential scan signal VDD11, VDD12: Image voltage

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving unit of a liquid crystal display. More particularly, the present invention relates to a liquid crystal display device that can improve image quality by applying accurate image information and control signals by synchronizing operation timings of a plurality of control boards. It relates to a drive unit.

In general, a liquid crystal display device is bonded to a thin film transistor array substrate and a color filter substrate facing each other so that a constant cell-gap is maintained, and the liquid crystal in the bonded space. A liquid crystal panel having a layer and a driving circuit for driving the liquid crystal panel to display an image.

On the thin film transistor array substrate, a plurality of gate lines arranged laterally at regular intervals and a plurality of data lines arranged at regular intervals vertically intersect with each other, and in the region where the gate lines and the data lines intersect each other, a pixel ( pixel) is provided. The pixels are arranged in a matrix form on the thin film transistor array substrate.

Red, green and blue color filter layers are formed on the color filter substrate by mixing red light, green light and blue light, and light leaks between the color filter layers outside the red, green and blue color filter layers. A black matrix layer is formed densely in the shape of a net to prevent it.

The pixel includes a switching element such as a thin film transistor, and the switching element is electrically connected to the data line and the gate line. In addition, the pixels are individually provided with pixel electrodes, and in general, an electric field is applied to the liquid crystal layer together with the common electrode provided in the color filter substrate.

In the switching device, a gate electrode is connected to the gate line, and a source electrode is connected to the data line. The drain electrode is electrically connected to the pixel electrode.

The data driving circuit converts digital image information supplied from the outside into analog image information and applies the same to the data line.

When the gate driving circuit sequentially applies a scan signal to the gate line every horizontal period, the switching elements connected to the gate line to which the scan signal is applied are turned on. In this case, the image information applied to the data line from the data driving circuit is applied to the pixel electrode of the pixel through the switching elements.

The intensity of the electric field formed in the liquid crystal layer is adjusted according to the voltage difference between the image information applied to the pixel electrode and the common voltage applied to the common electrode, and the light transmittance of the liquid crystal layer is adjusted by the strength of the electric field to display an image. do.

On the other hand, the liquid crystal display device is a holding type display device. That is, the image information is charged into the pixel while the high potential scan signal is applied, and the arrangement of the liquid crystal molecules is changed. In the section where the low potential scan signal is applied to the pixel, the arrangement of the liquid crystal is maintained with the charged image information. This is how you do it. Therefore, while the high potential scan signal is applied, the pixel must be charged with sufficient amount of image information to accurately maintain the arrangement state of the liquid crystal molecules for one frame.

Recently, liquid crystal display devices are becoming thinner and lighter, and are becoming a larger area. In such a large area liquid crystal display, signal delay may be a problem. That is, in the large-area liquid crystal display device, the lengths of the data lines and the gate lines are also lengthened, and the resistance according to the line length accumulates and increases. As the scan signal applied to the gate line through the gate driver moves away from the gate driver by the resistance of the gate line, delay and attenuation of the scan signal occurs. In this case, a scan signal with almost no signal delay is applied to a pixel close to the gate driver, while a significantly delayed scan signal is applied to a pixel far from the gate driver.

As the liquid crystal display becomes larger, the delay of the scan signal becomes larger, and the charging time of the image information of the pixel varies according to the length of the gate line, so that the image quality of the liquid crystal display varies due to the uneven charging amount of each pixel. Deterioration occurs.

As described above, as the liquid crystal display device becomes larger, a dual mode liquid crystal in which a gate driver and a data driver are formed on both sides of the liquid crystal panel to apply a signal to each other in order to prevent image degradation caused by the delay of the scan signal. A display device has been developed and shown schematically in FIG.

1 is a plan view schematically illustrating a general dual mode liquid crystal display device.

As shown in the figure, the liquid crystal display device according to the present invention includes a liquid crystal panel and first and second gate driving circuits 20 and 21 and first and second data driving circuits 10 and 11 for driving the liquid crystal panel. It is composed. In the liquid crystal panel, the color filter substrate and the thin film transistor array substrate 2 are bonded to each other, and a liquid crystal layer is formed between the two bonded substrates. The color filter substrate is provided with a common electrode for applying an electric field to the color filter, the black matrix, and the liquid crystal layer. For convenience of description, only the thin film transistor array substrate 2 is shown in the drawings.

The thin film transistor array substrate 2 is disposed such that the plurality of gate lines GL1..GLm are regularly spaced apart laterally and the plurality of data lines DL1..DLn are regularly spaced apart longitudinally. A plurality of pixels are defined in the regions divided by these intersections. Each pixel is formed with a switching element TFT1 such as a thin film transistor, and each pixel is formed with a common electrode and a pixel electrode (not shown) for applying an electric field to the liquid crystal layer.

Although not shown in the drawing, the gate electrode of the switching element TFT1 is connected to the gate line GL1..GLm, the source electrode is connected to the data line DL1..DLn, and the drain electrode is connected to the pixel electrode. do. Therefore, when a high potential scan signal is applied to the gate electrode through the gate line GL1..GLm, the image is applied from the data line DL1..DLn and applied to the pixel electrode via the source electrode and the drain electrode. The information is applied to the liquid crystal layer by the voltage difference from the common voltage of the common electrode, thereby adjusting the light transmittance of the liquid crystal layer. On the other hand, when the low potential scan signal is applied to the gate electrode, the movement of the image information via the source electrode and the drain electrode is blocked.

On the other hand, a storage capacitor is formed in each pixel, and the storage capacitor charges the image information while the scan signal is applied to the gate electrode, and then while the image information is supplied to the pixel electrode during the next gate line driving. The discharged voltage serves to prevent voltage variation of the pixel electrode.

In this case, the scan signals and the image information necessary to drive the liquid crystal are first and second gate driving circuits 20 and 21 and first and second terminals connected to both ends of the gate line GL1..GLm and the data line DL1..DLn. It is applied from the first and second data driving circuits 10 and 11. The first and second gate driving circuits 20 and 21 and the first and second data driving circuits 10 and 11 receive various control signals, driving voltages, and image information from the first and second control boards 30 and 31. The first and second control boards 30 and 31 are provided with a plurality of elements such as integrated circuits to generate various control signals, driving voltages and image information for driving the liquid crystal panel.

The gate driving circuits 20 and 21 correspond to the first gate driving circuit 20 connected to one side of the gate line GL1 .. GLm and the gate line GL1. And a second gate driving circuit 21 connected to the other side of the .GLm). The first and second gate driving circuits 20 and 21 simultaneously apply scan signals to both sides of the gate line GL1 .. GLm.

In addition, the data driving circuits 10 and 11 may include a first data driving circuit 10 connected to one side of the data line DL1 .. DLn, and the data line DL1 corresponding to the first data driving circuit 10. And a second data driving circuit 11 connected to the other side of .DLn). The first and second data driving circuits 10 and 11 simultaneously apply image information on both sides of the data line DL1..DLn.

As described above, since the signal is supplied from both sides of the gate line GL1..GLm and the data line DL1..DLn, the pixel having the largest real signal delay is the pixel located at the center and positioned at the center. Therefore, the resistance of the pixel having the largest wiring resistance is also about half of that of the conventional art.

As described above, as the scan resistance applied through the gate lines GL1..GLm and the data lines DL1..DLn and the wiring resistance affecting the image information are reduced than before, the signals of the scan signal and the image information are reduced. The delay can be reduced. Here, the reduction of the signal delay of the scanning signal and the image information means improvement of afterimage and improvement of image quality. In other words, it is possible to minimize the difference in the image information charging rate during the scanning signal applied to the storage capacitor Cst of the pixel to which the first scan signal is applied and the pixel to which the last scan signal is applied, thereby providing a screen having uniform brightness. .

Meanwhile, the first data driving circuit 10 and the second data driving circuit 11 receive various control signals and image information from the first control board 30 and the second control board 31, respectively. The first control board 30 and the second control board 31 are formed corresponding to both sides of the liquid crystal panel, and their functions are the same.

Although not shown in the drawings, the inside of the first control board 30 and the second control board 31 will be described in detail, and the first control board 30 and the second control board 31 may include data from outside. And a power supply (DC-DC converter) for forming and outputting a plurality of driving voltages for driving the respective circuits and receiving the driving voltage (VCC) from the power supply, and outputting the output power to the power supply. A timing controller for driving the power supply unit by applying an enable signal, a gamma voltage unit for forming and outputting a plurality of gamma voltages through a driving voltage VDD supplied by the power supply unit, and the power supply unit And a common voltage supply unit configured to receive the driving voltage VDD and output the common voltage VCOM.

The driving voltage VDD output from the power supply unit may be supplied to the gamma voltage unit to form a plurality of gamma voltages, and may be supplied to the first and second data driving circuits 10 and 11 to be output as image information. It may be.

The first control board 30 and the second control board 31 have the same internal configuration as described above. That is, the first control board 30 supplies the image information and the gamma voltage to the first data driving circuit 10, and the second control board 31 supplies the image to the second data driving circuit 11. It provides information and gamma voltage.

In addition, the first control board 30 and the second control board 31 supply common voltage, low potential, and high potential scan signals to the first and second gate driving circuits 20 and 21.

The power supply unit receives external data DATA and forms various control signals, voltages, and image information from the data DATA. The data DATA includes external image information, control signals, and voltages. The power supply unit is driven by an output enable signal of the time controller.

The relationship between the power supply unit and the time control unit will now be described with reference to the accompanying drawings.

2 is a view briefly showing an operation relationship between a power supply unit and a time control unit.

Referring to FIG. 2, the power supply unit 141 receives an external data DATA to output a driving voltage VCC and a plurality of signals, and receives a driving voltage VCC from the power supply unit 141. The time control unit 143 is shown to apply an output enable signal to the power supply unit 141 so that the power supply unit 141 outputs a plurality of signals.

The power supply unit 141 receives external data DATA and outputs the plurality of signals. However, the power supply unit 141 outputs a plurality of signals only when the output enable signal is applied from the time controller 143. That is, the power supply unit 141 operates the time control unit 143 by first applying the driving voltage VCC to the time control unit 143 by receiving external data DATA, but secondarily. In order to output a plurality of signals, control by the output enable signal of the time controller 143 is required.

However, the first control board and the second control board are operated separately. That is, the first control board and the second control board separately drive organic driving such as a power supply unit 141, a time control unit 143, a gamma voltage unit, and a common voltage supply unit that receive external data DATA. Is performed. Therefore, the operations of the power supply unit 141 and the time control unit 143 provided on the first control board and the power supply unit 141 and the time control unit 143 provided on the second control board are independently performed without affecting each other. do.

The liquid crystal display applies a high potential scan signal to the gate line sequentially every frame, and applies image information to the pixel in accordance with the application timing of the high potential scan signal. However, when the power supply unit 141 and the time control unit 143 provided in the first and second control boards operate separately as described above, the first gate driving circuit and the second gate driving circuit in each power supply unit 141. The timing of supplying the high potential and low potential scan signals to the furnace is changed, and the timing of applying image information to the first gate driving circuit and the second gate driving circuit is changed so that the same data is used in the first and second data driving circuits. Image information having different phase differences may be applied to the lines, and scanning signals having different phase differences may be applied to the same gate lines in the first and second gate driving circuits.

As a result, the operation timing is changed by different phase differences of signals applied to the same gate line or data line in the first and second control boards, respectively, so that no output may be performed at one control board. For example, when the high potential scan signal is applied to the gate line in the first gate driving circuit, the first data driving circuit applies the image information, and before the image information is output from the second data driving circuit, the scan signal is applied at the high potential. When the transition is made to the low potential, no output of the second data driving circuit is made. As described above, a phenomenon in which one of the first and second control boards is not output is referred to as a shut-down phenomenon.

When such a shut-down phenomenon occurs, accurate image information cannot be supplied to the liquid crystal panel, and thus the image quality of the liquid crystal display device is degraded.

Accordingly, the present invention has been devised to solve the above-described problems, and the present invention is driven by synchronizing and driving the respective control boards that operate individually, so that accurate image information is supplied to the liquid crystal panel at the same timing. Therefore, the purpose of the present invention is to improve the image quality deterioration phenomenon of the liquid crystal display device.

The driving unit of the liquid crystal display device for achieving the object of the present invention as described above to form a plurality of signals by receiving external data, and the first and second power supply unit for outputting a driving voltage; A first time controller which receives a driving voltage from the first power supply and outputs a first output enable signal; A second time controller which receives a driving voltage from the second power supply and outputs a second output enable signal; A first synchronizing unit configured to apply a synchronizing signal to the first power supply unit by synchronizing the first and second output enable signals; And a second synchronizer for synchronizing the first and second output enable signals to apply a synchronization signal to the second power supply.

That is, a feature of the present invention is that in a liquid crystal display having a plurality of time controllers and a power supply unit, by synchronizing the output enable signals output from the time controller, a synchronization signal is applied to the power supply unit, whereby a plurality of power supplies are provided at the same timing. As a result, the image quality and the control signal are supplied to the liquid crystal display, thereby improving the image quality.

3 is a view briefly illustrating an internal configuration of a driving unit of a liquid crystal display according to the present invention.

First, referring to FIG. 3A, a first power supply unit 241 for forming a plurality of signals by receiving external data DATA10 and outputting a driving voltage VCC11 and applying it from the first power supply unit 241. A first control board 231 operated by the received driving voltage VCC11 and including a first time control unit 243 for applying an output enable signal OE11 to the first power supply unit 241; It is operated by the second power supply unit 242 that receives the data DATA10 to form a plurality of signals and outputs the driving voltage VCC12, and the driving voltage VCC12 applied from the second power supply unit 242. And a second control board 232 including a second time controller 244 for applying an output enable signal OE12 to the second power supply unit 242, and the first time controller 243 is output. The output enable signal OE11 output from the output enable signal OE11 and the second time controller 244 is identical. To synchronize the output enable signals OE11 and OE12 of the first and second time controllers 243 and 244 to be applied to the first power supply unit 241 as a synchronization signal. And a second synchronization unit 262 for applying a synchronization signal to the power supply unit 242.

The first and second power supply units 241 and 242 output the plurality of signals only when the output enable signals OE11 and OE12 are applied from the first and second time controllers 243 and 244, respectively. The first and second power supply units 241 and 242 are individually operated by the output enable signals OE11 and OE12 of the first and second time control units 243 and 244, respectively. First and second synchronization units 261 and 262 are formed between the first and second power supply units 241 and 242 and the first and second time control units 243 and 244 to match the operation timing of the second power supply units 241 and 242.

The first synchronization unit 261 and the second synchronization unit 262 are devices for allowing the first power supply unit 241 and the second power supply unit 242 to organically operate with each other. That is, the output enable signal OE11 output from the first time control unit 243 is not only involved in the operation of the first power supply unit 241 but also in all of the driving of the first and second power supply units 241 and 242. . In addition, the output enable signal OE12 output from the second time controller 244 is similarly involved in driving both the first and second power supply units 241 and 242.

In the present invention, a characteristic device for synchronizing the driving of the first and second power supply units 241 and 242 is the first and second synchronization units OE11 and OE12. The first synchronizer 261 receives an output enable signal OE11 from the first time controller 243, and receives an output enable signal OE12 from the second time controller 244. Here, the output enable signal OE11 of the first time controller 243 is referred to as the first output enable signal OE11, and the output enable signal OE12 of the second time controller 244 is referred to as the second output enable. I will call it the Able signal (OE12). Meanwhile, the first synchronization unit 261 receiving the first and second output enable signals OE11 and OE12 is operated at the moment when the first and second output enable signals OE11 and OE12 transition from a low potential to a high potential. One synchronization signal SYNC_OE is applied to the first power supply 241.

The second synchronizer 262 receives the first and second output enable signals OE11 and OE12 from the first and second time controllers 243 and 244 and receives the first and second output enable signals OE11 and OE12. A synchronization signal SYNC_OE is applied to the second power supply unit 242 in synchronization with the edge of the waveform of which is shifted to the high potential.

Although not shown, the first and second power supply units 241 and 242 to which the synchronization signal SYNC_OE is applied are supplied with the high potential scan signal and the low potential scan signal to the first and second gate driving circuits, respectively. And the image voltages VDD11 and VDD12 are supplied to the common section and the common voltage supply section.

The AND-LOGIC-GATE is applied to the first and second driving units 261 and 262, but may be formed by a combination of other logic-gates except for the AND-logical-gate. The driving of the first and second driving units 261 and 262 will be described in detail as follows.

As in the prior art, the first and second power supply units 241 and 242 and the first and second time control units 243 and 244 are operated separately. Accordingly, the first and second outputs output from the first and second time controllers 243 and 244 may be used to prevent shutdown of the liquid crystal display device caused by different driving timings of the first and second control boards 231 and 232. The enable signals OE11 and OE12 are synchronized.

In practice, the low potential first output enable signal OE11 and the low potential second output enable signal OE12 are applied to the first synchronization unit 261 and the second synchronization unit 262, respectively. In this case, when the first output enable signal OE11 and the second output enable signal OE12 are moved to high potential, the first and second synchronization parts 261 and 262 output the synchronization signal SYNC_OE. That is, even if the time at which the first output enable signal OE11 transitions to high potential and the time at which the second output enable signal OE12 transitions to high potential are different from each other, both signals OE11 and OE12 transition to high potential. The synchronization signal SYNC_OE is output in accordance with the characteristics of the instantaneous end-combination.

As described above, since the first and second output enable signals 261 and 262 are operated when the first and second output enable signals OE11 and OE12 are all transitioned to high potentials, the first and second output enable signals OE11, OE12 causes the first and second synchronization units 261 and 262 to output the synchronization signal SYNC_OE at the same time.

Accordingly, the first and second power supply units 241 and 242 output a plurality of signals at the same time by the synchronization signal SYNC_OE applied at the same time. The first and second power supply units 241 and 242 are driven by the same synchronizing signal SYNC_OE to apply image information, high potential, and low potential scan signals to the liquid crystal panel, and thus the liquid crystal display device generated by different conventional output timings. As a result, the shut-down phenomenon of the liquid crystal display can be eliminated, and the image quality and the control signal are correctly applied, thereby preventing the deterioration of the image quality of the liquid crystal display device.

The first and second driving units 261 and 262 may be separately formed outside the first and second power supply units 241 and 242, respectively. At this time, the wiring for applying the first output enable signal OE11 to the second synchronization unit 262 from the first time control unit 243 and the second time enable unit 244 are applied to the second time enable unit 244. ), Wiring for applying to the first synchronization unit 261 should be formed on the liquid crystal panel.

However, when the first and second synchronization units 261 and 262 and the first and second power supply units 241 and 242 are far apart from each other, the first and second output enable signals may be transmitted through the first and second synchronization units 261 and 262. Signal attenuation and delay may occur while the synchronization signals SYNC_OE outputted in synchronization with OE11 and OE12 are applied to the first and second power supply units 241 and 242, respectively. Accordingly, in order to prevent the signal delay and attenuation of the synchronization signal SYNC_OE, the first and second synchronization parts 261 and 262 are formed inside the first and second power supply parts 241 and 242 so as to prevent the delay and attenuation of the synchronization signal SYNC_OE. The first and second power supply units 241 and 242 may be immediately operated without time delay by the synchronization signal SYNC_OE output from the 261 and 262.

As described above, the driving unit of the liquid crystal display device of the present invention can drive the liquid crystal panel at the same timing by synchronizing the plurality of output enable signals output from the plurality of time controllers and applying the same to the plurality of power supply units. In addition, it is possible to improve the image quality deterioration of the liquid crystal display device generated by different conventional timings.

Claims (5)

First and second power supply units configured to receive external data to form a plurality of signals and output a driving voltage; A first time controller which receives a driving voltage from the first power supply and outputs a first output enable signal; A second time controller which receives a driving voltage from the second power supply and outputs a second output enable signal; A first synchronizing unit configured to apply a synchronizing signal to the first power supply unit by synchronizing the first and second output enable signals; And a second synchronizing unit configured to apply the synchronizing signal to the second power supply unit by synchronizing the first and second output enable signals. The driving unit of claim 1, wherein the first and second synchronous units are formed inside or outside the first and second power supply units. 2. The driving unit of claim 1, wherein the first and second synchronization units comprise an end-logical combination. 2. The driving unit of claim 1, wherein a synchronization signal is simultaneously output from the first and second synchronization units. 2. The driving unit of claim 1, wherein a plurality of signals are output from the first and second power supply units by a synchronization signal of the first and second synchronization units.

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