KR20170080777A - Liquid crystal display device and driving method thereof - Google Patents

Abstract

The present invention relates to a liquid crystal display and a driving method thereof. This liquid crystal display device predicts the temperature of the source drive IC by using the preset heat generation cost modeling index and the weight setting value, adjusts the gain multiplied by the input data based on this, and changes the inversion phase of the source drive IC So that the temperature of the source drive IC can be managed at an appropriate temperature.

Description

TECHNICAL FIELD [0001] The present invention relates to a liquid crystal display (LCD)

The present invention predicts the temperature of a source drive integrated circuit (hereinafter referred to as "IC") in consideration of an image data analysis result and an inversion method of a data voltage, And a method of driving the liquid crystal display device.

Various flat panel display devices such as a liquid crystal display (LCD) device and an organic light emitting diode (OLED) display device are commercially available. A liquid crystal display device displays an image by controlling an electric field applied to liquid crystal molecules in accordance with a data voltage. A thin film transistor (hereinafter referred to as "TFT") is arranged for each pixel in a display device of an active matrix (Active Matrix) method.

Pixels of a liquid crystal display are divided into red (R), green (G) and blue (B) subpixels for color implementation. The liquid crystal display device is an inversion type in which polarities of data voltages charged in neighboring sub-pixels are reversed and the polarities of data voltages are periodically inverted in order to reduce direct current residual images and prevent deterioration of liquid crystal Is being driven. In most liquid crystal displays, a version system with one horizontal and vertical dots and a version system with one vertical dot and two vertical dots are applied. One dot means one sub-pixel.

The liquid crystal display device includes a plurality of source drive integrated circuits (D-ICs) for supplying data voltages to the data lines of the display panel, gate pulses (or scan pulses) applied to gate lines (or scan lines) Pulses) sequentially, and a timing controller for controlling the drive ICs, and the like.

The resolution of the liquid crystal display device is increased and the driving frequency is increasing. According to this tendency, the source drive IC (D-IC) is driven at a high speed, and a problem of heat generation of the IC is seriously arising. If the source drive IC (D-IC) generates heat above its proper temperature, the IC may malfunction or be damaged. The heat dissipation design of the IC package, the heat dissipation structure design of the IC circuit, and the heat dissipation structure design of the display module and the set structure are applied as a method of controlling the temperature of the conventional source drive IC (D-IC) .

The present invention provides a liquid crystal display device capable of managing the temperature of a source drive IC at an appropriate level and a driving method thereof.

The liquid crystal display of the present invention includes a display panel in which data lines and gate lines are crossed, pixels are arranged in a matrix form, one or more source drive ICs that convert received data into data voltages and supply the data voltages to the data lines, A first index defining a pixel connection structure of the display panel, a second index defining an inversion phase controlling polarity of data, a first weight set according to a level of data, and a transition size of the data The second weight, and the third weight according to the transition drive of the source drive IC, and adjusts the gain multiplied by the input data based on the temperature of the source drive IC, And a temperature control unit for changing the temperature.

Wherein the temperature control unit includes a memory for storing the indices and the weight value, and a controller for estimating a temperature of the source drive IC by using the indices and the weights, and when the temperature of the source drive IC becomes higher than a predetermined temperature, And a logic circuit that alters the phase of the version or makes the gain lower than the current value.

The temperature control unit receives the input data, the indices, and the weight values, and calculates a first heating cost for a level of the input data according to each inversion phase, and a second heating cost for a transition size of the input data, Calculate the heating cost. The temperature controller divides the sum of the first heat generation cost and the second heat generation cost for each channel of the source drive IC by inversion phases to accumulate the heat generation cost for each channel. Wherein the temperature control unit adds the cumulative value for each channel obtained in each channel of the source drive IC in the pixel array region occupied by the source drive IC to calculate the sum of the heat generation costs, And controls the polarity of the data in an inversion phase having a minimum value among the total heat generation cost of the IC. The temperature controller compares a maximum value among the total heat generation coefficients with a preset threshold value, and adjusts the gain according to the comparison result.

The gain has a value between 0 and 1. The gain is adjusted to a value less than 1 when the maximum value of the total heat generation cost is less than the threshold value while the maximum value of the total heat generation cost is less than 1 when the maximum value is less than the threshold value.

The transition drive of the source drive IC includes charge sharing drive and HVDD drive. The third weight is set to a different value in the charge sharing drive and the HVDD drive.

The driving method of the liquid crystal display device includes a first index defining a pixel connection structure of a display panel, a second index defining an inversion phase controlling polarity of data, a first weight set according to a level of data, Setting a first weight according to a size of the source drive IC and a third weight corresponding to a transition drive of the source drive IC; setting a temperature of the source drive IC for driving the data lines of the display panel using the indexes and the weight; And adjusting the gain based on the temperature prediction result of the source drive IC, and modulating the data to be transmitted to the source drive IC by multiplying the gain by the input data.

According to the present invention, the temperature of the source drive IC is predicted based on the indexes and the weights set in the preset heat generation cost modeling, the inversion phase and the input data are modulated according to the temperature prediction result, Can be managed.

Since the heat dissipation of the source drive IC is managed by an algorithm executed by the temperature control unit, the present invention eliminates the need for a mechanism to be added to the heat dissipation design, thereby reducing the cost of the heat dissipation design equipment. Also, since the temperature control unit can share the hardware resources with the over-driving circuit for improving the response characteristic of the liquid crystal, there is almost no addition of hardware resources.

1 is a block diagram showing a liquid crystal display device according to an embodiment of the present invention.
2 to 4 are views showing the structure of various display panels.
5 is a view illustrating a principle of a temperature control method of a source drive IC according to an embodiment of the present invention.
6 is a diagram showing the principle of charge sharing.
7 is a view showing the principle of driving the HVDD.
8 is a flowchart illustrating a method of controlling a temperature of a source drive IC according to an embodiment of the present invention.
9 is a diagram showing an example in which the transition level of data varies according to an in-phase shift of a phase.
FIGS. 10 and 11 are views showing an example of an index relating to a pixel connection structure.
12 and 13 are views showing an example of a temperature control method according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

The display device of the present invention can be implemented as a display device including source drive ICs (D-ICs), for example, a flat panel display device such as a liquid crystal display (LCD), an OLED display, and the like.

1 is a block diagram showing a liquid crystal display device according to an embodiment of the present invention. 2 to 4 are views showing the structure of various display panels.

1 to 4, a liquid crystal display according to an embodiment of the present invention includes a display panel 100, a timing controller 101, a data driver 102, and a gate driver 103.

The display panel 100 may be implemented in various known liquid crystal modes such as TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In Plane Switching) mode and FFS (Fringe Field Switching) mode. This liquid crystal display device can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, and a reflective liquid crystal display device. In a transmissive liquid crystal display device and a transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The display panel 100 includes a liquid crystal layer formed between two substrates. The display panel includes pixels arranged in a matrix form by an intersection structure of the data lines DL and the gate lines GL. Each of the pixels is divided into a red subpixel R, a green subpixel G and a blue subpixel B and may further include a white subpixel W as shown in FIG. Each of the subpixels includes liquid crystal cells Clc.

On the lower substrate of the display panel 100, a TFT array is formed. The TFT array includes liquid crystal cells Clc formed at the intersections of the data lines DL and the gate lines GL, TFTs connected to the pixel electrodes 11 of the liquid crystal cells, and storage capacitors Cst do. The TFT array may be implemented in various forms as shown in FIGS. The liquid crystal cells Clc are connected to the TFT and driven by the electric field between the pixel electrodes 11 and the common electrode 12. [ On the upper substrate of the display panel 100, a color filter array including a black matrix, a color filter, and the like is formed. On the upper substrate and the lower substrate of the display panel 100, a polarizing plate is attached and an alignment film for setting a pre-tilt angle of the liquid crystal is formed.

A timing controller (TCON) 101 transmits digital video data RGB of an input image input from a host system (HOST) 104 to the data driver 102. The timing controller 101 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE and a clock CLK from the system board 104. The timing controller 101 generates timing control signals SDC and GDC for controlling the operation timings of the data driver 102 and the gate driver 103 based on the timing signals.

The gate timing control signal GDC includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, and the like. The gate start pulse GSP controls the operation start timing of the gate drive IC constituting the gate driver 103. [ The gate shift clock GSC controls the shift timing of the gate pulse by a clock signal commonly input to the gate drive ICs. The gate output enable signal GOE controls the output timing of the gate drive ICs.

The data timing control signal SDC includes a source start pulse SSP, a source sampling clock SSC, a polarity control signal POL, and a source output enable signal SOE. The source start pulse SSP controls the data sampling start timing of the source drive ICs (D-IC) constituting the data driver 102. The source sampling clock SSC is a clock signal for controlling the sampling timing of data in each of the source drive ICs (D-IC). The source output enable signal SOE controls the output timing of the data driver 102. The source start pulse SSP and the source sampling clock SSC may be omitted. The polarity control signal POL controls the polarity of the data voltage supplied to the pixels.

The timing controller 101 includes a temperature controller 200. The temperature control unit 200 predicts the temperature of the source drive IC (D-IC) using preset heating cost modeling to adjust the inversion phase and gain. The temperature control unit 200 multiplies the input image data by the gain to lower the data level and the transition size, thereby suppressing the temperature rise of the source drive IC (D-IC) and inducing the temperature drop.

The temperature controller 200 includes a first index defining a pixel connection structure of the display panel 100, a second index defining an inversion phase controlling polarity of data, a first weight set according to a level of data, A second weight set according to the size, and a third weight according to the transition driving method of the source drive IC (D-IC). Also, the temperature controller 200 executes the algorithm shown in FIG. 8 to predict the temperature of the source drive IC (D-IC) based on the indices and the weights, Adjust the temperature of the source drive IC (D-IC) to an appropriate level by lowering the gain multiplied by the data when the temperature of the source drive IC is higher than the current value.

The temperature control unit 200 estimates the temperature of the source drive IC (D-IC) using the preset heat cost modeling and calculates the gain from the predicted temperature to modulate the data gradation (or data level) do. The data analysis of the input image includes a process of analyzing the gradation of the input image data or the voltage of the data voltage and the change thereof. The temperature control unit 200 can modulate the input image data based on the temperature prediction result of the source drive IC (D-IC) D-IC). Therefore, the present invention minimizes the heat dissipation design (mechanism, material addition) to reduce the temperature of the source drive IC (D-IC) and can manage the temperature of the source drive IC (D-IC) at an appropriate level.

The timing controller 101 increases the frame rate to a frequency of a frame rate (frame rate or frame frequency) × N (N is a positive integer of 2 or more) of the input image and sets the driving frequency of the display panel driving units 102 and 104 to N The frame rate can be controlled at a multiple of the frame rate. The frame rate is 60 Hz in the National Television Standards Committee (NTSC) system and 50 Hz in the PAL (Phase-Alternating Line) system.

The data driver 102 includes one or more source driver ICs (D-ICs). Each of the source drive ICs D-IC includes a shift register, a latch, a digital-to-analog converter (DAC), an output buffer, And converts the data received from the timing controller 101 into a positive polarity / negative polarity data voltage. The DAC includes a P (Positive) decoder for converting data into a positive data voltage and an N (Negative) decoder for converting data into a negative data voltage as shown in FIG. The data output from the timing controller 101 is data modulated by the temperature control unit 200. [ The source driver ICs (D-IC) latch digital video data (RGB) under the control of the timing controller 101. The source driver ICs D-IC convert the digital video data RGB to an analog positive / negative gamma compensation voltage to generate a data voltage, and in response to the polarity control signal POL, . The source drive ICs (D-IC) output the data voltage to the data lines (DL) in response to the source output enable signal (SOE). The source drive ICs D-IC output the data voltage to the low logic section (Low or 0) of the source output enable signal SOE and the high logic section of the source output enable signal SOE (high or 1 ) Can be charge-shared. Charge sharing short circuits the neighboring data lines DL to average the voltages of the data lines to reduce the swing width of the data voltage.

The gate drive ICs of the gate driver 103 include a shift register and a level shifter. The gate driver 103 sequentially supplies a gate pulse synchronized with the data voltage to the gate lines GL in response to the gate timing control signal GDC.

The host system 104 may be implemented in any one of a television system, a home theater system, a set top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), and a phone system. The host system 104 scales the digital video data RGB of the input image according to the resolution of the display panel 100. The host system 14 transmits the timing signals Vsync, Hsync, DE, and CLK to the timing controller 101 together with the digital video data RGB of the input image.

Figs. 2 to 4 are equivalent circuits showing various examples of the TFT array. Figs. 2 to 4 show a part of the TFT array. 2 to 4, D1 to D6 denote data lines, G1 to G6 denote gate lines, and LINE # 1 to LINE # 6 denote line numbers of pixel arrays, respectively.

The TFT array shown in Fig. 2 is a TFT array which is applied in most liquid crystal displays. In this TFT array, the data lines D1 to D6 and the gate lines G1 to G4 are crossed. Each of the TFTs applies a data voltage from the data lines D1 to D6 to the pixel electrodes of the liquid crystal cells arranged on the left side (or right side) of the data lines D1 to D6 in response to gate pulses from the gate lines G1 to G4, (11). When the resolution of the TFT array shown in Fig. 2 is M x N (where each of M and N is a positive integer of 2 or more), M x 3 data lines and N gate lines are required. In M x 3, 3 is the number of sub-pixels contained in one pixel.

The TFT array shown in Fig. 3 is a TFT array having a structure in which the number of data lines required at the same resolution is reduced to 1/2 as compared with the TFT array shown in Fig. The driving frequency of this TFT array is twice as high as that of the TFT array shown in Fig. For this reason, the display panel having the TFT array shown in FIG. 3 may also be referred to as a double rate driving (DRD) panel. Hereinafter, the DRD panel refers to the display panel as shown in Fig. The DRD panel drives the source drive ICs (D-IC) at a high speed as compared with the TFT array shown in FIG. 2, but can reduce the number of ICs required by half. Each of the red subpixel R, green subpixel G and blue subpixel B in the TFT array of the DRD panel is arranged along the column direction. Left and right neighboring liquid crystal cells in the TFT array of the DRD panel share the same data line and continuously charge the data voltage supplied in a time division manner through the data line. The liquid crystal cell and the TFT disposed on the left side of the data lines D1 to D4 are referred to as a first liquid crystal cell and the first TFT T1 respectively and the liquid crystal cell and TFT disposed on the right side of the data lines D1 to D4, The structure of the TFT array will be described as a second liquid crystal cell and a second TFT (T2) as follows. The first TFT T1 supplies a data voltage from the data lines D1 to D4 to the pixel electrodes of the first liquid crystal cell in response to gate pulses from the odd gate lines G1, G3, G5 and G7. The gate electrode of the first TFT T1 is connected to the odd gate lines G1, G3, G5 and G7 and the drain electrode thereof is connected to the data lines D1 to D4. The source electrode of the first TFT (T1) is connected to the pixel electrode of the first liquid crystal cell. The second TFT T2 supplies a data voltage from the data lines D1 to D4 to the pixel electrodes of the second liquid crystal cell in response to gate pulses from the even gate lines G2, G4, G6 and G8. The gate electrode of the second TFT T2 is connected to the even gate lines G2, G4, G6 and G8 and the drain electrode thereof is connected to the data lines D1 to D4. The source electrode of the second TFT (T2) is connected to the pixel electrode of the second liquid crystal cell. The number of data lines in the TFT array of the DRD panel is reduced to 1/2 as compared with the TFT array structure of Fig. 2 at the same resolution.

In Fig. 3, the arrows show the charging sequence of the data voltage output from one channel of the source drive IC (D-IC). In the display panel of Fig. 3, since the pixels are connected in zigzag form along one data line connected to one channel of the source drive IC (D-IC), the data voltage is supplied to the pixels along the arrow direction.

The TFT array shown in Fig. 4 is a TFT array having a structure in which the number of data lines required at the same resolution is reduced to one third as compared with the TFT array shown in Fig. The driving frequency of this TFT array is three times higher than that of the TFT array shown in Fig. Therefore, the display panel having the TFT array shown in FIG. 4 may also be referred to as a TRD (triple rate driving) panel. Hereinafter, the TRD panel refers to the display panel as shown in Fig. One pixel in the TFT array of the TRD panel includes a red subpixel R, a green subpixel G and a blue subpixel G neighboring along the column direction. In the TFT array of the TRD panel, each of the TFTs applies a data voltage from the data lines D1 to D6 to the left (or right) of the data lines D1 to D6 in response to the gate pulse from the gate lines G1 to G6 To the pixel electrode of the arranged liquid crystal cell. The number of data lines in the TFT array of the TRD panel is reduced to 1/3 of that of the TFT array structure of Fig. 2 at the same resolution.

In a liquid crystal display device, a frame rate (frame rate or refresh rate) is high, and DRD or TRD driving requiring high-speed driving can be applied. To this end, the source drive ICs (D-IC) must be driven at a high speed, and in this case, the heat generation problem of the IC becomes serious. The present invention predicts the temperature of the source drive IC (D-IC) using previously set heat cost modeling, and when the data of the source drive IC (D-IC) exceeds the proper temperature range, Modulates the phase and data to lower the level and transition size of the data, thereby inducing a temperature drop in the source drive IC.

5 is a diagram illustrating a principle of a temperature control method of a source drive IC (D-IC) according to an embodiment of the present invention. The waveform diagram of FIG. 5 shows a waveform diagram in which a data voltage inverted in a vertical two-dot version mode is output through one channel of the source drive IC (D-IC). The vertical 2-dot inversion method is an inversion method in which the polarity of the data voltage continuously supplied through the channel of the source drive IC (D-IC) is inverted in the order of + + - - or - - + +.

Referring to FIG. 5, one channel of the source driver IC (D-IC) outputs data voltages of various waveforms according to input image data and an inversion method. The dynamic power consumed per channel in the source drive IC (D-IC) is proportional to V2f. Where V is the voltage and f is the frequency. Therefore, the power value consumed in one channel of the source drive IC (D-IC) can be predicted by waveform analysis of the data voltage.

If the total sum of consumed power per channel of the source drive IC (D-IC) is dangerous, by modulating the data to lower the swing width of the data voltage and lowering V or changing the inversion method, (D-IC) can be lowered and the power consumption can be lowered. The risk level refers to the temperature above the proper temperature at which the reliability of the source drive IC (D-IC) is maintained. The change of the inversion method has difficulties in designing the flexibility of the flicker or the source drive IC (D-IC).

The present invention manages the temperature of the source drive IC to an appropriate temperature by modulating the input data by adjusting the gain based on the predicted temperature of the source drive IC by using the index and the weight setting value of the preset heat generation cost modeling. The present invention suppresses the temperature rise of the source drive IC (D-IC) by adjusting the gain value multiplied by the input image data when the temperature of the source drive IC (D-IC) is predicted as a dangerous level, So that the temperature of the source drive IC is always maintained at an appropriate temperature.

6 is a diagram showing the principle of charge sharing.

6, the source drive IC (D-IC) short-circuits the channel (CH1) to which the positive data voltage is supplied and the channel (CH2) to which the negative data voltage is supplied in the transition junction in which the polarity of the data voltage is inverted And the voltage of the two channels is adjusted by the average voltage to invert the polarity of the data voltage. The source drive IC (D-IC) uses charge sharing to reduce power consumption and heat generation by reducing the swing width of the data voltage when the polarity of the data voltage is reversed.

7 is a diagram showing a principle of driving the HVDD of the source drive IC.

7, a sink current is generated in a channel to which a P decoder P is connected in a transition period in which the data voltage changes in the same polarity, and the sink current is supplied to the N decoder (D- N data voltages are generated by the HVDD driving method under the driving conditions used as the source current in the channel to which the NAND gate N is connected. P decoder P outputs a positive polarity data voltage swinging in a voltage range between VDD and HVDD. N decoder N outputs a negative data voltage swinging in a voltage range between HVDD and VSS. The HVDD driving method uses the sink current I of the channel CH1 to which the P decoder P is connected as the source current I at the channel CN2 to which the N decoder N is connected, . Therefore, the HVDD driving method can reduce power consumption and heat generation of the source drive IC when the data voltage changes at the same polarity.

The source drive IC drives the transition of the positive / negative data voltage to the normal driving state in cases other than the HVDD driving condition under the condition that the data voltage changes at the same polarity. In the normal driving transition, the current flowing in the P decoder and the current flowing in the N decoder are separated, and current consumption is higher than in the HVDD driving method.

8 is a flowchart illustrating a method of controlling a temperature of a source drive IC (D-IC) according to an embodiment of the present invention.

Referring to FIG. 8, the present invention prepares an exothermic cost modeling setting value considering the level of data, the transition size of data, and the transition driving method of the source drive IC (D-IC) based on the preliminary experiment (S1). The level of the data means the gradation of the input image data, or the data voltage level supplied to the pixel. The present invention can determine the level of the data by either the gradation of the data or the data voltage. The transition drive method of the source drive IC (D-IC) may include charge sharing, HVDD (Half VDD) driving, and the like.

In the present invention, a connection structure between pixels and an inversion phase are set in the display panel 100 (S2). The connection structure between the pixels is set to a predetermined first index. In phase is set to a second index that defines the polarity of the data and its polarity inversion timing. In steps S1 and S2, the exothermic cost modeling set values, the indexes indicating the pixel connection structure and the inversion phase are stored in a ROM memory, for example, an EEPROM connected to the timing controller 101. [ When power is supplied to the liquid crystal display device, the data stored in the ROM memory is transferred to the internal memory of the timing controller 101. The temperature controller 200 predicts the temperature of the source drive IC (D-IC) using the data set in the internal memory of the timing controller 101 and the input image data.

Steps S3 to S8 are performed by the temperature control unit 200 in an environment in which the input image is displayed on the display device after the preset values of S1 and S2 are stored in the EEPROM.

Step S3 modulates the data by multiplying the input image data by a gain in order to manage the temperature of the source drive IC (D-IC) at an appropriate level.

In step S4, the data input in step S3 and the pre-set exothermic cost modeling setting values in step S2 are received, and the heat generation cost for each channel of the source drive IC (D-IC) according to the pixel connection structure is calculated. The heat generation cost includes a first heat generation cost for the data level and a second heat generation cost depending on the data transition size considering the driving method (Charge sharing, HVDD) of the source drive IC.

The step S4 accumulates the sum of the first heat generation cost and the second heat generation cost for each channel of the source drive IC (D-IC). The cumulative value of the heat cost sum is accumulated by dividing the phase of the inversion version. In phase is the same as the phase of the polarity control signal POL. For example, a version with vertical 4 dots can be divided into four inversion phases (1) - (4) as follows (see FIG. 9). The data voltage is supplied to the pixels with the polarity changing from left to right as in the inversion phase below.

+ + + + - - - -

 + + + - - - - +

 + + - - - - + +

 + - - - - + + +

The size of the transition of the data voltage and the driving method of the source drive IC can be changed according to the inversion phase. With this in mind, the present invention predicts temperature contributions in various inversion phases.

In step S5, the cumulative value of the heat generation cost per channel obtained in each channel of the source drive IC is added for each region of the source drive IC (D-IC), and the sum of the heat generation costs of each IC is calculated. The region of the source drive IC (D-IC) means a pixel array region in which the IC (D-IC) is responsible. The calculated heat costs at each of the first source drive IC (D-IC) channels are added to calculate the heat cost sum of the first source drive IC (D-IC). The calculated heat costs at each of the second source drive IC (D-IC) channels are added to calculate the heat cost sum of the second source drive IC (D-IC).

The sum of the heat cost calculated in each of the source drive ICs is separated for each phase of the inversion. For example, if there are four in-phase phases, four heating cost totals are obtained in each of the source drive ICs (D-IC).

Step S6 selects an inversion phase having a minimum value among the heat generation cost totals of the source drive ICs (D-IC) separated for each in-phase phase. In step S6, in each of the source drive ICs (D-IC), the polarity control signal POL is generated in the selected inversion phase to control the polarity of the data voltage supplied to the display panel 100. [ The source drive ICs (D-IC) can reverse the polarity of the data voltage in response to the polarity control signal POL having different phases according to the input image data. For example, the inversion phase of the lowest heat cost in the inversion phase-by-phase heat cost at each of a number of source drive ICs is applied in an inversion phase of the source drive ICs.

Step S7 extracts the maximum value among the heat generation cost totals of each of the source drive ICs (D-IC). In step S8, the gain is calculated by comparing the maximum value of the total heat generation cost for each IC with a predetermined threshold value. The gain has a value close to 1 when the maximum value of the total heat cost sum is less than the threshold value between 0 and 1. On the other hand, when the maximum value of the total heat cost sum is larger than the threshold value, . Steps S7 and S8 are performed when the temperature of the corresponding source drive IC (D-IC) is set based on the temperature of the source drive IC (D-IC) predicted as the maximum value among the predicted temperatures of the source drive ICs If it is higher than the temperature, multiply the data by a gain smaller than 1 to adjust the data to a lower value. The set temperature is a suitable temperature at which the source drive IC (D-IC) can operate stably. The threshold value may be set to 130 if the set temperature is 130 degrees or less.

If the temperature contribution of the source drive IC (D-IC) is modeled according to the transition size of the data, it is possible to know how much the transition size should be lowered to lower the temperature of the source drive IC (D-IC) below the proper level. The present invention estimates the temperature of the current source drive IC (D-IC) based on the heat cost modeling and adjusts the gain value to a value for lowering the temperature below the appropriate level.

The present invention pre-sets an index that identifies the pixel connection structure of the display panel. By utilizing this index, when the pixel structure of the display panel is changed, the index value can be changed to know the order of the data supplied to the pixels. The number of transitions of data supplied through each channel of the source drive IC may be varied depending on the pixel connection structure.

FIGS. 10 and 11 are views showing an example of an index relating to a pixel connection structure.

Referring to Figs. 10 and 11, the first index defines the direction of the next pixel position from the current pixel position as a number or character as viewed in the order of filling the data. 11, the first index is set to '3' when the next pixel is positioned along the right horizontal direction from the current pixel, and when the next pixel is positioned along the diagonal direction from the current pixel to the right downward, Is set to " 4 ". The first index is set to '5' if the next pixel is located along the vertical direction from the current pixel downward. Therefore, the first index can define different pixel connection structures with a combination of numbers such as " 5 ", " 46 ", " 36 ", and the like.

The temperature controller 200 can determine the data to be written to the next pixel with reference to the first index. If the pixel connection structure is changed, the first index stored in the EEPROM may be changed by the data input through the ROM writer.

The present invention can set a second index for identifying an in-phase shift. For example, according to the present invention, the second index can be set to a number such as 1, 2, 3, 4, etc., as in the above-described example. The temperature controller 200 can determine the transition of data by anticipating the polarity reversal timing of the data with reference to the second index stored in the EEPROM.

12 and 13 are views showing an example of a temperature control method according to an embodiment of the present invention.

An example of applying heat generation cost modeling in the example of FIG. 12 will be described below.

The exiting cost modeling setting values, the indexes indicating the pixel connection structure and the inversion phase are as follows (steps S1 and S2).

- First index (pixel link structure): 36

- Second index (Inversion, assuming 4 dot inversion)

(1) - + + + + - - - -

(2) - - + + + + - - -

(3) - - - + + + + - - -

(4) - - - - + + + + -

- Data level per gradation Heating cost: 0.1

- Transition heating cost per gradation: 0.2

- Charge sharing transition weight: 0.5

- HVDD transition weight: 0.6

Here, it is assumed that the data is linear data that is modulated at a voltage level.

The heat cost and weight are proportional to the temperature contribution of the source drive IC (D-IC). It should be noted that the heating cost and weight are determined experimentally and may vary depending on the IC product and the driving characteristics of the display device, and thus are not limited to the above values.

In the example of FIG. 12, the in-phase phase-specific data level and transition course can be calculated (step S4). CS is a driving condition in which data is transited by the charge-share driving method. H is a driving condition in which data is transited by the HVDD driving method. N is a driving condition in which data is transited to a normal driving transition. CS is modeled as the sum of the current data and the next data as the polarity of the data changes. H is modeled as the difference between the current data and the next data in the HVDD driving condition of the source drive IC. N is modeled as the difference between the current data and the next data under normal driving transition conditions.

(N) - 115 (CS) - 105 (N) - 50 (N) - 120 (N) - (+) - + + + + H)

(2) - - + + + + - - -: 130 (H) - 130 (CS) - 20 (N) - 40 (N) H)

(3) - - + + + + - -: 130 (H) - 50 (H) - 100 (CS) - 40 (N) - 85 (H) H)

(4) - - - + + + + -: 130 (H) - 50 (H) - 20 (N) - 160 (CS) CS)

The heat generation cost per phase of the inversion is calculated as follows.

First heat cost calculation according to data level: (220 + 90 + 40 + 60 + 100 + 15 + 120 + 170 + 50) * 0.1 = 86.5

(N) + Charge sharing transition (CS) + HVDD transition (H)

(1) ((20 + 40 + 105 + 50) + (310 + 115) * 0.5 + (50 + 120) * 0.6)

(20 + 40 + 50) + (130 + 135) * 0.5 + (130 + 85 + 120) * 0.6) * 0.2 = 88.7

(3) ((40 + 105) + (100 + 290) * 0.5 + (130 + 50 + 85 + 120) * 0.6) * 0.2 = 114.2

(20 + 105 + 50) + (160 + 220) * 0.5 + (130 + 50 + 85) * 0.6) * 0.2 = 104.8

Here, 0.5 is the weight of the charge sharing and 0.6 is the weight of the HVDD drive transition.

Step S5 is omitted, and the minimum value among the heat generation cost values per phase of the above-described inversion version is calculated as a final cost as follows. Applying this example, the polarity of the data voltage is controlled in phase 2 of the inversion.

Final cost: 86.5 + 88.7 = 175.2

After the in-phase shift of the phase, if the maximum value of the heat generation cost does not satisfy the set temperature condition of the source drive IC in step S8, the gain is adjusted so as to lower the temperature to the threshold value or less. Assuming that the heat generation cost satisfying the set temperature is 150 or less, the gain can be calculated as follows.

gain = 150 / 175.2 = 0.86

This gain is multiplied by the input image data so that the data is adjusted low. In Fig. 13, the right drawing is data modulated by gain. When the data is modulated in this manner, the level of the data voltage output from the source drive IC and the size of the transition are reduced, thereby lowering the temperature and power consumption of the source drive IC.

Since the heat dissipation of the source drive IC is managed by an algorithm executed by the temperature control unit 200, the cost of the heat dissipation designing apparatus can be reduced. In addition, the temperature controller 200 can share hardware resources with the over-driving circuit for improving the response characteristics of the liquid crystal. Therefore, the logic circuit and memory resources added for the temperature controller 200 in the timing controller 101 can be minimized.

The present invention can use the index setting to model the heat generation cost for any pixel structure, so that even if the design of the display panel is changed, the temperature control unit 200 can be used as it is.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100; Display panel 101: Timing controller
102: Data driver 103: Gate driver
200: Temperature controller D-IC: Source drive IC

Claims (9)

A display panel in which data lines and gate lines are crossed and pixels are arranged in a matrix form;
One or more source drive ICs for converting received data into data voltages and supplying the data voltages to the data lines; And
A first index defining a pixel connection structure of the display panel, a second index defining an inversion phase controlling polarity of data, a first weight set according to a level of data, and a second weight set according to a transition size of the data, And a temperature that changes the gain multiplied by the input data based on the temperature of the source drive IC predicted by using the third weight according to the transition drive of the source drive IC and changes the phase of the inversion of the source drive IC A liquid crystal display comprising a control unit. The method according to claim 1,
The temperature control unit includes:
A memory for storing the indices and the weights;
And a logic circuit for predicting the temperature of the source drive IC using the indices and the weight values and lowering the gain to a value lower than a current value when the temperature of the source drive IC becomes higher than a predetermined temperature. 3. The method of claim 2,
The temperature control unit includes:
The temperature control unit receives the input data, the indices, and the weights, and calculates a first heating cost for the level of the input data according to each inversion phase and a second heating cost corresponding to a transition size of the input data, Calculating,
The sum of the first heat generation cost and the second heat generation cost for each channel of the source drive IC is divided and accumulated for each inversion phase to obtain an accumulated value for each channel of the heat generation cost,
The cumulative value for each channel obtained in each channel of the source drive IC is added in the pixel array region occupied by the source drive IC to calculate the heat generation cost sum,
And controlling the polarity of the data in an inversion phase having a minimum value among a sum of the heat generation costs of the source drive ICs separated by phases of the inversion,
And compares a maximum value of the heat generation cost totals with a preset threshold value, and adjusts the gain according to the comparison result. The method of claim 3,
The gain has a value between 0 and 1,
Wherein the gain is adjusted to a value less than 1 when the maximum value of the heat generation cost sum is less than 1 when the maximum value of the heat generation cost sum is less than the threshold while the value is close to 1 when the maximum value of the heat generation cost sum is less than the threshold value. 5. The method according to any one of claims 1 to 4,
The transition drive of the source drive IC
Charge-sharing drive and HVDD drive,
Wherein the third weight is set to a different value in the charge sharing drive and the HVDD drive. A first index defining a pixel connection structure of a display panel, a second index defining an inversion phase controlling polarity of data, a first weight set according to a level of data, a second weight set according to a transition size of the data, And setting a third weight according to a transition drive of the source drive IC;
Predicting the temperature of the source drive IC for driving the data lines of the display panel using the indices and the weight and adjusting the gain based on the temperature prediction result of the source drive IC; And
And modulating data to be transmitted to the source drive IC by multiplying the gain by the input data. The method according to claim 6,
Estimating the temperature of the source drive IC for driving the data lines of the display panel using the indices and the weight and adjusting the gain based on the temperature prediction result of the source drive IC,
Calculating the second heat generation cost according to the transition cost of the input data and the first heat generation cost for the level of the input data, receiving the input data, the indices, and the weight values;
Accumulating the sum of the first heat generation cost and the second heat generation cost for each channel of the source drive IC by an inversion phase to obtain an accumulation value for each channel of the heat generation cost;
Summing an accumulated value for each channel obtained in each channel of the source drive IC in a pixel array area occupied by the source drive IC to calculate an overall heat cost sum;
Controlling the polarity of the data in an inversion phase having a minimum value among the sum of the heat generation costs of the source drive IC separated by the inversion phase; And
Comparing the maximum value of the heat generation cost totals with a preset threshold value, and adjusting the gain according to the comparison result. 8. The method of claim 7,
The gain has a value between 0 and 1,
Wherein the gain is adjusted to a value lower than 1 when the maximum value of the heat generation cost sum is less than 1 when the maximum value of the total heat generation cost is greater than the threshold value, Way. 9. The method according to any one of claims 6 to 8,
The transition drive of the source drive IC
Charge-sharing drive and HVDD drive,
Wherein the third weight is set to a different value in the charge sharing drive and the HVDD drive.

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